ivpu_err
ivpu_err(vdev, "Failed to allocate context id: %d\n", ret);
ivpu_err(vdev, "Invalid NPU ready message: 0x%x\n", ipc_hdr.data_addr);
ivpu_err(vdev, "Failed to enable hw scheduler: %d", ret);
ivpu_err(vdev, "Failed to start the firmware: %d\n", ret);
ivpu_err(vdev, "Failed to boot the firmware: %d\n", ret);
ivpu_err(vdev, "Failed to allocate a MSI IRQ: %d\n", ret);
ivpu_err(vdev, "Failed to request an IRQ %d\n", ret);
ivpu_err(vdev, "Failed to map bar 0: %pe\n", vdev->regv);
ivpu_err(vdev, "Failed to map bar 4: %pe\n", vdev->regb);
ivpu_err(vdev, "Failed to set DMA mask: %d\n", ret);
ivpu_err(vdev, "Failed to enable PCI device: %d\n", ret);
ivpu_err(vdev, "Unknown NPU IP generation\n");
ivpu_err(vdev, "Unknown buttress generation\n");
ivpu_err(vdev, "Incompatible FW %s API version: %d.%d, required %d.0 or later\n",
ivpu_err(vdev, "Firmware file is too small: %zu\n", fw->file->size);
ivpu_err(vdev, "Invalid firmware header version: %u\n", fw_hdr->header_version);
ivpu_err(vdev, "Invalid boot params address: 0x%llx\n", boot_params_addr);
ivpu_err(vdev, "Invalid firmware version size: %u\n",
ivpu_err(vdev, "Invalid firmware version address: 0x%llx\n", fw_version_addr);
ivpu_err(vdev, "Invalid firmware runtime address: 0x%llx and size %llu\n",
ivpu_err(vdev, "Invalid image size: %llu\n", image_size);
ivpu_err(vdev, "Runtime address 0x%llx not page aligned\n", runtime_addr);
ivpu_err(vdev, "Runtime size %llu not page aligned\n", runtime_size);
ivpu_err(vdev, "Runtime size too small: %llu, image size: %llu\n",
ivpu_err(vdev, "Invalid firmware load address: 0x%llx and size %llu\n",
ivpu_err(vdev, "Invalid entry point: 0x%llx\n", fw_hdr->entry_point);
ivpu_err(vdev, "SHAVE NN firmware is too big: %u\n", fw_hdr->shave_nn_fw_size);
ivpu_err(vdev, "Invalid read-only section: start address 0x%llx, size %u\n",
ivpu_err(vdev, "Failed to create firmware boot params memory buffer\n");
ivpu_err(vdev, "Failed to create firmware version memory buffer\n");
ivpu_err(vdev, "Failed to create firmware runtime memory buffer\n");
ivpu_err(vdev, "Failed to set firmware image read-only\n");
ivpu_err(vdev, "Failed to create critical log buffer\n");
ivpu_err(vdev, "Failed to create verbose log buffer\n");
ivpu_err(vdev, "Failed to create shavenn buffer\n");
ivpu_err(vdev, "Failed to request firmware: %d\n", ret);
ivpu_err(vdev, "Failed to map BO in MMU: %d\n", ret);
ivpu_err(vdev, "Failed to allocate BO: %pe vpu_addr 0x%llx size %llu flags 0x%x\n",
ivpu_err(vdev, "Failed to allocate NPU address for BO: %pe ctx %u size %llu: %d\n",
ivpu_err(vdev, "Invalid runtime BO address 0x%llx size %llu\n", addr, size);
ivpu_err(vdev, "Failed to map BO in IOMMU: %ld\n", PTR_ERR(sgt));
ivpu_err(vdev, "Failed to map BO in IOMMU: %d\n", ret);
ivpu_err(vdev, "Invalid range: start 0x%llx size %llu\n", start, size);
ivpu_err(vdev, "Failed to enable workpoint: %d\n", ret);
ivpu_err(vdev, "Failed to configure host SS: %d\n", ret);
ivpu_err(vdev, "Timed out waiting for clock resource own ACK\n");
ivpu_err(vdev, "Failed to enable power domain: %d\n", ret);
ivpu_err(vdev, "Failed to enable AXI: %d\n", ret);
ivpu_err(vdev, "Failed to enable TOP NOC: %d\n", ret);
ivpu_err(vdev, "Failed to reset NPU IP\n");
ivpu_err(vdev, "Failed to disable workpoint\n");
ivpu_err(vdev, "Failed to reset NPU\n");
ivpu_err(vdev, "Failed to enter D0I3\n");
ivpu_err(vdev, "Failed to boot SOC CPU: %d\n", ret);
ivpu_err(vdev, "Invalid platform type: %d\n", platform);
ivpu_err(vdev, "Fuse: invalid (0x%x)\n", fuse);
ivpu_err(vdev, "Failed to sync before workpoint request: %d\n", ret);
ivpu_err(vdev, "Failed to sync after workpoint request: %d\n", ret);
ivpu_err(vdev, "Failed to send workpoint request: %d\n", ret);
ivpu_err(vdev, "Timed out waiting for PLL lock\n");
ivpu_err(vdev, "Timed out waiting for NPU ready status\n");
ivpu_err(vdev, "Timed out waiting for CDYN deassert\n");
ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret);
ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret);
ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret);
ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret);
ivpu_err(vdev, "Failed to enable D0i3: %d\n", ret);
ivpu_err(vdev, "Failed to disable D0i3: %d\n", ret);
ivpu_err(vdev, "Timed out waiting for TRIGGER bit\n");
ivpu_err(vdev, "Timed out waiting for RESET completion\n");
ivpu_err(vdev, "Wait for *_TRIGGER timed out\n");
ivpu_err(vdev, "Timed out waiting for RESET completion\n");
ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_HW_BTRS_MTL_ATS_ERR_LOG_0));
ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx",
ivpu_err(vdev, "ATS_ERR LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",
ivpu_err(vdev, "CFI0_ERR 0x%08x", REGB_RD32(VPU_HW_BTRS_LNL_CFI0_ERR_LOG));
ivpu_err(vdev, "CFI1_ERR 0x%08x", REGB_RD32(VPU_HW_BTRS_LNL_CFI1_ERR_LOG));
ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x",
ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x",
ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_HW_BTRS_MTL_ATS_ERR_LOG_0));
ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx",
ivpu_err(vdev, "ATS_ERR_LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",
ivpu_err(vdev, "CFI0_ERR_LOG 0x%08x\n", REGB_RD32(VPU_HW_BTRS_LNL_CFI0_ERR_LOG));
ivpu_err(vdev, "CFI1_ERR_LOG 0x%08x\n", REGB_RD32(VPU_HW_BTRS_LNL_CFI1_ERR_LOG));
ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x\n",
ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x\n",
ivpu_err(vdev, "Survivability IRQ\n");
ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ");
ivpu_err(vdev, "WDT MSS timeout detected\n");
ivpu_err(vdev, "WDT NCE timeout detected\n");
ivpu_err(vdev, "NOC Firewall irq detected\n");
ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ");
ivpu_err(vdev, "WDT MSS timeout detected\n");
ivpu_err(vdev, "WDT NCE timeout detected\n");
ivpu_err(vdev, "NOC Firewall irq detected\n");
ivpu_err(vdev, "Timed out waiting for NPU IP bar\n");
ivpu_err(vdev, "Failed qreqn check: %d\n", ret);
ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
ivpu_err(vdev, "Failed qdeny check %d\n", ret);
ivpu_err(vdev, "Failed HOST SS NOC QACCEPTN check: %d\n", ret);
ivpu_err(vdev, "Failed HOST SS NOC QDENY check: %d\n", ret);
ivpu_err(vdev, "Failed TOP NOC QACCEPTN check: %d\n", ret);
ivpu_err(vdev, "Failed TOP NOC QDENY check: %d\n", ret);
ivpu_err(vdev, "Unknown device ID\n");
ivpu_err(vdev, "Timed out waiting for power island status\n");
ivpu_err(vdev, "Failed TOP NOC QREQN check %d\n", ret);
ivpu_err(vdev, "Failed qacceptn check: %d\n", ret);
ivpu_err(vdev, "Failed qdeny check: %d\n", ret);
ivpu_err(vdev, "Failed to enable SOC CPU: %d\n", ret);
ivpu_err(vdev, "IPC resp result error: %d\n", rx_msg->jsm_msg->result);
ivpu_err(vdev, "Failed to allocate mem_tx\n");
ivpu_err(vdev, "Failed to allocate mem_rx\n");
ivpu_err(vdev, "Failed to create gen pool, %pe\n", ipc->mm_tx);
ivpu_err(vdev, "gen_pool_add failed, ret %d\n", ret);
ivpu_err(vdev, "Failed to initialize ipc->lock, ret %d\n", ret);
ivpu_err(vdev, "IPC message has no JSM payload\n");
ivpu_err(vdev, "Invalid JSM message result: %d\n", jsm_msg->result);
ivpu_err(vdev, "Failed to allocate command queue\n");
ivpu_err(vdev, "Failed to create primary preemption buffer\n");
ivpu_err(vdev, "Failed to create secondary preemption buffer\n");
ivpu_err(vdev, "Failed to create a fence\n");
ivpu_err(vdev, "Failed to register command queue: %d\n", ret);
ivpu_err(vdev, "Failed to initialize preemption buffers for job %d: %d\n",
ivpu_err(vdev, "Failed to allocate cdtab: %d\n", ret);
ivpu_err(vdev, "Failed to allocate strtab: %d\n", ret);
ivpu_err(vdev, "Failed to allocate cmdq: %d\n", ret);
ivpu_err(vdev, "Failed to allocate evtq: %d\n", ret);
ivpu_err(vdev, "Failed to write MMU CMD %s\n", name);
ivpu_err(vdev, "Timed out waiting for MMU consumer: %d, error: %s\n", ret,
ivpu_err(vdev, "Failed to initialize strtab: %d\n", ret);
ivpu_err(vdev, "Failed to resume MMU: %d\n", ret);
ivpu_err(vdev, "Failed to reset MMU: %d\n", ret);
ivpu_err(vdev, "Failed to invalidate TLB for ctx %u: %d\n", ctx->id, ret);
ivpu_err(vdev, "Scatter-gather table size exceeds buffer object size\n");
ivpu_err(vdev, "Failed to map context pages\n");
ivpu_err(vdev, "Scatter-gather table size too small to cover buffer object size\n");
ivpu_err(vdev, "Failed to set context descriptor for context %u: %d\n",
ivpu_err(vdev, "Failed to invalidate TLB for ctx %u: %d\n", ctx->id, ret);
ivpu_err(vdev, "Failed to allocate root page table for reserved context\n");
ivpu_err(vdev, "Failed to set context descriptor for reserved context\n");
ivpu_err(vdev, "Failed to resume MMU: %d\n", ret);
ivpu_err(vdev, "Failed to resume the FW: %d\n", ret);
ivpu_err(vdev, "Failed to resume NPU: %d\n", ret);
ivpu_err(vdev, "Recovering the NPU (reset #%d)\n", atomic_read(&vdev->pm->reset_counter));
ivpu_err(vdev, "Recovery triggered by %s\n", reason);
ivpu_err(vdev, "Recovery not available when disable_recovery param is set\n");
ivpu_err(vdev, "Job timeout detected, heartbeat not progressed\n");
ivpu_err(vdev, "Job timeout detected, heartbeat limit (%lld) exceeded\n",
ivpu_err(vdev, "Failed to enter idle on system suspend\n");
ivpu_err(vdev, "Failed to resume: %d\n", ret);
ivpu_err(vdev, "NPU is not idle before autosuspend\n");
ivpu_err(vdev, "Failed to prepare for d0i3: %d\n", ret_d0i3);
ivpu_err(vdev, "Failed to suspend NPU: %d\n", ret);
ivpu_err(vdev, "Forcing cold boot due to previous errors\n");
ivpu_err(vdev, "Failed to set RESUME state: %d\n", ret);
ivpu_err(vdev, "Failed to resume NPU: %d\n", ret);
ivpu_err(vdev, "Failed to shutdown NPU: %d\n", ret);
ivpu_err(vdev, "Failed to power up HW: %d\n", ret);