irq_domain_set_hwirq_and_chip
irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
return irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, &xive_irq_chip, xd);
return irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
irq_domain_set_hwirq_and_chip(domain, virq + i, sgi + i,
ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip,
ret = irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
irq_domain_set_hwirq_and_chip(d, virq + i, hwirq + i,
irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
irq_domain_set_hwirq_and_chip(domain, virq + i,
irq_domain_set_hwirq_and_chip(domain, virq + i, i,
irq_domain_set_hwirq_and_chip(domain, virq + i, i,
irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
irq_domain_set_hwirq_and_chip(domain, virq, i,
irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &ls_extirq_chip,
irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &mchp_eic_chip, eic);
irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
ret = irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq,
ret = irq_domain_set_hwirq_and_chip(domain->parent, virq + i, hwirq,
err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq,
ret = irq_domain_set_hwirq_and_chip(d->parent, virq + i, hwirq,
irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
irq_domain_set_hwirq_and_chip(domain, virq, hwirq, info->chip, info->chip_data);
irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
irq_domain_set_hwirq_and_chip(domain, virq, fwspec->param[0],
irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &owl_sirq_chip,
ret = irq_domain_set_hwirq_and_chip(domain, virq, pin,
ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &priv->chip,
ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, (void *)(uintptr_t)tint);
ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, NULL);
ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, (void *)(uintptr_t)tint);
irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
irq_domain_set_hwirq_and_chip(dom, virq, hwirq, &exiu_irq_chip, info);
irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data);
irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
irq_domain_set_hwirq_and_chip(d, virq + i, 0, &hv_msi_irq_chip, NULL);
irq_domain_set_hwirq_and_chip(domain, virq + i,
irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
err = irq_domain_set_hwirq_and_chip(domain, virq,
err = irq_domain_set_hwirq_and_chip(domain, virq,
int irq_domain_set_hwirq_and_chip(struct irq_domain *domain, unsigned int virq,
EXPORT_SYMBOL_GPL(irq_domain_set_hwirq_and_chip);
irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, chip_data);
irq_domain_set_hwirq_and_chip(domain, virq, hwirq, info->chip,