irq_reg_writel
irq_reg_writel(gc, reg_val, ct->regs.mask);
irq_reg_writel(gc, reg_val, ct->regs.mask);
irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
irq_reg_writel(gc, gc->mask_cache, AT91_AIC_IDCR);
irq_reg_writel(gc, gc->wake_active, AT91_AIC_IECR);
irq_reg_writel(gc, gc->wake_active, AT91_AIC_IDCR);
irq_reg_writel(gc, gc->mask_cache, AT91_AIC_IECR);
irq_reg_writel(gc, 0xffffffff, AT91_AIC_IDCR);
irq_reg_writel(gc, 0xffffffff, AT91_AIC_ICCR);
irq_reg_writel(gc, 0, AT91_AIC_EOICR);
irq_reg_writel(gc, 0xffffffff, AT91_AIC_SPU);
irq_reg_writel(gc, 0, AT91_AIC_DCR);
irq_reg_writel(gc, 0xffffffff, AT91_AIC_IDCR);
irq_reg_writel(gc, 0xffffffff, AT91_AIC_ICCR);
irq_reg_writel(gc, i, AT91_AIC_SVR(i));
irq_reg_writel(gc, smr, AT91_AIC_SMR(*out_hwirq));
irq_reg_writel(gc, 0, AT91_AIC_EOICR);
irq_reg_writel(gc, d->mask, AT91_AIC_ISCR);
irq_reg_writel(gc, smr, AT91_AIC_SMR(d->hwirq));
irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);
irq_reg_writel(gc, 1, AT91_AIC5_IECR);
irq_reg_writel(bgc, d->hwirq, AT91_AIC5_SSR);
irq_reg_writel(bgc, 1, AT91_AIC5_ISCR);
irq_reg_writel(bgc, d->hwirq, AT91_AIC5_SSR);
irq_reg_writel(bgc, smr, AT91_AIC5_SMR);
irq_reg_writel(bgc, i, AT91_AIC5_SSR);
irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);
irq_reg_writel(bgc, 1, AT91_AIC5_IECR);
irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);
irq_reg_writel(bgc, 0xffffffff, AT91_AIC5_SPU);
irq_reg_writel(bgc, i, AT91_AIC5_SSR);
irq_reg_writel(bgc, i, AT91_AIC5_SVR);
irq_reg_writel(bgc, smr_cache[i], AT91_AIC5_SMR);
irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);
irq_reg_writel(bgc, 1, AT91_AIC5_IECR);
irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);
irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);
irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);
irq_reg_writel(bgc, 1, AT91_AIC5_ICCR);
irq_reg_writel(gc, 0, AT91_AIC5_EOICR);
irq_reg_writel(gc, 0xffffffff, AT91_AIC5_SPU);
irq_reg_writel(gc, 0, AT91_AIC5_DCR);
irq_reg_writel(gc, i, AT91_AIC5_SSR);
irq_reg_writel(gc, i, AT91_AIC5_SVR);
irq_reg_writel(gc, 1, AT91_AIC5_IDCR);
irq_reg_writel(gc, 1, AT91_AIC5_ICCR);
irq_reg_writel(bgc, *out_hwirq, AT91_AIC5_SSR);
irq_reg_writel(bgc, smr, AT91_AIC5_SMR);
irq_reg_writel(bgc, 0, AT91_AIC5_EOICR);
irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);
irq_reg_writel(gc, 1, AT91_AIC5_IDCR);
irq_reg_writel(gc, data->irq_fwd_mask[idx],
irq_reg_writel(gc, gc->mask_cache | gc->wake_active, ct->regs.mask);
irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);
irq_reg_writel(gc, gc->wake_active, ct->regs.enable);
irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,
irq_reg_writel(gc, b->saved_mask, ct->regs.disable);
irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);
irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
irq_reg_writel(gc, irq_reg_readl(gc, ifr) & ~mask, ifr);
irq_reg_writel(gc, IRQ_MSK(32), JZ_REG_INTC_SET_MASK);
irq_reg_writel(gc, map, chip_regs->reg_off_map);
irq_reg_writel(gc, ~0U, chip_regs->reg_off_ena_clr);
irq_reg_writel(gc, ~0U, gc->chip_types[0].regs.disable);
irq_reg_writel(gc, ~0U, gc->chip_types[0].regs.ack);
irq_reg_writel(gc, map, chip_regs->reg_off_map);
irq_reg_writel(gc, 0, p->reg_off_ena);
irq_reg_writel(gc, 0xffffffff, p->reg_off_sticky);
irq_reg_writel(gc, BIT(0), p->reg_off_ena_irq0);
irq_reg_writel(gc, mask, p->reg_off_sticky);
irq_reg_writel(gc, mask, p->reg_off_ena_set);
irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
irq_reg_writel(gc, val, off);
irq_reg_writel(gc, val, reg);
irq_reg_writel(gc, mask, ct->regs.enable);
irq_reg_writel(gc, mask, ct->regs.ack);
irq_reg_writel(gc, mask, ct->regs.ack);
irq_reg_writel(gc, mask, ct->regs.disable);
irq_reg_writel(gc, mask, ct->regs.ack);
irq_reg_writel(gc, mask, ct->regs.eoi);
irq_reg_writel(gc, mask, ct->regs.disable);
irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);