irq_reg_readl
reg_val = irq_reg_readl(gc, ct->regs.mask);
reg_val = irq_reg_readl(gc, ct->regs.mask);
bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
smr = irq_reg_readl(gc, AT91_AIC_SMR(*out_hwirq));
irqnr = irq_reg_readl(gc, AT91_AIC_IVR);
irqstat = irq_reg_readl(gc, AT91_AIC_ISR);
smr = irq_reg_readl(gc, AT91_AIC_SMR(d->hwirq));
smr = irq_reg_readl(bgc, AT91_AIC5_SMR);
smr_cache[i] = irq_reg_readl(bgc, AT91_AIC5_SMR);
smr = irq_reg_readl(bgc, AT91_AIC5_SMR);
irqnr = irq_reg_readl(bgc, AT91_AIC5_IVR);
irqstat = irq_reg_readl(bgc, AT91_AIC5_ISR);
gc->mask_cache = irq_reg_readl(gc, ct->regs.mask);
pending = irq_reg_readl(gc, b->stat_offset[idx]) & gc->mask_cache &
b->saved_mask = irq_reg_readl(gc, ct->regs.mask);
status = irq_reg_readl(b->gc, b->status_offset) &
~(irq_reg_readl(b->gc, b->mask_offset));
irq_reg_writel(gc, irq_reg_readl(gc, ifr) & ~mask, ifr);
status = irq_reg_readl(gc, IC_INT0STATUS_LO);
status = irq_reg_readl(gc, IC_INT0STATUS_XLO);
pending = irq_reg_readl(idtpic->gc, IDT_PIC_IRQ_PEND);
pending = irq_reg_readl(gc, JZ_REG_INTC_PENDING);
ident = irq_reg_readl(gc, chip_regs->reg_off_ident);
map = irq_reg_readl(gc, chip_regs->reg_off_map);
map = irq_reg_readl(gc, chip_regs->reg_off_map);
u32 reg = irq_reg_readl(gc, ICPU_CFG_INTR_DST_INTR_IDENT(p, 0));
val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 0)) |
irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 1));
return irq_reg_readl(gc, stm32_bank->rpr_ofst);
rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
return irq_reg_readl(gc, off);
return irq_reg_readl(gc, reg);
*mskptr = irq_reg_readl(gc, mskreg);