irq_map
static int irq_map[2][12] = {
irq = irq_map[dev->bus->number][PCI_SLOT(dev->devfn)];
.map = irq_map,
struct kvmppc_irq_map *irq_map,
struct kvmppc_irq_map *irq_map;
irq_map = &pimap->mapped[i];
irq_map->v_hwirq = guest_gsi;
irq_map->desc = desc;
irq_map->r_hwirq = (unsigned int)irqd_to_hwirq(host_data);
kvmppc_xics_set_mapped(kvm, guest_gsi, irq_map->r_hwirq);
irq_map->r_hwirq = 0;
struct kvmppc_irq_map *irq_map;
irq_map = get_irqmap(pimap, xisr);
if (!irq_map)
return kvmppc_deliver_irq_passthru(vcpu, xirr, irq_map, pimap, again);
struct kvmppc_irq_map *irq_map,
irq = irq_map->v_hwirq;
kvmppc_rm_handle_irq_desc(irq_map->desc);
icp_eoi(irq_desc_get_irq_data(irq_map->desc), irq_map->r_hwirq, xirr, again);
ppc4xx_hsta_msi.irq_map = kmalloc_objs(int, irq_count);
if (!ppc4xx_hsta_msi.irq_map) {
ppc4xx_hsta_msi.irq_map[irq] =
if (!ppc4xx_hsta_msi.irq_map[irq]) {
kfree(ppc4xx_hsta_msi.irq_map);
int *irq_map;
hwirq = ppc4xx_hsta_msi.irq_map[irq];
if (ppc4xx_hsta_msi.irq_map[irq] == hwirq)
extern struct irq_bucket *irq_map[SUN4D_MAX_IRQ];
struct irq_bucket *irq_map[SUN4D_MAX_IRQ];
p->next = irq_map[pil];
irq_map[pil] = p;
pnext = &irq_map[p->pil];
p = irq_map[pil];
p = irq_map[eirq];
return priv->irq_map[pin];
generic_handle_irq(priv->irq_map[i]);
priv->irq_map[0] = grpci1_build_device_irq(1);
priv->irq_map[1] = grpci1_build_device_irq(2);
priv->irq_map[2] = grpci1_build_device_irq(3);
priv->irq_map[3] = grpci1_build_device_irq(4);
priv->irq_map[0], priv->irq_map[1], priv->irq_map[2],
priv->irq_map[3]);
unsigned char irq_map[4]; /* GRPCI nexus PCI INTX# IRQs */
unsigned char irq_map[4];
return priv->irq_map[pin];
generic_handle_irq(priv->irq_map[i]);
priv->irq_map[0] = grpci2_build_device_irq(1);
priv->irq_map[1] = grpci2_build_device_irq(2);
priv->irq_map[2] = grpci2_build_device_irq(3);
priv->irq_map[3] = grpci2_build_device_irq(4);
priv->irq_map[i] = ofdev->archdata.irqs[i];
priv->virq_err = priv->irq_map[0];
priv->virq_dma = priv->irq_map[0];
p = irq_map[pil];
p = irq_map[pil];
struct intel_gvt_irq_map *map = irq->irq_map;
for (map = irq->irq_map; map->up_irq_bit != -1; map++) {
for (map = irq->irq_map; map->up_irq_bit != -1; map++) {
irq->irq_map = gen8_irq_map;
struct intel_gvt_irq_map *irq_map;
cb->irq_map[i] = IRQ_FREE;
cb->irq_map[d->hwirq] = IRQ_FREE;
cb->irq_map = kcalloc(max, sizeof(int), GFP_KERNEL);
if (!cb->irq_map)
cb->irq_map[i] = IRQ_FREE;
cb->irq_map[entry] = IRQ_RESERVED;
cb->irq_map[entry] = IRQ_SKIP;
if (cb->irq_map[i] == IRQ_RESERVED)
if (cb->irq_map[i] == IRQ_RESERVED ||
cb->irq_map[i] == IRQ_SKIP)
kfree(cb->irq_map);
uint *irq_map;
if (cb->irq_map[i] == IRQ_FREE) {
cb->irq_map[i] = hwirq;
per_cpu_ptr(irq_map, adata->cpu)[adata->vec] = irq_data_to_desc(data);
this_cpu_write(irq_map[vector], NULL);
d = this_cpu_read(irq_map[vector]);
per_cpu_ptr(irq_map, adata->cpu)[adata->vec] = irq_data_to_desc(irqd);
per_cpu(irq_map, adata->cpu)[adata->vec] = NULL;
per_cpu(irq_map, adata->prev_cpu)[adata->prev_vec] = NULL;
static DEFINE_PER_CPU(struct irq_desc * [NR_VECTORS], irq_map);
int irq_map; /* IRQ map from EEPROM */
lp->irq_map = 0xffff;
lp->irq_map = CS8900_IRQ_MAP; /* fixed IRQ map for CS8900 */
lp->irq_map = ((irq_map_buff[0] >> 8) |
if ((1 << i) & lp->irq_map) {
if (((1 << dev->irq) & lp->irq_map) == 0) {
dev->name, dev->irq, lp->irq_map);
fdev->irq_map = bitmap_zalloc(fdev->num_irqs, GFP_KERNEL);
if (!fdev->irq_map)
__set_bit(0, fdev->irq_map);
for_each_clear_bit(b, fdev->irq_map, fdev->num_irqs) {
__set_bit(b, fdev->irq_map);
__clear_bit(irq_indices[i], fdev->irq_map);
bitmap_free(fdev->irq_map);
bitmap_free(fdev->irq_map);
unsigned long *irq_map;
struct msi_map irq_map;
irq_map = pci_msix_alloc_irq_at(pdev, i, NULL);
if (!irq_map.virq) {
err = irq_map.index;
.map = irq_map,
static const struct mt792x_irq_map irq_map = {
dev->irq_map = &irq_map;
mt76_wr(dev, irq_map.host_irq_enable, 0);
mt76_wr(dev, dev->irq_map->host_irq_enable, 0);
dev->irq_map->tx.all_complete_mask |
mt76_wr(dev, dev->irq_map->host_irq_enable, 0);
mt76_wr(dev, dev->irq_map->host_irq_enable,
dev->irq_map->tx.all_complete_mask |
static const struct mt792x_irq_map irq_map = {
dev->irq_map = &irq_map;
mt76_wr(dev, irq_map.host_irq_enable, 0);
mt76_wr(dev, dev->irq_map->host_irq_enable, 0);
dev->irq_map->tx.all_complete_mask |
mt76_wr(dev, dev->irq_map->host_irq_enable,
dev->irq_map->tx.all_complete_mask |
const struct mt792x_irq_map *irq_map = dev->irq_map;
mt76_wr(dev, dev->irq_map->host_irq_enable, 0);
if (irq_map->rx.data_complete_mask)
if (irq_map->rx.wm_complete_mask)
if (irq_map->rx.wm2_complete_mask)
if (irq_map->tx.all_complete_mask)
const struct mt792x_irq_map *irq_map;
dev->irq_map->tx.all_complete_mask |
dev->irq_map->rx.data_complete_mask |
dev->irq_map->rx.wm2_complete_mask |
dev->irq_map->rx.wm_complete_mask |
mt76_wr(dev, dev->irq_map->host_irq_enable, 0);
mt76_wr(dev, dev->irq_map->host_irq_enable, 0);
const struct mt792x_irq_map *irq_map = dev->irq_map;
dev->irq_map->tx.all_complete_mask);
mt76_wr(dev, irq_map->host_irq_enable, 0);
mask |= intr & (irq_map->rx.data_complete_mask |
irq_map->rx.wm_complete_mask |
irq_map->rx.wm2_complete_mask);
if (intr & dev->irq_map->tx.mcu_complete_mask)
mask |= dev->irq_map->tx.mcu_complete_mask;
mask |= irq_map->rx.data_complete_mask;
intr |= irq_map->rx.data_complete_mask;
mt76_set_irq_mask(&dev->mt76, irq_map->host_irq_enable, mask, 0);
if (intr & dev->irq_map->tx.all_complete_mask)
if (intr & irq_map->rx.wm_complete_mask)
if (intr & irq_map->rx.wm2_complete_mask)
if (intr & irq_map->rx.data_complete_mask)
const struct mt792x_irq_map *irq_map = dev->irq_map;
mt76_connac_irq_enable(mdev, irq_map->rx.data_complete_mask);
mt76_connac_irq_enable(mdev, irq_map->rx.wm2_complete_mask);
mt76_connac_irq_enable(mdev, irq_map->rx.wm_complete_mask);
int *irq_map; /* v2 hw */
&hisi_hba->irq_map);
irq = hisi_hba->irq_map[i + 1]; /* Phy up/down is irq1 */
irq = hisi_hba->irq_map[phy_no + 72];
irq = hisi_hba->irq_map[fatal_no + 81];
cq->irq_no = hisi_hba->irq_map[queue_no + 96];
mask = irq_get_affinity_mask(hisi_hba->irq_map[96 + queue]);