drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

149

static const struct dce_ipp_registers ipp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

150

ipp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

151

ipp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

152

ipp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

153

ipp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

154

ipp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

155

ipp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

620

&ipp_regs[inst], &ipp_shift, &ipp_mask);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

181

static const struct dce_ipp_registers ipp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

182

ipp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

183

ipp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

184

ipp_regs(2)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

655

&ipp_regs[inst], &ipp_shift, &ipp_mask);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

190

static const struct dce_ipp_registers ipp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

191

ipp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

192

ipp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

193

ipp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

194

ipp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

195

ipp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

196

ipp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

679

&ipp_regs[inst], &ipp_shift, &ipp_mask);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

189

static const struct dce_ipp_registers ipp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

190

ipp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

191

ipp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

192

ipp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

193

ipp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

194

ipp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

195

ipp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

764

&ipp_regs[inst], &ipp_shift, &ipp_mask);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

166

static const struct dce_ipp_registers ipp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

167

ipp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

168

ipp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

169

ipp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

170

ipp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

171

ipp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

172

ipp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

820

&ipp_regs[inst], &ipp_shift, &ipp_mask);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

165

static const struct dce_ipp_registers ipp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

166

ipp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

167

ipp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

168

ipp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

169

ipp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

170

ipp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

171

ipp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

826

&ipp_regs[inst], &ipp_shift, &ipp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

299

static const struct dcn10_ipp_registers ipp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

300

ipp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

301

ipp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

302

ipp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

303

ipp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

627

&ipp_regs[inst], &ipp_shift, &ipp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

358

static const struct dcn10_ipp_registers ipp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

359

ipp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

360

ipp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

361

ipp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

362

ipp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

363

ipp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

364

ipp_regs(5),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

793

&ipp_regs[inst], &ipp_shift, &ipp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

420

static const struct dcn10_ipp_registers ipp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

421

ipp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

422

ipp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

423

ipp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

424

ipp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

660

&ipp_regs[inst], &ipp_shift, &ipp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

412

static const struct dcn10_ipp_registers ipp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

413

ipp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

414

ipp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

415

ipp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

416

ipp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

515

&ipp_regs[inst], &ipp_shift, &ipp_mask);