drivers/gpu/drm/gma500/cdv_intel_dp.c

1005

intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1007

lane_count = intel_dp->lane_count;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1010

lane_count = intel_dp->lane_count;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1041

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1044

intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1045

intel_dp->DP |= intel_dp->color_range;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1048

intel_dp->DP |= DP_SYNC_HS_HIGH;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1050

intel_dp->DP |= DP_SYNC_VS_HIGH;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1052

intel_dp->DP |= DP_LINK_TRAIN_OFF;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1054

switch (intel_dp->lane_count) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1056

intel_dp->DP |= DP_PORT_WIDTH_1;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1059

intel_dp->DP |= DP_PORT_WIDTH_2;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1062

intel_dp->DP |= DP_PORT_WIDTH_4;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1065

if (intel_dp->has_audio)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1066

intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1068

memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1069

intel_dp->link_configuration[0] = intel_dp->link_bw;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1070

intel_dp->link_configuration[1] = intel_dp->lane_count;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1075

if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&

drivers/gpu/drm/gma500/cdv_intel_dp.c

1076

(intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1077

intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1078

intel_dp->DP |= DP_ENHANCED_FRAMING;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1083

intel_dp->DP |= DP_PIPEB_SELECT;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1085

REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN));

drivers/gpu/drm/gma500/cdv_intel_dp.c

1086

DRM_DEBUG_KMS("DP expected reg is %x\n", intel_dp->DP);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1107

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1111

if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1169

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1171

uint32_t dp_reg = REG_READ(intel_dp->output_reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1230

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1233

intel_dp->link_status,

drivers/gpu/drm/gma500/cdv_intel_dp.c

1275

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1280

for (lane = 0; lane < intel_dp->lane_count; lane++) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1281

uint8_t this_v = cdv_intel_get_adjust_request_voltage(intel_dp->link_status, lane);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1282

uint8_t this_p = cdv_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1297

intel_dp->train_set[lane] = v | p;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1334

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1339

lane_align = cdv_intel_dp_link_status(intel_dp->link_status,

drivers/gpu/drm/gma500/cdv_intel_dp.c

1343

for (lane = 0; lane < intel_dp->lane_count; lane++) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1344

lane_status = cdv_intel_get_lane_status(intel_dp->link_status, lane);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1358

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1360

REG_WRITE(intel_dp->output_reg, dp_reg_value);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1361

REG_READ(intel_dp->output_reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1382

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1386

intel_dp->train_set,

drivers/gpu/drm/gma500/cdv_intel_dp.c

1387

intel_dp->lane_count);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1389

if (ret != intel_dp->lane_count) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1391

intel_dp->train_set[0], intel_dp->lane_count);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1401

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1405

if (intel_dp->output_reg == DP_B)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1467

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1473

uint32_t DP = intel_dp->DP;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1481

REG_WRITE(intel_dp->output_reg, reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1482

REG_READ(intel_dp->output_reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1488

intel_dp->link_configuration,

drivers/gpu/drm/gma500/cdv_intel_dp.c

1491

memset(intel_dp->train_set, 0, 4);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1502

intel_dp->train_set[0],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1503

intel_dp->link_configuration[0],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1504

intel_dp->link_configuration[1]);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1509

cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1519

intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1520

intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1522

if (cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1529

for (i = 0; i < intel_dp->lane_count; i++)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1530

if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1532

if (i == intel_dp->lane_count)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1536

if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1542

voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1550

DRM_DEBUG_KMS("failure in DP pattern 1 training, train set %x\n", intel_dp->train_set[0]);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1553

intel_dp->DP = DP;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1560

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1563

uint32_t DP = intel_dp->DP;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1575

intel_dp->train_set[0],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1576

intel_dp->link_configuration[0],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1577

intel_dp->link_configuration[1]);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1592

cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1601

intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1602

intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1605

if (!cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1633

REG_WRITE(intel_dp->output_reg, reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1634

REG_READ(intel_dp->output_reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1643

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1644

uint32_t DP = intel_dp->DP;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1646

if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1654

REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1656

REG_READ(intel_dp->output_reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1660

REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1661

REG_READ(intel_dp->output_reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1666

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1670

if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd,

drivers/gpu/drm/gma500/cdv_intel_dp.c

1671

sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))

drivers/gpu/drm/gma500/cdv_intel_dp.c

1673

if (intel_dp->dpcd[DP_DPCD_REV] != 0)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1678

intel_dp->dpcd[0], intel_dp->dpcd[1],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1679

intel_dp->dpcd[2], intel_dp->dpcd[3]);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1693

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1698

intel_dp->has_audio = false;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1709

if (intel_dp->force_audio) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1710

intel_dp->has_audio = intel_dp->force_audio > 0;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1712

edid = drm_get_edid(connector, &intel_dp->adapter);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1714

intel_dp->has_audio = drm_detect_monitor_audio(edid);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1727

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1733

edid = drm_get_edid(connector, &intel_dp->adapter);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1746

if (edp && !intel_dp->panel_fixed_mode) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1751

intel_dp->panel_fixed_mode =

drivers/gpu/drm/gma500/cdv_intel_dp.c

1760

if (!intel_dp->panel_fixed_mode && dev_priv->lfp_lvds_vbt_mode) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1761

intel_dp->panel_fixed_mode =

drivers/gpu/drm/gma500/cdv_intel_dp.c

1763

if (intel_dp->panel_fixed_mode) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1764

intel_dp->panel_fixed_mode->type |=

drivers/gpu/drm/gma500/cdv_intel_dp.c

1768

if (intel_dp->panel_fixed_mode != NULL) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1770

mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1783

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1791

edid = drm_get_edid(connector, &intel_dp->adapter);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1809

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1820

if (i == intel_dp->force_audio)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1823

intel_dp->force_audio = i;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1830

if (has_audio == intel_dp->has_audio)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1833

intel_dp->has_audio = has_audio;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1838

if (val == !!intel_dp->color_range)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1841

intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1863

struct cdv_intel_dp *intel_dp = gma_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1867

kfree(intel_dp->panel_fixed_mode);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1868

intel_dp->panel_fixed_mode = NULL;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1870

i2c_del_adapter(&intel_dp->adapter);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1952

struct cdv_intel_dp *intel_dp;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1962

intel_dp = kzalloc_obj(struct cdv_intel_dp);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1963

if (!intel_dp)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1983

gma_encoder->dev_priv=intel_dp;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1984

intel_dp->encoder = gma_encoder;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1985

intel_dp->output_reg = output_reg;

drivers/gpu/drm/gma500/cdv_intel_dp.c

2052

intel_dp->panel_power_up_delay = cur.t1_t3 / 10;

drivers/gpu/drm/gma500/cdv_intel_dp.c

2053

intel_dp->backlight_on_delay = cur.t8 / 10;

drivers/gpu/drm/gma500/cdv_intel_dp.c

2054

intel_dp->backlight_off_delay = cur.t9 / 10;

drivers/gpu/drm/gma500/cdv_intel_dp.c

2055

intel_dp->panel_power_down_delay = cur.t10 / 10;

drivers/gpu/drm/gma500/cdv_intel_dp.c

2056

intel_dp->panel_power_cycle_delay = (cur.t11_t12 - 1) * 100;

drivers/gpu/drm/gma500/cdv_intel_dp.c

2059

intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,

drivers/gpu/drm/gma500/cdv_intel_dp.c

2060

intel_dp->panel_power_cycle_delay);

drivers/gpu/drm/gma500/cdv_intel_dp.c

2063

intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);

drivers/gpu/drm/gma500/cdv_intel_dp.c

2068

intel_dp->dpcd,

drivers/gpu/drm/gma500/cdv_intel_dp.c

2069

sizeof(intel_dp->dpcd));

drivers/gpu/drm/gma500/cdv_intel_dp.c

2079

intel_dp->dpcd[0], intel_dp->dpcd[1],

drivers/gpu/drm/gma500/cdv_intel_dp.c

2080

intel_dp->dpcd[2], intel_dp->dpcd[3]);

drivers/gpu/drm/gma500/cdv_intel_dp.c

324

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

327

if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

328

max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;

drivers/gpu/drm/gma500/cdv_intel_dp.c

342

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

343

int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];

drivers/gpu/drm/gma500/cdv_intel_dp.c

380

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

383

if (intel_dp->panel_on) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

394

msleep(intel_dp->panel_power_up_delay);

drivers/gpu/drm/gma500/cdv_intel_dp.c

415

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

418

if (intel_dp->panel_on)

drivers/gpu/drm/gma500/cdv_intel_dp.c

431

intel_dp->panel_on = false;

drivers/gpu/drm/gma500/cdv_intel_dp.c

433

intel_dp->panel_on = true;

drivers/gpu/drm/gma500/cdv_intel_dp.c

434

msleep(intel_dp->panel_power_up_delay);

drivers/gpu/drm/gma500/cdv_intel_dp.c

443

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

452

intel_dp->panel_on = false;

drivers/gpu/drm/gma500/cdv_intel_dp.c

467

msleep(intel_dp->panel_power_cycle_delay);

drivers/gpu/drm/gma500/cdv_intel_dp.c

494

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

504

msleep(intel_dp->backlight_off_delay);

drivers/gpu/drm/gma500/cdv_intel_dp.c

512

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

517

if (is_edp(encoder) && intel_dp->panel_fixed_mode) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

518

if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)

drivers/gpu/drm/gma500/cdv_intel_dp.c

520

if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)

drivers/gpu/drm/gma500/cdv_intel_dp.c

571

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

572

uint32_t output_reg = intel_dp->output_reg;

drivers/gpu/drm/gma500/cdv_intel_dp.c

752

struct cdv_intel_dp *intel_dp = container_of(adapter,

drivers/gpu/drm/gma500/cdv_intel_dp.c

755

struct gma_encoder *encoder = intel_dp->encoder;

drivers/gpu/drm/gma500/cdv_intel_dp.c

848

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

853

intel_dp->algo.running = false;

drivers/gpu/drm/gma500/cdv_intel_dp.c

854

intel_dp->algo.address = 0;

drivers/gpu/drm/gma500/cdv_intel_dp.c

855

intel_dp->algo.aux_ch = cdv_intel_dp_i2c_aux_ch;

drivers/gpu/drm/gma500/cdv_intel_dp.c

857

memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));

drivers/gpu/drm/gma500/cdv_intel_dp.c

858

intel_dp->adapter.owner = THIS_MODULE;

drivers/gpu/drm/gma500/cdv_intel_dp.c

859

strscpy(intel_dp->adapter.name, name);

drivers/gpu/drm/gma500/cdv_intel_dp.c

860

intel_dp->adapter.algo_data = &intel_dp->algo;

drivers/gpu/drm/gma500/cdv_intel_dp.c

861

intel_dp->adapter.dev.parent = connector->base.kdev;

drivers/gpu/drm/gma500/cdv_intel_dp.c

865

ret = i2c_dp_aux_add_bus(&intel_dp->adapter);

drivers/gpu/drm/gma500/cdv_intel_dp.c

896

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

904

if (is_edp(intel_encoder) && intel_dp->panel_fixed_mode) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

905

cdv_intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);

drivers/gpu/drm/gma500/cdv_intel_dp.c

906

refclock = intel_dp->panel_fixed_mode->clock;

drivers/gpu/drm/gma500/cdv_intel_dp.c

915

intel_dp->link_bw = bws[clock];

drivers/gpu/drm/gma500/cdv_intel_dp.c

916

intel_dp->lane_count = lane_count;

drivers/gpu/drm/gma500/cdv_intel_dp.c

917

adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);

drivers/gpu/drm/gma500/cdv_intel_dp.c

920

intel_dp->link_bw, intel_dp->lane_count,

drivers/gpu/drm/gma500/cdv_intel_dp.c

928

intel_dp->lane_count = max_lane_count;

drivers/gpu/drm/gma500/cdv_intel_dp.c

929

intel_dp->link_bw = bws[max_clock];

drivers/gpu/drm/gma500/cdv_intel_dp.c

930

adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);

drivers/gpu/drm/gma500/cdv_intel_dp.c

933

intel_dp->link_bw, intel_dp->lane_count,

drivers/gpu/drm/gma500/cdv_intel_dp.c

999

struct cdv_intel_dp *intel_dp;

drivers/gpu/drm/i915/display/g4x_dp.c

101

intel_dp_set_link_params(intel_dp,

drivers/gpu/drm/i915/display/g4x_dp.c

1034

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

1035

u8 train_set = intel_dp->train_set[0];

drivers/gpu/drm/i915/display/g4x_dp.c

1043

intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);

drivers/gpu/drm/i915/display/g4x_dp.c

1044

intel_dp->DP |= signal_levels;

drivers/gpu/drm/i915/display/g4x_dp.c

1046

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

1047

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

1082

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

1083

u8 train_set = intel_dp->train_set[0];

drivers/gpu/drm/i915/display/g4x_dp.c

1091

intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;

drivers/gpu/drm/i915/display/g4x_dp.c

1092

intel_dp->DP |= signal_levels;

drivers/gpu/drm/i915/display/g4x_dp.c

1094

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

1095

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

1134

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

1135

u8 train_set = intel_dp->train_set[0];

drivers/gpu/drm/i915/display/g4x_dp.c

1143

intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;

drivers/gpu/drm/i915/display/g4x_dp.c

1144

intel_dp->DP |= signal_levels;

drivers/gpu/drm/i915/display/g4x_dp.c

1146

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

1147

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

1166

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

1169

if (intel_dp_test_phy(intel_dp))

drivers/gpu/drm/i915/display/g4x_dp.c

1174

intel_dp_check_link_state(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

124

intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;

drivers/gpu/drm/i915/display/g4x_dp.c

1264

struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));

drivers/gpu/drm/i915/display/g4x_dp.c

1266

intel_dp->DP = intel_de_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

1268

intel_dp->reset_link_params = true;

drivers/gpu/drm/i915/display/g4x_dp.c

1269

intel_dp_invalidate_source_oui(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

127

intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;

drivers/gpu/drm/i915/display/g4x_dp.c

1272

vlv_pps_pipe_reset(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

1274

intel_pps_encoder_reset(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

128

intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);

drivers/gpu/drm/i915/display/g4x_dp.c

134

intel_dp->DP |= DP_SYNC_HS_HIGH;

drivers/gpu/drm/i915/display/g4x_dp.c

136

intel_dp->DP |= DP_SYNC_VS_HIGH;

drivers/gpu/drm/i915/display/g4x_dp.c

137

intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

drivers/gpu/drm/i915/display/g4x_dp.c

140

intel_dp->DP |= DP_ENHANCED_FRAMING;

drivers/gpu/drm/i915/display/g4x_dp.c

142

intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);

drivers/gpu/drm/i915/display/g4x_dp.c

144

intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

drivers/gpu/drm/i915/display/g4x_dp.c

152

intel_dp->DP |= DP_COLOR_RANGE_16_235;

drivers/gpu/drm/i915/display/g4x_dp.c

155

intel_dp->DP |= DP_SYNC_HS_HIGH;

drivers/gpu/drm/i915/display/g4x_dp.c

157

intel_dp->DP |= DP_SYNC_VS_HIGH;

drivers/gpu/drm/i915/display/g4x_dp.c

158

intel_dp->DP |= DP_LINK_TRAIN_OFF;

drivers/gpu/drm/i915/display/g4x_dp.c

161

intel_dp->DP |= DP_ENHANCED_FRAMING;

drivers/gpu/drm/i915/display/g4x_dp.c

164

intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);

drivers/gpu/drm/i915/display/g4x_dp.c

166

intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);

drivers/gpu/drm/i915/display/g4x_dp.c

170

static void assert_dp_port(struct intel_dp *intel_dp, bool state)

drivers/gpu/drm/i915/display/g4x_dp.c

172

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

173

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

174

bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN;

drivers/gpu/drm/i915/display/g4x_dp.c

194

static void ilk_edp_pll_on(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/g4x_dp.c

197

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

201

assert_dp_port_disabled(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

207

intel_dp->DP &= ~EDP_PLL_FREQ_MASK;

drivers/gpu/drm/i915/display/g4x_dp.c

210

intel_dp->DP |= EDP_PLL_FREQ_162MHZ;

drivers/gpu/drm/i915/display/g4x_dp.c

212

intel_dp->DP |= EDP_PLL_FREQ_270MHZ;

drivers/gpu/drm/i915/display/g4x_dp.c

214

intel_de_write(display, DP_A, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

227

intel_dp->DP |= EDP_PLL_ENABLE;

drivers/gpu/drm/i915/display/g4x_dp.c

229

intel_de_write(display, DP_A, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

234

static void ilk_edp_pll_off(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/g4x_dp.c

237

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

240

assert_dp_port_disabled(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

245

intel_dp->DP &= ~EDP_PLL_ENABLE;

drivers/gpu/drm/i915/display/g4x_dp.c

247

intel_de_write(display, DP_A, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

303

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

312

ret = g4x_dp_port_enabled(display, intel_dp->output_reg,

drivers/gpu/drm/i915/display/g4x_dp.c

339

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

349

tmp = intel_de_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

404

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/g4x_dp.c

415

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

420

(intel_de_read(display, intel_dp->output_reg) &

drivers/gpu/drm/i915/display/g4x_dp.c

426

intel_dp->DP &= ~DP_PORT_EN;

drivers/gpu/drm/i915/display/g4x_dp.c

427

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

428

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

444

intel_dp->DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);

drivers/gpu/drm/i915/display/g4x_dp.c

445

intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |

drivers/gpu/drm/i915/display/g4x_dp.c

447

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

448

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

450

intel_dp->DP &= ~DP_PORT_EN;

drivers/gpu/drm/i915/display/g4x_dp.c

451

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

452

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

459

msleep(intel_dp->pps.panel_power_down_delay);

drivers/gpu/drm/i915/display/g4x_dp.c

470

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

476

intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;

drivers/gpu/drm/i915/display/g4x_dp.c

477

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

487

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

495

intel_dp->DP &= ~DP_AUDIO_OUTPUT_ENABLE;

drivers/gpu/drm/i915/display/g4x_dp.c

496

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

504

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

506

intel_dp->link.active = false;

drivers/gpu/drm/i915/display/g4x_dp.c

512

intel_pps_vdd_on(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

514

intel_dp_set_power(intel_dp, DP_SET_POWER_D3);

drivers/gpu/drm/i915/display/g4x_dp.c

515

intel_pps_off(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

539

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

552

ilk_edp_pll_off(intel_dp, old_crtc_state);

drivers/gpu/drm/i915/display/g4x_dp.c

575

cpt_set_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/g4x_dp.c

579

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

581

intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;

drivers/gpu/drm/i915/display/g4x_dp.c

585

intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

drivers/gpu/drm/i915/display/g4x_dp.c

588

intel_dp->DP |= DP_LINK_TRAIN_PAT_1_CPT;

drivers/gpu/drm/i915/display/g4x_dp.c

591

intel_dp->DP |= DP_LINK_TRAIN_PAT_2_CPT;

drivers/gpu/drm/i915/display/g4x_dp.c

598

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

599

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

603

cpt_set_idle_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/g4x_dp.c

606

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

608

intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;

drivers/gpu/drm/i915/display/g4x_dp.c

609

intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;

drivers/gpu/drm/i915/display/g4x_dp.c

611

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

612

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

616

g4x_set_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/g4x_dp.c

620

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

622

intel_dp->DP &= ~DP_LINK_TRAIN_MASK;

drivers/gpu/drm/i915/display/g4x_dp.c

626

intel_dp->DP |= DP_LINK_TRAIN_OFF;

drivers/gpu/drm/i915/display/g4x_dp.c

629

intel_dp->DP |= DP_LINK_TRAIN_PAT_1;

drivers/gpu/drm/i915/display/g4x_dp.c

632

intel_dp->DP |= DP_LINK_TRAIN_PAT_2;

drivers/gpu/drm/i915/display/g4x_dp.c

639

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

640

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

644

g4x_set_idle_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/g4x_dp.c

647

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

649

intel_dp->DP &= ~DP_LINK_TRAIN_MASK;

drivers/gpu/drm/i915/display/g4x_dp.c

650

intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;

drivers/gpu/drm/i915/display/g4x_dp.c

652

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

653

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

656

static void intel_dp_enable_port(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/g4x_dp.c

659

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

663

intel_dp_program_link_training_pattern(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/g4x_dp.c

672

intel_dp->DP |= DP_PORT_EN;

drivers/gpu/drm/i915/display/g4x_dp.c

674

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

675

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

684

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

685

u32 dp_reg = intel_de_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

690

with_intel_pps_lock(intel_dp) {

drivers/gpu/drm/i915/display/g4x_dp.c

694

intel_dp_enable_port(intel_dp, pipe_config);

drivers/gpu/drm/i915/display/g4x_dp.c

696

intel_pps_vdd_on_unlocked(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

697

intel_pps_on_unlocked(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

698

intel_pps_vdd_off_unlocked(intel_dp, true);

drivers/gpu/drm/i915/display/g4x_dp.c

710

intel_dp_set_power(intel_dp, DP_SET_POWER_D0);

drivers/gpu/drm/i915/display/g4x_dp.c

711

intel_dp_configure_protocol_converter(intel_dp, pipe_config);

drivers/gpu/drm/i915/display/g4x_dp.c

712

intel_dp_check_frl_training(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

713

intel_dp_pcon_dsc_configure(intel_dp, pipe_config);

drivers/gpu/drm/i915/display/g4x_dp.c

714

intel_dp_start_link_train(state, intel_dp, pipe_config);

drivers/gpu/drm/i915/display/g4x_dp.c

715

intel_dp_stop_link_train(intel_dp, pipe_config);

drivers/gpu/drm/i915/display/g4x_dp.c

740

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

747

ilk_edp_pll_on(intel_dp, pipe_config);

drivers/gpu/drm/i915/display/g4x_dp.c

801

static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/g4x_dp.c

807

static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/g4x_dp.c

813

static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/g4x_dp.c

818

static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/g4x_dp.c

826

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

829

u8 train_set = intel_dp->train_set[0];

drivers/gpu/drm/i915/display/g4x_dp.c

912

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

915

u8 train_set = intel_dp->train_set[0];

drivers/gpu/drm/i915/display/g4x_dp.c

96

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.h

17

struct intel_dp;

drivers/gpu/drm/i915/display/intel_alpm.c

120

_lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.c

123

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

150

static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.c

153

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

166

if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_alpm.c

202

bool intel_alpm_compute_params(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.c

205

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

210

int precharge = intel_dp_aux_fw_sync_len(intel_dp) - preamble;

drivers/gpu/drm/i915/display/intel_alpm.c

234

if (!_lnl_compute_alpm_params(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_alpm.c

285

void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.c

29

bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_alpm.c

31

return intel_dp->alpm_dpcd & DP_ALPM_CAP;

drivers/gpu/drm/i915/display/intel_alpm.c

314

if (intel_alpm_aux_less_wake_supported(intel_dp))

drivers/gpu/drm/i915/display/intel_alpm.c

323

void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.c

327

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

329

if (intel_dp->alpm.lobf_disable_debug) {

drivers/gpu/drm/i915/display/intel_alpm.c

334

if (intel_dp->alpm.sink_alpm_error)

drivers/gpu/drm/i915/display/intel_alpm.c

337

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_alpm.c

34

bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_alpm.c

343

if (!intel_dp->as_sdp_supported)

drivers/gpu/drm/i915/display/intel_alpm.c

353

if (!(intel_alpm_aux_wake_supported(intel_dp) ||

drivers/gpu/drm/i915/display/intel_alpm.c

354

intel_alpm_aux_less_wake_supported(intel_dp)))

drivers/gpu/drm/i915/display/intel_alpm.c

357

if (!intel_alpm_compute_params(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_alpm.c

36

return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP;

drivers/gpu/drm/i915/display/intel_alpm.c

380

static void lnl_alpm_configure(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.c

383

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

387

if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&

drivers/gpu/drm/i915/display/intel_alpm.c

39

bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.c

391

mutex_lock(&intel_dp->alpm.lock);

drivers/gpu/drm/i915/display/intel_alpm.c

396

if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {

drivers/gpu/drm/i915/display/intel_alpm.c

402

if (intel_dp->as_sdp_supported) {

drivers/gpu/drm/i915/display/intel_alpm.c

42

return intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) ||

drivers/gpu/drm/i915/display/intel_alpm.c

427

mutex_unlock(&intel_dp->alpm.lock);

drivers/gpu/drm/i915/display/intel_alpm.c

43

(crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));

drivers/gpu/drm/i915/display/intel_alpm.c

430

void intel_alpm_configure(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.c

433

lnl_alpm_configure(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_alpm.c

434

intel_dp->alpm.transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_alpm.c

437

void intel_alpm_port_configure(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.c

440

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

441

enum port port = dp_to_dig_port(intel_dp)->base.port;

drivers/gpu/drm/i915/display/intel_alpm.c

447

if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {

drivers/gpu/drm/i915/display/intel_alpm.c

46

void intel_alpm_init(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_alpm.c

475

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_alpm.c

48

mutex_init(&intel_dp->alpm.lock);

drivers/gpu/drm/i915/display/intel_alpm.c

480

intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_alpm.c

482

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_alpm.c

485

mutex_lock(&intel_dp->alpm.lock);

drivers/gpu/drm/i915/display/intel_alpm.c

488

mutex_unlock(&intel_dp->alpm.lock);

drivers/gpu/drm/i915/display/intel_alpm.c

492

void intel_alpm_enable_sink(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.c

497

if (!intel_psr_needs_alpm(intel_dp, crtc_state) && !crtc_state->has_lobf)

drivers/gpu/drm/i915/display/intel_alpm.c

503

intel_alpm_aux_less_wake_supported(intel_dp)))

drivers/gpu/drm/i915/display/intel_alpm.c

506

drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val);

drivers/gpu/drm/i915/display/intel_alpm.c

516

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_alpm.c

521

intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_alpm.c

523

if (intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_alpm.c

524

intel_alpm_enable_sink(intel_dp, new_crtc_state);

drivers/gpu/drm/i915/display/intel_alpm.c

525

intel_alpm_configure(intel_dp, new_crtc_state);

drivers/gpu/drm/i915/display/intel_alpm.c

570

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_alpm.c

572

*val = intel_dp->alpm.lobf_disable_debug;

drivers/gpu/drm/i915/display/intel_alpm.c

581

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_alpm.c

583

intel_dp->alpm.lobf_disable_debug = val;

drivers/gpu/drm/i915/display/intel_alpm.c

608

void intel_alpm_disable(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_alpm.c

610

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

611

enum transcoder cpu_transcoder = intel_dp->alpm.transcoder;

drivers/gpu/drm/i915/display/intel_alpm.c

613

if (DISPLAY_VER(display) < 20 || !intel_dp->alpm_dpcd)

drivers/gpu/drm/i915/display/intel_alpm.c

616

mutex_lock(&intel_dp->alpm.lock);

drivers/gpu/drm/i915/display/intel_alpm.c

622

mutex_unlock(&intel_dp->alpm.lock);

drivers/gpu/drm/i915/display/intel_alpm.c

625

bool intel_alpm_get_error(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_alpm.c

627

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

628

struct drm_dp_aux *aux = &intel_dp->aux;

drivers/gpu/drm/i915/display/intel_alpm.h

11

struct intel_dp;

drivers/gpu/drm/i915/display/intel_alpm.h

18

void intel_alpm_init(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.h

19

bool intel_alpm_compute_params(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.h

21

void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.h

24

void intel_alpm_configure(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.h

26

void intel_alpm_enable_sink(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.h

29

void intel_alpm_port_configure(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.h

33

bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.h

34

bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.h

35

bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.h

37

void intel_alpm_disable(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.h

38

bool intel_alpm_get_error(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.h

39

void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_cdclk.c

2655

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_cdclk.c

2657

intel_psr_pause(intel_dp);

drivers/gpu/drm/i915/display/intel_cdclk.c

2669

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_cdclk.c

2671

mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,

drivers/gpu/drm/i915/display/intel_cdclk.c

2678

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_cdclk.c

2680

mutex_unlock(&intel_dp->aux.hw_mutex);

drivers/gpu/drm/i915/display/intel_cdclk.c

2685

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_cdclk.c

2687

intel_psr_resume(intel_dp);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

112

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

115

intel_psr_pause(intel_dp);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

125

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

127

intel_psr_resume(intel_dp);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

1991

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

1993

(intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);

drivers/gpu/drm/i915/display/intel_ddi.c

1128

static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

1131

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

1132

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_ddi.c

1152

static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_ddi.c

1183

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1186

intel_dp->hobl_active = is_hobl_buf_trans(trans);

drivers/gpu/drm/i915/display/intel_ddi.c

1188

intel_dp->hobl_active ? val : 0);

drivers/gpu/drm/i915/display/intel_ddi.c

1467

static int translate_signal_level(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

1470

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

1490

static int intel_ddi_dp_level(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

1494

u8 train_set = intel_dp->train_set[lane];

drivers/gpu/drm/i915/display/intel_ddi.c

1502

return translate_signal_level(intel_dp, signal_levels);

drivers/gpu/drm/i915/display/intel_ddi.c

1535

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1552

intel_dp->DP &= ~DDI_BUF_EMP_MASK;

drivers/gpu/drm/i915/display/intel_ddi.c

1553

intel_dp->DP |= signal_levels;

drivers/gpu/drm/i915/display/intel_ddi.c

1555

intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP);

drivers/gpu/drm/i915/display/intel_ddi.c

2316

static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

2320

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

2325

if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,

drivers/gpu/drm/i915/display/intel_ddi.c

2332

static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

2336

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

2341

if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION,

drivers/gpu/drm/i915/display/intel_ddi.c

2347

drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS,

drivers/gpu/drm/i915/display/intel_ddi.c

2380

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2404

ret = wait_for_fec_detected(&intel_dp->aux, enabled);

drivers/gpu/drm/i915/display/intel_ddi.c

2628

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2633

intel_dp_set_link_params(intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

2677

intel_dp_set_power(intel_dp, DP_SET_POWER_D0);

drivers/gpu/drm/i915/display/intel_ddi.c

2679

transparent_mode = intel_dp_lttpr_transparent_mode_enabled(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

2680

drm_dp_lttpr_wake_timeout_setup(&intel_dp->aux, transparent_mode);

drivers/gpu/drm/i915/display/intel_ddi.c

2682

intel_dp_configure_protocol_converter(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2693

intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);

drivers/gpu/drm/i915/display/intel_ddi.c

2695

intel_dp_check_frl_training(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

2696

intel_dp_pcon_dsc_configure(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2717

intel_dp_start_link_train(state, intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2721

intel_dp_stop_link_train(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2729

ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);

drivers/gpu/drm/i915/display/intel_ddi.c

2744

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2749

intel_dp_set_link_params(intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

2767

intel_pps_on(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

2841

intel_dp_set_power(intel_dp, DP_SET_POWER_D0);

drivers/gpu/drm/i915/display/intel_ddi.c

2843

intel_dp_configure_protocol_converter(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2853

intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);

drivers/gpu/drm/i915/display/intel_ddi.c

2855

intel_dp_check_frl_training(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

2856

intel_dp_pcon_dsc_configure(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2865

intel_dp_start_link_train(state, intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2869

intel_dp_stop_link_train(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2876

ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);

drivers/gpu/drm/i915/display/intel_ddi.c

2891

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2902

intel_dp_set_link_params(intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

2912

intel_pps_on(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

2932

intel_dp_set_power(intel_dp, DP_SET_POWER_D0);

drivers/gpu/drm/i915/display/intel_ddi.c

2933

intel_dp_configure_protocol_converter(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2938

intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);

drivers/gpu/drm/i915/display/intel_ddi.c

2939

intel_dp_start_link_train(state, intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2942

intel_dp_stop_link_train(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3128

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_ddi.c

3141

intel_dp_set_power(intel_dp, DP_SET_POWER_D3);

drivers/gpu/drm/i915/display/intel_ddi.c

3159

intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false);

drivers/gpu/drm/i915/display/intel_ddi.c

3171

intel_pps_vdd_on(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

3172

intel_pps_off(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

3227

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3243

drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0);

drivers/gpu/drm/i915/display/intel_ddi.c

3251

drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0);

drivers/gpu/drm/i915/display/intel_ddi.c

3367

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3372

intel_dp_stop_link_train(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3535

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3543

drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0);

drivers/gpu/drm/i915/display/intel_ddi.c

357

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3571

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3575

intel_dp->link.active = false;

drivers/gpu/drm/i915/display/intel_ddi.c

3578

intel_psr_disable(intel_dp, old_crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3579

intel_alpm_disable(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

3585

intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

361

intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) |

drivers/gpu/drm/i915/display/intel_ddi.c

365

intel_dp->DP |= DDI_BUF_PORT_REVERSAL;

drivers/gpu/drm/i915/display/intel_ddi.c

367

intel_dp->DP |= DDI_A_4_LANES;

drivers/gpu/drm/i915/display/intel_ddi.c

371

intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;

drivers/gpu/drm/i915/display/intel_ddi.c

373

intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;

drivers/gpu/drm/i915/display/intel_ddi.c

3731

static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

3735

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

377

intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);

drivers/gpu/drm/i915/display/intel_ddi.c

3771

intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;

drivers/gpu/drm/i915/display/intel_ddi.c

3773

intel_ddi_buf_enable(encoder, intel_dp->DP);

drivers/gpu/drm/i915/display/intel_ddi.c

3774

intel_dp->DP |= DDI_BUF_CTL_ENABLE;

drivers/gpu/drm/i915/display/intel_ddi.c

3780

intel_alpm_port_configure(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3789

static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

379

intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;

drivers/gpu/drm/i915/display/intel_ddi.c

3792

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

3793

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

3817

intel_ddi_buf_enable(encoder, intel_dp->DP);

drivers/gpu/drm/i915/display/intel_ddi.c

3818

intel_dp->DP |= DDI_BUF_CTL_ENABLE;

drivers/gpu/drm/i915/display/intel_ddi.c

3821

static void intel_ddi_set_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

3825

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

3826

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_ddi.c

385

intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay);

drivers/gpu/drm/i915/display/intel_ddi.c

3853

static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

3856

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

3857

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_ddi.c

4156

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4162

if (intel_dp_mst_active_streams(intel_dp))

drivers/gpu/drm/i915/display/intel_ddi.c

4669

struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));

drivers/gpu/drm/i915/display/intel_ddi.c

4672

intel_dp->reset_link_params = true;

drivers/gpu/drm/i915/display/intel_ddi.c

4673

intel_dp_invalidate_source_oui(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

4675

intel_pps_encoder_reset(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

4739

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_ddi.c

4740

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_ddi.c

4834

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_ddi.c

4840

if (intel_dp_test_phy(intel_dp))

drivers/gpu/drm/i915/display/intel_ddi.c

4851

intel_dp_check_link_state(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

5066

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

5067

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

5087

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

5088

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

890

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

903

intel_dp_mst_active_streams(intel_dp))

drivers/gpu/drm/i915/display/intel_ddi.h

18

struct intel_dp;

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1189

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1190

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1192

return connector->panel.vbt.edp.hobl && !intel_dp->hobl_failed;

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1197

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1198

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1052

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1060

intel_dp->force_dsc_bpc = dsc_bpc;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1119

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1127

intel_dp->force_dsc_output_format = dsc_output_format;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1154

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1170

intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1172

str_yes_no(intel_dp->force_dsc_fractional_bpp_en));

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1188

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1204

intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

218

struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

220

seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

224

drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,

drivers/gpu/drm/i915/display/intel_display_debugfs.c

225

connector->detect_edid, &intel_dp->aux);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

904

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

939

intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

955

drm_dp_dsc_sink_max_slice_count((connector->dp.dsc_dpcd), intel_dp_is_edp(intel_dp)));

drivers/gpu/drm/i915/display/intel_display_debugfs.c

957

str_yes_no(intel_dp->force_dsc_en));

drivers/gpu/drm/i915/display/intel_display_debugfs.c

958

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_display_debugfs.c

977

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

993

intel_dp->force_dsc_en = dsc_enable;

drivers/gpu/drm/i915/display/intel_display_irq.c

1292

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_display_irq.c

1296

intel_dp->psr.transcoder);

drivers/gpu/drm/i915/display/intel_display_irq.c

1305

intel_psr_irq_handler(intel_dp, psr_iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

961

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_display_irq.c

965

intel_psr_irq_handler(intel_dp, psr_iir);

drivers/gpu/drm/i915/display/intel_display_types.h

1890

u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);

drivers/gpu/drm/i915/display/intel_display_types.h

1895

u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,

drivers/gpu/drm/i915/display/intel_display_types.h

1898

intel_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);

drivers/gpu/drm/i915/display/intel_display_types.h

1899

intel_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);

drivers/gpu/drm/i915/display/intel_display_types.h

1902

void (*prepare_link_retrain)(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_display_types.h

1904

void (*set_link_train)(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_display_types.h

1907

void (*set_idle_link_train)(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_display_types.h

1910

u8 (*preemph_max)(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_display_types.h

1911

u8 (*voltage_max)(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_display_types.h

1979

struct intel_dp dp;

drivers/gpu/drm/i915/display/intel_display_types.h

2105

static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)

drivers/gpu/drm/i915/display/intel_display_types.h

2110

static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector)

drivers/gpu/drm/i915/display/intel_display_types.h

2146

dp_to_dig_port(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_display_types.h

2148

return container_of(intel_dp, struct intel_digital_port, dp);

drivers/gpu/drm/i915/display/intel_display_types.h

2309

__assoc(intel_dp, p), \

drivers/gpu/drm/i915/display/intel_display_types.h

601

struct intel_dp *dp;

drivers/gpu/drm/i915/display/intel_dp.c

1144

static bool source_can_output(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

1147

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1172

dfp_can_convert_from_rgb(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

1175

if (!drm_dp_is_branch(intel_dp->dpcd))

drivers/gpu/drm/i915/display/intel_dp.c

1179

return intel_dp->dfp.rgb_to_ycbcr;

drivers/gpu/drm/i915/display/intel_dp.c

1182

return intel_dp->dfp.rgb_to_ycbcr &&

drivers/gpu/drm/i915/display/intel_dp.c

1183

intel_dp->dfp.ycbcr_444_to_420;

drivers/gpu/drm/i915/display/intel_dp.c

1189

dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

119

bool intel_dp_is_edp(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

1192

if (!drm_dp_is_branch(intel_dp->dpcd))

drivers/gpu/drm/i915/display/intel_dp.c

1196

return intel_dp->dfp.ycbcr_444_to_420;

drivers/gpu/drm/i915/display/intel_dp.c

1202

dfp_can_convert(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

1208

return dfp_can_convert_from_rgb(intel_dp, sink_format);

drivers/gpu/drm/i915/display/intel_dp.c

121

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1210

return dfp_can_convert_from_ycbcr444(intel_dp, sink_format);

drivers/gpu/drm/i915/display/intel_dp.c

1224

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

1226

intel_dp->force_dsc_output_format;

drivers/gpu/drm/i915/display/intel_dp.c

1229

if (source_can_output(intel_dp, force_dsc_output_format) &&

drivers/gpu/drm/i915/display/intel_dp.c

1230

(!drm_dp_is_branch(intel_dp->dpcd) ||

drivers/gpu/drm/i915/display/intel_dp.c

1232

dfp_can_convert(intel_dp, force_dsc_output_format, sink_format)))

drivers/gpu/drm/i915/display/intel_dp.c

1239

dfp_can_convert_from_rgb(intel_dp, sink_format))

drivers/gpu/drm/i915/display/intel_dp.c

1243

dfp_can_convert_from_ycbcr444(intel_dp, sink_format))

drivers/gpu/drm/i915/display/intel_dp.c

1249

drm_WARN_ON(display->drm, !source_can_output(intel_dp, output_format));

drivers/gpu/drm/i915/display/intel_dp.c

126

static void intel_dp_unset_edid(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1303

static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

1305

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

1307

int max_tmds_clock = intel_dp->dfp.max_tmds_clock;

drivers/gpu/drm/i915/display/intel_dp.c

1317

intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

1329

min_tmds_clock = intel_dp->dfp.min_tmds_clock;

drivers/gpu/drm/i915/display/intel_dp.c

1330

max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1356

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

1359

if (intel_dp->dfp.pcon_max_frl_bw) {

drivers/gpu/drm/i915/display/intel_dp.c

1365

max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;

drivers/gpu/drm/i915/display/intel_dp.c

1376

if (intel_dp->dfp.max_dotclock &&

drivers/gpu/drm/i915/display/intel_dp.c

1377

target_clock > intel_dp->dfp.max_dotclock)

drivers/gpu/drm/i915/display/intel_dp.c

1381

return intel_dp_tmds_clock_valid(intel_dp, target_clock,

drivers/gpu/drm/i915/display/intel_dp.c

1390

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

1395

if (intel_dp->dfp.min_tmds_clock &&

drivers/gpu/drm/i915/display/intel_dp.c

1396

!intel_dp_has_hdmi_sink(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

1438

bool intel_dp_can_join(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

1441

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1443

if (num_joined_pipes > 1 && !intel_dp_has_joiner(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

1489

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

1504

max_link_clock = intel_dp_max_link_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1505

max_lanes = intel_dp_max_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1507

max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes);

drivers/gpu/drm/i915/display/intel_dp.c

1548

if (intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

158

static int max_dprx_rate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

160

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1611

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

1628

if (intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

163

if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

164

max_rate = drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp.c

166

max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);

drivers/gpu/drm/i915/display/intel_dp.c

1681

static void intel_dp_print_rates(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

1683

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1689

seq_buf_print_array(&s, intel_dp->source_rates, intel_dp->num_source_rates);

drivers/gpu/drm/i915/display/intel_dp.c

1693

seq_buf_print_array(&s, intel_dp->sink_rates, intel_dp->num_sink_rates);

drivers/gpu/drm/i915/display/intel_dp.c

1697

seq_buf_print_array(&s, intel_dp->common_rates, intel_dp->num_common_rates);

drivers/gpu/drm/i915/display/intel_dp.c

1701

static int forced_link_rate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

1703

int len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.force_rate);

drivers/gpu/drm/i915/display/intel_dp.c

1706

return intel_dp_common_rate(intel_dp, 0);

drivers/gpu/drm/i915/display/intel_dp.c

1708

return intel_dp_common_rate(intel_dp, len - 1);

drivers/gpu/drm/i915/display/intel_dp.c

1712

intel_dp_max_link_rate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

1716

if (intel_dp->link.force_rate)

drivers/gpu/drm/i915/display/intel_dp.c

1717

return forced_link_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1719

len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate);

drivers/gpu/drm/i915/display/intel_dp.c

1721

return intel_dp_common_rate(intel_dp, len - 1);

drivers/gpu/drm/i915/display/intel_dp.c

1725

intel_dp_min_link_rate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

1727

if (intel_dp->link.force_rate)

drivers/gpu/drm/i915/display/intel_dp.c

1728

return forced_link_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1730

return intel_dp_common_rate(intel_dp, 0);

drivers/gpu/drm/i915/display/intel_dp.c

1733

int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)

drivers/gpu/drm/i915/display/intel_dp.c

1735

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1736

int i = intel_dp_rate_index(intel_dp->sink_rates,

drivers/gpu/drm/i915/display/intel_dp.c

1737

intel_dp->num_sink_rates, rate);

drivers/gpu/drm/i915/display/intel_dp.c

174

if (intel_dp_is_edp(intel_dp) && intel_has_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2))

drivers/gpu/drm/i915/display/intel_dp.c

1745

void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,

drivers/gpu/drm/i915/display/intel_dp.c

1748

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1755

if (intel_dp->use_rate_select) {

drivers/gpu/drm/i915/display/intel_dp.c

1758

intel_dp_rate_select(intel_dp, port_clock);

drivers/gpu/drm/i915/display/intel_dp.c

1765

bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

1767

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

1772

static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

1775

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1776

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

1788

bool intel_dp_supports_fec(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

1792

return intel_dp_source_supports_fec(intel_dp, pipe_config) &&

drivers/gpu/drm/i915/display/intel_dp.c

1796

bool intel_dp_supports_dsc(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

180

static int max_dprx_lane_count(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

1804

!intel_dp_supports_fec(intel_dp, connector, crtc_state))

drivers/gpu/drm/i915/display/intel_dp.c

1810

static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

182

if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

183

return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp.c

1833

intel_dp_has_hdmi_sink(intel_dp)) &&

drivers/gpu/drm/i915/display/intel_dp.c

1834

intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,

drivers/gpu/drm/i915/display/intel_dp.c

1842

static int intel_dp_max_bpp(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

1846

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1847

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

185

return drm_dp_max_lane_count(intel_dp->dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

1852

if (intel_dp->dfp.max_bpc)

drivers/gpu/drm/i915/display/intel_dp.c

1853

bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);

drivers/gpu/drm/i915/display/intel_dp.c

1855

if (intel_dp->dfp.min_tmds_clock) {

drivers/gpu/drm/i915/display/intel_dp.c

1858

max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,

drivers/gpu/drm/i915/display/intel_dp.c

1867

if (intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

188

static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

190

intel_dp->sink_rates[0] = 162000;

drivers/gpu/drm/i915/display/intel_dp.c

1909

intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

191

intel_dp->num_sink_rates = 1;

drivers/gpu/drm/i915/display/intel_dp.c

1923

for (i = 0; i < intel_dp->num_common_rates; i++) {

drivers/gpu/drm/i915/display/intel_dp.c

1924

link_rate = intel_dp_common_rate(intel_dp, i);

drivers/gpu/drm/i915/display/intel_dp.c

1939

link_avail = intel_dp_max_link_data_rate(intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

195

static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

203

if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {

drivers/gpu/drm/i915/display/intel_dp.c

207

memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));

drivers/gpu/drm/i915/display/intel_dp.c

208

intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);

drivers/gpu/drm/i915/display/intel_dp.c

2125

static bool is_bw_sufficient_for_dsc_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

2134

available_bw = intel_dp_max_link_data_rate(intel_dp, link_clock, lane_count);

drivers/gpu/drm/i915/display/intel_dp.c

2142

static int dsc_compute_link_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

2152

for (i = 0; i < intel_dp->num_common_rates; i++) {

drivers/gpu/drm/i915/display/intel_dp.c

2153

link_rate = intel_dp_common_rate(intel_dp, i);

drivers/gpu/drm/i915/display/intel_dp.c

216

max_rate = max_dprx_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

217

max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);

drivers/gpu/drm/i915/display/intel_dp.c

2175

ret = intel_dp_mtp_tu_compute_config(intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

2189

if (!is_bw_sufficient_for_dsc_config(intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

224

intel_dp->sink_rates[i] = dp_rates[i];

drivers/gpu/drm/i915/display/intel_dp.c

2264

static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

2266

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2274

if (intel_dp->force_dsc_en)

drivers/gpu/drm/i915/display/intel_dp.c

231

if (drm_dp_128b132b_supported(intel_dp->dpcd)) {

drivers/gpu/drm/i915/display/intel_dp.c

2310

bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16)

drivers/gpu/drm/i915/display/intel_dp.c

2312

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2315

if (intel_dp->force_dsc_fractional_bpp_en && !fxp_q4_to_frac(bpp_x16))

drivers/gpu/drm/i915/display/intel_dp.c

234

BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);

drivers/gpu/drm/i915/display/intel_dp.c

236

drm_dp_dpcd_readb(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp.c

2365

static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

2371

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2383

if (intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

239

if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {

drivers/gpu/drm/i915/display/intel_dp.c

2393

if (!intel_dp_dsc_valid_compressed_bpp(intel_dp, bpp_x16))

drivers/gpu/drm/i915/display/intel_dp.c

2396

ret = dsc_compute_link_config(intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

2403

if (intel_dp->force_dsc_fractional_bpp_en &&

drivers/gpu/drm/i915/display/intel_dp.c

241

if (intel_dp->lttpr_common_caps[0] >= 0x20 &&

drivers/gpu/drm/i915/display/intel_dp.c

242

intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -

drivers/gpu/drm/i915/display/intel_dp.c

2430

int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

2433

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2436

if (!intel_dp->force_dsc_bpc)

drivers/gpu/drm/i915/display/intel_dp.c

2439

forced_bpp = intel_dp->force_dsc_bpc * 3;

drivers/gpu/drm/i915/display/intel_dp.c

2443

intel_dp->force_dsc_bpc);

drivers/gpu/drm/i915/display/intel_dp.c

2449

intel_dp->force_dsc_bpc);

drivers/gpu/drm/i915/display/intel_dp.c

2454

static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

246

uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -

drivers/gpu/drm/i915/display/intel_dp.c

2462

forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);

drivers/gpu/drm/i915/display/intel_dp.c

2468

ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state,

drivers/gpu/drm/i915/display/intel_dp.c

2511

int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

2517

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2540

ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,

drivers/gpu/drm/i915/display/intel_dp.c

255

intel_dp->sink_rates[i++] = 1000000;

drivers/gpu/drm/i915/display/intel_dp.c

257

intel_dp->sink_rates[i++] = 1350000;

drivers/gpu/drm/i915/display/intel_dp.c

259

intel_dp->sink_rates[i++] = 2000000;

drivers/gpu/drm/i915/display/intel_dp.c

262

intel_dp->num_sink_rates = i;

drivers/gpu/drm/i915/display/intel_dp.c

2630

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

2635

dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

265

static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

267

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2672

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

268

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

269

struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2691

return is_bw_sufficient_for_dsc_config(intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

2709

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

2713

const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

272

intel_dp_set_dpcd_sink_rates(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

274

if (intel_dp->num_sink_rates)

drivers/gpu/drm/i915/display/intel_dp.c

2793

intel_dp_compute_config_limits(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

2800

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2805

limits->min_rate = intel_dp_min_link_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2806

limits->max_rate = intel_dp_max_link_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2810

limits->min_lane_count = intel_dp_min_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2811

limits->max_lane_count = intel_dp_max_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

282

intel_dp_set_default_sink_rates(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2825

limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

2830

if (intel_dp_supports_dsc(intel_dp, connector, crtc_state) &&

drivers/gpu/drm/i915/display/intel_dp.c

2838

str_yes_no(intel_dp_supports_dsc(intel_dp, connector,

drivers/gpu/drm/i915/display/intel_dp.c

285

static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

287

intel_dp->max_sink_lane_count = 1;

drivers/gpu/drm/i915/display/intel_dp.c

2875

if (is_mst || intel_dp->use_max_params) {

drivers/gpu/drm/i915/display/intel_dp.c

2891

intel_dp_test_compute_config(intel_dp, crtc_state, limits);

drivers/gpu/drm/i915/display/intel_dp.c

290

static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

292

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

293

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

2937

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

294

struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2946

dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||

drivers/gpu/drm/i915/display/intel_dp.c

2947

!intel_dp_compute_config_limits(intel_dp, conn_state, pipe_config,

drivers/gpu/drm/i915/display/intel_dp.c

2957

ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,

drivers/gpu/drm/i915/display/intel_dp.c

2960

ret = intel_dp_mtp_tu_compute_config(intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

297

intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2976

if (dsc_needed && !intel_dp_supports_dsc(intel_dp, connector, pipe_config)) {

drivers/gpu/drm/i915/display/intel_dp.c

2987

str_yes_no(intel_dp->force_dsc_en));

drivers/gpu/drm/i915/display/intel_dp.c

2989

if (!intel_dp_compute_config_limits(intel_dp, conn_state, pipe_config,

drivers/gpu/drm/i915/display/intel_dp.c

299

switch (intel_dp->max_sink_lane_count) {

drivers/gpu/drm/i915/display/intel_dp.c

2995

ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,

drivers/gpu/drm/i915/display/intel_dp.c

3017

intel_dp_max_link_data_rate(intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

3035

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

3040

!intel_dp_supports_fec(intel_dp, connector, crtc_state))

drivers/gpu/drm/i915/display/intel_dp.c

310

intel_dp->max_sink_lane_count);

drivers/gpu/drm/i915/display/intel_dp.c

312

intel_dp_set_default_max_sink_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3210

static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

3213

if (!intel_dp->as_sdp_v2_supported)

drivers/gpu/drm/i915/display/intel_dp.c

3219

if (drm_dp_is_branch(intel_dp->dpcd))

drivers/gpu/drm/i915/display/intel_dp.c

3222

if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) &&

drivers/gpu/drm/i915/display/intel_dp.c

3223

!intel_psr_pr_async_video_timing_supported(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

3229

static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

3241

if (!intel_dp_needs_as_sdp(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_dp.c

3275

if (intel_psr_pr_async_video_timing_supported(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

3279

static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

3285

if ((!intel_dp->colorimetry_support ||

drivers/gpu/drm/i915/display/intel_dp.c

330

static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

333

return intel_dp_rate_limit_len(intel_dp->common_rates,

drivers/gpu/drm/i915/display/intel_dp.c

334

intel_dp->num_common_rates, max_rate);

drivers/gpu/drm/i915/display/intel_dp.c

3341

intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

3345

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

337

int intel_dp_common_rate(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp.c

339

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

342

index < 0 || index >= intel_dp->num_common_rates))

drivers/gpu/drm/i915/display/intel_dp.c

345

return intel_dp->common_rates[index];

drivers/gpu/drm/i915/display/intel_dp.c

3461

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

3462

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

3483

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

3484

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

349

int intel_dp_max_common_rate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

351

return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);

drivers/gpu/drm/i915/display/intel_dp.c

3536

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

3539

if (intel_dp->needs_modeset_retry)

drivers/gpu/drm/i915/display/intel_dp.c

3542

intel_dp->needs_modeset_retry = true;

drivers/gpu/drm/i915/display/intel_dp.c

3545

intel_connector_queue_modeset_retry_work(intel_dp->attached_connector);

drivers/gpu/drm/i915/display/intel_dp.c

3554

if (connector->mst.dp == intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

3656

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

3657

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

3660

if (intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

369

static bool intel_dp_set_max_common_lane_count(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

3701

drm_dp_enhanced_frame_cap(intel_dp->dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

371

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3710

if (intel_dp->mso_link_count) {

drivers/gpu/drm/i915/display/intel_dp.c

3711

int n = intel_dp->mso_link_count;

drivers/gpu/drm/i915/display/intel_dp.c

3712

int overlap = intel_dp->mso_pixel_overlap;

drivers/gpu/drm/i915/display/intel_dp.c

373

int sink_max = intel_dp->max_sink_lane_count;

drivers/gpu/drm/i915/display/intel_dp.c

375

int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);

drivers/gpu/drm/i915/display/intel_dp.c

3751

intel_psr_compute_config(intel_dp, pipe_config, conn_state);

drivers/gpu/drm/i915/display/intel_dp.c

3752

intel_dp_compute_as_sdp(intel_dp, pipe_config);

drivers/gpu/drm/i915/display/intel_dp.c

3753

intel_alpm_lobf_compute_config(intel_dp, pipe_config, conn_state);

drivers/gpu/drm/i915/display/intel_dp.c

3755

intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);

drivers/gpu/drm/i915/display/intel_dp.c

3756

intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);

drivers/gpu/drm/i915/display/intel_dp.c

3758

return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,

drivers/gpu/drm/i915/display/intel_dp.c

376

int old_max_common_lane_count = intel_dp->max_common_lane_count;

drivers/gpu/drm/i915/display/intel_dp.c

3762

void intel_dp_set_link_params(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

3765

memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));

drivers/gpu/drm/i915/display/intel_dp.c

3766

intel_dp->link.active = false;

drivers/gpu/drm/i915/display/intel_dp.c

3767

intel_dp->needs_modeset_retry = false;

drivers/gpu/drm/i915/display/intel_dp.c

3768

intel_dp->link_rate = link_rate;

drivers/gpu/drm/i915/display/intel_dp.c

3769

intel_dp->lane_count = lane_count;

drivers/gpu/drm/i915/display/intel_dp.c

3772

void intel_dp_reset_link_params(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

3774

intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3775

intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3776

intel_dp->link.mst_probed_lane_count = 0;

drivers/gpu/drm/i915/display/intel_dp.c

3777

intel_dp->link.mst_probed_rate = 0;

drivers/gpu/drm/i915/display/intel_dp.c

3778

intel_dp->link.retrain_disabled = false;

drivers/gpu/drm/i915/display/intel_dp.c

3779

intel_dp->link.seq_train_failures = 0;

drivers/gpu/drm/i915/display/intel_dp.c

3787

struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));

drivers/gpu/drm/i915/display/intel_dp.c

3789

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

3795

intel_pps_backlight_on(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3801

struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));

drivers/gpu/drm/i915/display/intel_dp.c

3802

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3804

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

3809

intel_pps_backlight_off(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

381

intel_dp->max_common_lane_count = min3(source_max, sink_max, lane_max);

drivers/gpu/drm/i915/display/intel_dp.c

3813

static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

3823

return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&

drivers/gpu/drm/i915/display/intel_dp.c

3824

drm_dp_is_branch(intel_dp->dpcd) &&

drivers/gpu/drm/i915/display/intel_dp.c

3825

intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;

drivers/gpu/drm/i915/display/intel_dp.c

383

return intel_dp->max_common_lane_count != old_max_common_lane_count;

drivers/gpu/drm/i915/display/intel_dp.c

386

int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

388

return intel_dp->max_common_lane_count;

drivers/gpu/drm/i915/display/intel_dp.c

391

static int forced_lane_count(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

393

return clamp(intel_dp->link.force_lane_count, 1, intel_dp_max_common_lane_count(intel_dp));

drivers/gpu/drm/i915/display/intel_dp.c

396

int intel_dp_max_lane_count(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

400

if (intel_dp->link.force_lane_count)

drivers/gpu/drm/i915/display/intel_dp.c

4002

intel_dp_init_source_oui(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4004

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4008

if (READ_ONCE(intel_dp->oui_valid))

drivers/gpu/drm/i915/display/intel_dp.c

401

lane_count = forced_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4011

WRITE_ONCE(intel_dp->oui_valid, true);

drivers/gpu/drm/i915/display/intel_dp.c

4017

if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)

drivers/gpu/drm/i915/display/intel_dp.c

4022

intel_dp->last_oui_write = jiffies;

drivers/gpu/drm/i915/display/intel_dp.c

4026

if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) {

drivers/gpu/drm/i915/display/intel_dp.c

4028

WRITE_ONCE(intel_dp->oui_valid, false);

drivers/gpu/drm/i915/display/intel_dp.c

403

lane_count = intel_dp->link.max_lane_count;

drivers/gpu/drm/i915/display/intel_dp.c

4031

intel_dp->last_oui_write = jiffies;

drivers/gpu/drm/i915/display/intel_dp.c

4034

void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4036

WRITE_ONCE(intel_dp->oui_valid, false);

drivers/gpu/drm/i915/display/intel_dp.c

4039

void intel_dp_wait_source_oui(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4041

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4042

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

4049

wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,

drivers/gpu/drm/i915/display/intel_dp.c

4054

void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)

drivers/gpu/drm/i915/display/intel_dp.c

4056

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4057

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

4061

if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)

drivers/gpu/drm/i915/display/intel_dp.c

4065

if (downstream_hpd_needs_d0(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

4068

ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);

drivers/gpu/drm/i915/display/intel_dp.c

4070

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4075

intel_dp_init_source_oui(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4082

ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);

drivers/gpu/drm/i915/display/intel_dp.c

4100

intel_dp_get_dpcd(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4113

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

4120

if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) {

drivers/gpu/drm/i915/display/intel_dp.c

4121

intel_dp_get_dpcd(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4125

intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);

drivers/gpu/drm/i915/display/intel_dp.c

4128

intel_dp_reset_link_params(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4129

intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp.c

4130

intel_dp->link.active = true;

drivers/gpu/drm/i915/display/intel_dp.c

4138

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

4145

if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,

drivers/gpu/drm/i915/display/intel_dp.c

416

static int intel_dp_min_lane_count(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4169

if (CAN_PANEL_REPLAY(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

418

if (intel_dp->link.force_lane_count)

drivers/gpu/drm/i915/display/intel_dp.c

4180

static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4182

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4186

memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));

drivers/gpu/drm/i915/display/intel_dp.c

4188

if (!drm_dp_is_branch(intel_dp->dpcd))

drivers/gpu/drm/i915/display/intel_dp.c

419

return forced_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4191

if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,

drivers/gpu/drm/i915/display/intel_dp.c

4192

intel_dp->pcon_dsc_dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

4193

sizeof(intel_dp->pcon_dsc_dpcd)) < 0)

drivers/gpu/drm/i915/display/intel_dp.c

4198

(int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

4233

static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4235

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

4251

if (drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) &&

drivers/gpu/drm/i915/display/intel_dp.c

4263

intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

4266

if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&

drivers/gpu/drm/i915/display/intel_dp.c

4267

drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&

drivers/gpu/drm/i915/display/intel_dp.c

4274

static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4276

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4283

max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;

drivers/gpu/drm/i915/display/intel_dp.c

4286

max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4298

if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))

drivers/gpu/drm/i915/display/intel_dp.c

4301

ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);

drivers/gpu/drm/i915/display/intel_dp.c

4305

ret = poll_timeout_us(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux),

drivers/gpu/drm/i915/display/intel_dp.c

4311

ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,

drivers/gpu/drm/i915/display/intel_dp.c

4315

ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,

drivers/gpu/drm/i915/display/intel_dp.c

4319

ret = drm_dp_pcon_frl_enable(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp.c

4326

ret = poll_timeout_us(is_active = intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),

drivers/gpu/drm/i915/display/intel_dp.c

4334

intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);

drivers/gpu/drm/i915/display/intel_dp.c

4335

intel_dp->frl.is_trained = true;

drivers/gpu/drm/i915/display/intel_dp.c

4337

intel_dp->frl.trained_rate_gbps);

drivers/gpu/drm/i915/display/intel_dp.c

4342

static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4344

if (drm_dp_is_branch(intel_dp->dpcd) &&

drivers/gpu/drm/i915/display/intel_dp.c

4345

intel_dp_has_hdmi_sink(intel_dp) &&

drivers/gpu/drm/i915/display/intel_dp.c

4346

intel_dp_hdmi_sink_max_frl(intel_dp) > 0)

drivers/gpu/drm/i915/display/intel_dp.c

4353

int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4361

ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);

drivers/gpu/drm/i915/display/intel_dp.c

4367

ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);

drivers/gpu/drm/i915/display/intel_dp.c

4374

void intel_dp_check_frl_training(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4376

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4383

if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||

drivers/gpu/drm/i915/display/intel_dp.c

4384

!intel_dp_is_hdmi_2_1_sink(intel_dp) ||

drivers/gpu/drm/i915/display/intel_dp.c

4385

intel_dp->frl.is_trained)

drivers/gpu/drm/i915/display/intel_dp.c

4388

if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {

drivers/gpu/drm/i915/display/intel_dp.c

4393

ret = intel_dp_pcon_set_tmds_mode(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4394

mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);

drivers/gpu/drm/i915/display/intel_dp.c

4413

intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

4416

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

4420

int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

4421

int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

4429

intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

4433

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

4437

int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

4447

intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

4450

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4451

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

4461

if (!intel_dp_is_hdmi_2_1_sink(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

4471

if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||

drivers/gpu/drm/i915/display/intel_dp.c

4479

num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

4486

bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

4498

ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);

drivers/gpu/drm/i915/display/intel_dp.c

4503

void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

4506

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4511

if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)

drivers/gpu/drm/i915/display/intel_dp.c

4514

if (!drm_dp_is_branch(intel_dp->dpcd))

drivers/gpu/drm/i915/display/intel_dp.c

4517

tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0;

drivers/gpu/drm/i915/display/intel_dp.c

4519

if (drm_dp_dpcd_writeb(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp.c

4523

str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));

drivers/gpu/drm/i915/display/intel_dp.c

4555

if (drm_dp_dpcd_writeb(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp.c

4559

str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));

drivers/gpu/drm/i915/display/intel_dp.c

4563

if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)

drivers/gpu/drm/i915/display/intel_dp.c

4569

static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4573

if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,

drivers/gpu/drm/i915/display/intel_dp.c

4688

intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)

drivers/gpu/drm/i915/display/intel_dp.c

4690

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4696

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

4697

intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],

drivers/gpu/drm/i915/display/intel_dp.c

4700

intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],

drivers/gpu/drm/i915/display/intel_dp.c

4701

&intel_dp->desc, drm_dp_is_branch(intel_dp->dpcd),

drivers/gpu/drm/i915/display/intel_dp.c

4709

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

4710

int n = intel_dp->mso_link_count;

drivers/gpu/drm/i915/display/intel_dp.c

4711

int overlap = intel_dp->mso_pixel_overlap;

drivers/gpu/drm/i915/display/intel_dp.c

4733

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

4734

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

4757

static void intel_edp_mso_init(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4759

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4760

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

4764

if (intel_dp->edp_dpcd[0] < DP_EDP_14)

drivers/gpu/drm/i915/display/intel_dp.c

4767

if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {

drivers/gpu/drm/i915/display/intel_dp.c

4774

if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {

drivers/gpu/drm/i915/display/intel_dp.c

4782

mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,

drivers/gpu/drm/i915/display/intel_dp.c

4791

intel_dp->mso_link_count = mso;

drivers/gpu/drm/i915/display/intel_dp.c

4792

intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;

drivers/gpu/drm/i915/display/intel_dp.c

4796

intel_edp_set_data_override_rates(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4798

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

4799

int *sink_rates = intel_dp->sink_rates;

drivers/gpu/drm/i915/display/intel_dp.c

4802

for (i = 0; i < intel_dp->num_sink_rates; i++) {

drivers/gpu/drm/i915/display/intel_dp.c

4804

intel_dp->sink_rates[i]))

drivers/gpu/drm/i915/display/intel_dp.c

4807

sink_rates[count++] = intel_dp->sink_rates[i];

drivers/gpu/drm/i915/display/intel_dp.c

4809

intel_dp->num_sink_rates = count;

drivers/gpu/drm/i915/display/intel_dp.c

4813

intel_edp_set_sink_rates(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4815

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4817

intel_dp->num_sink_rates = 0;

drivers/gpu/drm/i915/display/intel_dp.c

4819

if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {

drivers/gpu/drm/i915/display/intel_dp.c

4824

ret = drm_dp_dpcd_read_data(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp.c

4856

intel_dp->sink_rates[i] = rate;

drivers/gpu/drm/i915/display/intel_dp.c

4858

intel_dp->num_sink_rates = i;

drivers/gpu/drm/i915/display/intel_dp.c

4865

if (intel_dp->num_sink_rates)

drivers/gpu/drm/i915/display/intel_dp.c

4866

intel_dp->use_rate_select = true;

drivers/gpu/drm/i915/display/intel_dp.c

4868

intel_dp_set_sink_rates(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4870

intel_edp_set_data_override_rates(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4874

intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)

drivers/gpu/drm/i915/display/intel_dp.c

4876

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4880

drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);

drivers/gpu/drm/i915/display/intel_dp.c

4882

if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)

drivers/gpu/drm/i915/display/intel_dp.c

4885

drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,

drivers/gpu/drm/i915/display/intel_dp.c

4886

drm_dp_is_branch(intel_dp->dpcd));

drivers/gpu/drm/i915/display/intel_dp.c

4887

intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);

drivers/gpu/drm/i915/display/intel_dp.c

4889

intel_dp->colorimetry_support =

drivers/gpu/drm/i915/display/intel_dp.c

4890

intel_dp_get_colorimetry_status(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4901

if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,

drivers/gpu/drm/i915/display/intel_dp.c

4902

intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==

drivers/gpu/drm/i915/display/intel_dp.c

4903

sizeof(intel_dp->edp_dpcd)) {

drivers/gpu/drm/i915/display/intel_dp.c

4905

(int)sizeof(intel_dp->edp_dpcd),

drivers/gpu/drm/i915/display/intel_dp.c

4906

intel_dp->edp_dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

4908

intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;

drivers/gpu/drm/i915/display/intel_dp.c

491

int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

4915

intel_dp_init_source_oui(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4918

ret = drm_dp_dpcd_read_byte(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,

drivers/gpu/drm/i915/display/intel_dp.c

4919

&intel_dp->alpm_dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

4927

intel_psr_init_dpcd(intel_dp, connector);

drivers/gpu/drm/i915/display/intel_dp.c

4929

intel_edp_set_sink_rates(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4930

intel_dp_set_max_sink_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4933

intel_dp_detect_dsc_caps(intel_dp, connector);

drivers/gpu/drm/i915/display/intel_dp.c

4939

intel_dp_has_sink_count(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4941

if (!intel_dp->attached_connector)

drivers/gpu/drm/i915/display/intel_dp.c

4944

return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,

drivers/gpu/drm/i915/display/intel_dp.c

4945

intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

4946

&intel_dp->desc);

drivers/gpu/drm/i915/display/intel_dp.c

4949

void intel_dp_update_sink_caps(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4951

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4953

intel_dp_set_sink_rates(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4954

intel_dp_set_max_sink_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

496

if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

4960

if (intel_dp_set_common_link_params(intel_dp) &&

drivers/gpu/drm/i915/display/intel_dp.c

4961

!intel_dp->reset_link_params) {

drivers/gpu/drm/i915/display/intel_dp.c

4964

intel_dp->reset_link_params = true;

drivers/gpu/drm/i915/display/intel_dp.c

4969

intel_dp_get_dpcd(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4973

if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)

drivers/gpu/drm/i915/display/intel_dp.c

498

drm_dp_tunnel_available_bw(intel_dp->tunnel));

drivers/gpu/drm/i915/display/intel_dp.c

4980

if (!intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

4981

drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,

drivers/gpu/drm/i915/display/intel_dp.c

4982

drm_dp_is_branch(intel_dp->dpcd));

drivers/gpu/drm/i915/display/intel_dp.c

4984

intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);

drivers/gpu/drm/i915/display/intel_dp.c

4986

intel_dp->colorimetry_support =

drivers/gpu/drm/i915/display/intel_dp.c

4987

intel_dp_get_colorimetry_status(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4989

intel_dp_update_sink_caps(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4992

if (intel_dp_has_sink_count(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

4993

ret = drm_dp_read_sink_count(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp.c

5002

intel_dp->sink_count = ret;

drivers/gpu/drm/i915/display/intel_dp.c

5011

if (!intel_dp->sink_count)

drivers/gpu/drm/i915/display/intel_dp.c

5015

return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

5016

intel_dp->downstream_ports) == 0;

drivers/gpu/drm/i915/display/intel_dp.c

503

bool intel_dp_has_joiner(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5030

intel_dp_mst_mode_choose(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

5033

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5038

if (!intel_dp_mst_source_support(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

5042

!(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B))

drivers/gpu/drm/i915/display/intel_dp.c

5049

intel_dp_mst_detect(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

505

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5051

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5052

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

5056

sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

5058

mst_detect = intel_dp_mst_mode_choose(intel_dp, sink_mst_mode);

drivers/gpu/drm/i915/display/intel_dp.c

506

struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5063

str_yes_no(intel_dp_mst_source_support(intel_dp)),

drivers/gpu/drm/i915/display/intel_dp.c

5072

intel_dp_mst_configure(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5074

if (!intel_dp_mst_source_support(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

5077

intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST;

drivers/gpu/drm/i915/display/intel_dp.c

5079

if (intel_dp->is_mst)

drivers/gpu/drm/i915/display/intel_dp.c

508

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

5080

intel_dp_mst_prepare_probe(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5082

drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, intel_dp->is_mst);

drivers/gpu/drm/i915/display/intel_dp.c

5085

intel_dp->mst_detect = DRM_DP_SST;

drivers/gpu/drm/i915/display/intel_dp.c

5089

intel_dp_mst_disconnect(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5091

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5093

if (!intel_dp->is_mst)

drivers/gpu/drm/i915/display/intel_dp.c

5098

intel_dp->is_mst, intel_dp->mst.mgr.mst_state);

drivers/gpu/drm/i915/display/intel_dp.c

5099

intel_dp->is_mst = false;

drivers/gpu/drm/i915/display/intel_dp.c

5100

drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, intel_dp->is_mst);

drivers/gpu/drm/i915/display/intel_dp.c

511

if (intel_dp->mso_link_count)

drivers/gpu/drm/i915/display/intel_dp.c

5122

intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)

drivers/gpu/drm/i915/display/intel_dp.c

5124

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5133

if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 3) != 3)

drivers/gpu/drm/i915/display/intel_dp.c

5137

return drm_dp_dpcd_readb(&intel_dp->aux, DP_LINK_SERVICE_IRQ_VECTOR_ESI0,

drivers/gpu/drm/i915/display/intel_dp.c

514

if (intel_dp_is_edp(intel_dp) &&

drivers/gpu/drm/i915/display/intel_dp.c

5141

return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;

drivers/gpu/drm/i915/display/intel_dp.c

5144

static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])

drivers/gpu/drm/i915/display/intel_dp.c

5149

if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,

drivers/gpu/drm/i915/display/intel_dp.c

5158

static bool intel_dp_get_sink_irq_esi_sst(struct intel_dp *intel_dp, u8 esi[4])

drivers/gpu/drm/i915/display/intel_dp.c

5166

if (drm_dp_dpcd_read_data(&intel_dp->aux, DP_SINK_COUNT, esi, 2) != 0)

drivers/gpu/drm/i915/display/intel_dp.c

5169

if (intel_dp->dpcd[DP_DPCD_REV] < DP_DPCD_REV_12)

drivers/gpu/drm/i915/display/intel_dp.c

5173

if (drm_dp_dpcd_read_byte(&intel_dp->aux, DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &esi[3]) != 0)

drivers/gpu/drm/i915/display/intel_dp.c

5180

static bool intel_dp_ack_sink_irq_esi_sst(struct intel_dp *intel_dp, u8 esi[4])

drivers/gpu/drm/i915/display/intel_dp.c

5186

if (drm_dp_dpcd_write_byte(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, esi[1]) != 0)

drivers/gpu/drm/i915/display/intel_dp.c

5189

if (intel_dp->dpcd[DP_DPCD_REV] < DP_DPCD_REV_12)

drivers/gpu/drm/i915/display/intel_dp.c

5193

if (drm_dp_dpcd_write_byte(&intel_dp->aux, DP_LINK_SERVICE_IRQ_VECTOR_ESI0, esi[3]) != 0)

drivers/gpu/drm/i915/display/intel_dp.c

5203

static bool intel_dp_get_and_ack_sink_irq_esi_sst(struct intel_dp *intel_dp, u8 esi[4])

drivers/gpu/drm/i915/display/intel_dp.c

5205

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5206

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

5207

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

5209

if (!intel_dp_get_sink_irq_esi_sst(intel_dp, esi))

drivers/gpu/drm/i915/display/intel_dp.c

5224

if (!intel_dp_ack_sink_irq_esi_sst(intel_dp, esi))

drivers/gpu/drm/i915/display/intel_dp.c

523

static int dg2_max_source_rate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

525

return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;

drivers/gpu/drm/i915/display/intel_dp.c

528

static int icl_max_source_rate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

530

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

532

if (intel_encoder_is_combo(encoder) && !intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

538

static int ehl_max_source_rate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

540

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

546

static int mtl_max_source_rate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

548

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

549

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

561

static int vbt_max_link_rate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

563

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

568

if (intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

5686

static bool intel_dp_link_ok(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

5689

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

569

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

5690

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

5691

bool uhbr = intel_dp->link_rate >= 1000000;

drivers/gpu/drm/i915/display/intel_dp.c

5696

intel_dp->lane_count);

drivers/gpu/drm/i915/display/intel_dp.c

5698

ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);

drivers/gpu/drm/i915/display/intel_dp.c

5703

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp.c

5713

intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)

drivers/gpu/drm/i915/display/intel_dp.c

5717

drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst.mgr, esi, ack, &handled);

drivers/gpu/drm/i915/display/intel_dp.c

5720

intel_hdcp_handle_cp_irq(intel_dp->attached_connector);

drivers/gpu/drm/i915/display/intel_dp.c

5725

static bool intel_dp_handle_link_service_irq(struct intel_dp *intel_dp, u8 irq_mask);

drivers/gpu/drm/i915/display/intel_dp.c

5742

intel_dp_check_mst_status(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5744

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5745

bool force_retrain = intel_dp->link.force_retrain;

drivers/gpu/drm/i915/display/intel_dp.c

5754

if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {

drivers/gpu/drm/i915/display/intel_dp.c

5766

intel_dp_mst_hpd_irq(intel_dp, esi, ack);

drivers/gpu/drm/i915/display/intel_dp.c

5773

if (new_irqs && !intel_dp_ack_sink_irq_esi(intel_dp, ack))

drivers/gpu/drm/i915/display/intel_dp.c

5777

drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp.c

5785

if (intel_dp_handle_link_service_irq(intel_dp, ack[3]))

drivers/gpu/drm/i915/display/intel_dp.c

5801

intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5806

is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp.c

5807

if (intel_dp->frl.is_trained && !is_active) {

drivers/gpu/drm/i915/display/intel_dp.c

5808

if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)

drivers/gpu/drm/i915/display/intel_dp.c

5812

if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)

drivers/gpu/drm/i915/display/intel_dp.c

5815

drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);

drivers/gpu/drm/i915/display/intel_dp.c

5817

intel_dp->frl.is_trained = false;

drivers/gpu/drm/i915/display/intel_dp.c

582

intel_dp_set_source_rates(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5820

intel_dp_check_frl_training(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5825

intel_dp_read_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])

drivers/gpu/drm/i915/display/intel_dp.c

5831

if (intel_dp_mst_active_streams(intel_dp) > 0)

drivers/gpu/drm/i915/display/intel_dp.c

5832

err = drm_dp_dpcd_read_data(&intel_dp->aux, DP_LANE0_1_STATUS_ESI,

drivers/gpu/drm/i915/display/intel_dp.c

5835

err = drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp.c

5843

WRITE_ONCE(intel_dp->downstream_port_changed, true);

drivers/gpu/drm/i915/display/intel_dp.c

5849

intel_dp_needs_link_retrain(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5853

if (!intel_dp->link.active)

drivers/gpu/drm/i915/display/intel_dp.c

5864

if (intel_psr_enabled(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

5867

if (intel_dp->link.force_retrain)

drivers/gpu/drm/i915/display/intel_dp.c

5870

if (intel_dp_read_link_status(intel_dp, link_status) < 0)

drivers/gpu/drm/i915/display/intel_dp.c

5881

if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,

drivers/gpu/drm/i915/display/intel_dp.c

5882

intel_dp->lane_count))

drivers/gpu/drm/i915/display/intel_dp.c

5885

if (intel_dp->link.retrain_disabled)

drivers/gpu/drm/i915/display/intel_dp.c

5888

if (intel_dp->link.seq_train_failures)

drivers/gpu/drm/i915/display/intel_dp.c

5892

return !intel_dp_link_ok(intel_dp, link_status) &&

drivers/gpu/drm/i915/display/intel_dp.c

5893

!intel_psr_link_ok(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5896

bool intel_dp_has_connector(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

5899

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5907

encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

5913

encoder = &intel_dp->mst.stream_encoders[pipe]->base;

drivers/gpu/drm/i915/display/intel_dp.c

5936

int intel_dp_get_active_pipes(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

5940

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5954

if (!intel_dp_has_connector(intel_dp, conn_state))

drivers/gpu/drm/i915/display/intel_dp.c

5987

static bool intel_dp_is_connected(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5989

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

5992

intel_dp->is_mst;

drivers/gpu/drm/i915/display/intel_dp.c

5999

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

6003

if (!intel_dp_is_connected(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6011

if (!intel_dp_needs_link_retrain(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6014

ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);

drivers/gpu/drm/i915/display/intel_dp.c

6021

if (!intel_dp_needs_link_retrain(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6027

str_yes_no(intel_dp->link.force_retrain));

drivers/gpu/drm/i915/display/intel_dp.c

6033

intel_dp->link.force_retrain = false;

drivers/gpu/drm/i915/display/intel_dp.c

6053

void intel_dp_check_link_state(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

6055

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6058

if (!intel_dp_is_connected(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6061

if (!intel_dp_needs_link_retrain(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6067

static void intel_dp_handle_device_service_irq(struct intel_dp *intel_dp, u8 irq_mask)

drivers/gpu/drm/i915/display/intel_dp.c

6069

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6074

intel_dp_test_request(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6077

intel_hdcp_handle_cp_irq(intel_dp->attached_connector);

drivers/gpu/drm/i915/display/intel_dp.c

6088

static bool intel_dp_handle_link_service_irq(struct intel_dp *intel_dp, u8 irq_mask)

drivers/gpu/drm/i915/display/intel_dp.c

609

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6090

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6091

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

6092

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

6099

intel_dp->reset_link_params = true;

drivers/gpu/drm/i915/display/intel_dp.c

6104

intel_dp_check_link_state(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6107

intel_dp_handle_hdmi_link_status_change(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6117

&intel_dp->aux))

drivers/gpu/drm/i915/display/intel_dp.c

6137

intel_dp_short_pulse(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

6142

intel_dp_test_reset(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6144

if (!intel_dp_get_and_ack_sink_irq_esi_sst(intel_dp, esi))

drivers/gpu/drm/i915/display/intel_dp.c

615

intel_dp->source_rates || intel_dp->num_source_rates);

drivers/gpu/drm/i915/display/intel_dp.c

6152

if (intel_dp_has_sink_count(intel_dp) &&

drivers/gpu/drm/i915/display/intel_dp.c

6153

DP_GET_SINK_COUNT(esi[0]) != intel_dp->sink_count)

drivers/gpu/drm/i915/display/intel_dp.c

6157

intel_dp_handle_device_service_irq(intel_dp, esi[1]);

drivers/gpu/drm/i915/display/intel_dp.c

6165

if (intel_dp_handle_link_service_irq(intel_dp, esi[3]))

drivers/gpu/drm/i915/display/intel_dp.c

6169

drm_dp_cec_irq(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp.c

6171

if (READ_ONCE(intel_dp->downstream_port_changed)) {

drivers/gpu/drm/i915/display/intel_dp.c

6172

WRITE_ONCE(intel_dp->downstream_port_changed, false);

drivers/gpu/drm/i915/display/intel_dp.c

6176

intel_psr_short_pulse(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6178

if (intel_alpm_get_error(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

6179

intel_alpm_disable(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6180

intel_dp->alpm.sink_alpm_error = true;

drivers/gpu/drm/i915/display/intel_dp.c

6183

if (intel_dp_test_short_pulse(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6191

intel_dp_detect_dpcd(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

6193

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6194

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6195

u8 *dpcd = intel_dp->dpcd;

drivers/gpu/drm/i915/display/intel_dp.c

6198

if (drm_WARN_ON(display->drm, intel_dp_is_edp(intel_dp)))

drivers/gpu/drm/i915/display/intel_dp.c

6201

WRITE_ONCE(intel_dp->downstream_port_changed, false);

drivers/gpu/drm/i915/display/intel_dp.c

6205

if (!intel_dp_get_dpcd(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6208

intel_dp->mst_detect = intel_dp_mst_detect(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6215

if (intel_dp_has_sink_count(intel_dp) &&

drivers/gpu/drm/i915/display/intel_dp.c

6216

intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {

drivers/gpu/drm/i915/display/intel_dp.c

6217

return intel_dp->sink_count ?

drivers/gpu/drm/i915/display/intel_dp.c

6221

if (intel_dp->mst_detect == DRM_DP_MST)

drivers/gpu/drm/i915/display/intel_dp.c

6225

if (drm_probe_ddc(&intel_dp->aux.ddc))

drivers/gpu/drm/i915/display/intel_dp.c

6229

if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {

drivers/gpu/drm/i915/display/intel_dp.c

6230

type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;

drivers/gpu/drm/i915/display/intel_dp.c

6235

type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &

drivers/gpu/drm/i915/display/intel_dp.c

6248

edp_detect(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

625

max_rate = mtl_max_source_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

630

max_rate = dg2_max_source_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6311

intel_dp_get_edid(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

6313

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

6325

return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);

drivers/gpu/drm/i915/display/intel_dp.c

6329

intel_dp_update_dfp(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

6332

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6333

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

6335

intel_dp->dfp.max_bpc =

drivers/gpu/drm/i915/display/intel_dp.c

6336

drm_dp_downstream_max_bpc(intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

6337

intel_dp->downstream_ports, drm_edid);

drivers/gpu/drm/i915/display/intel_dp.c

6339

intel_dp->dfp.max_dotclock =

drivers/gpu/drm/i915/display/intel_dp.c

6340

drm_dp_downstream_max_dotclock(intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

6341

intel_dp->downstream_ports);

drivers/gpu/drm/i915/display/intel_dp.c

6343

intel_dp->dfp.min_tmds_clock =

drivers/gpu/drm/i915/display/intel_dp.c

6344

drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

6345

intel_dp->downstream_ports,

drivers/gpu/drm/i915/display/intel_dp.c

6347

intel_dp->dfp.max_tmds_clock =

drivers/gpu/drm/i915/display/intel_dp.c

6348

drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

6349

intel_dp->downstream_ports,

drivers/gpu/drm/i915/display/intel_dp.c

635

max_rate = ehl_max_source_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6352

intel_dp->dfp.pcon_max_frl_bw =

drivers/gpu/drm/i915/display/intel_dp.c

6353

drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

6354

intel_dp->downstream_ports);

drivers/gpu/drm/i915/display/intel_dp.c

6359

intel_dp->dfp.max_bpc,

drivers/gpu/drm/i915/display/intel_dp.c

6360

intel_dp->dfp.max_dotclock,

drivers/gpu/drm/i915/display/intel_dp.c

6361

intel_dp->dfp.min_tmds_clock,

drivers/gpu/drm/i915/display/intel_dp.c

6362

intel_dp->dfp.max_tmds_clock,

drivers/gpu/drm/i915/display/intel_dp.c

6363

intel_dp->dfp.pcon_max_frl_bw);

drivers/gpu/drm/i915/display/intel_dp.c

6365

intel_dp_get_pcon_dsc_cap(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6369

intel_dp_can_ycbcr420(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

637

max_rate = icl_max_source_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6371

if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) &&

drivers/gpu/drm/i915/display/intel_dp.c

6372

(!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))

drivers/gpu/drm/i915/display/intel_dp.c

6375

if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&

drivers/gpu/drm/i915/display/intel_dp.c

6376

dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))

drivers/gpu/drm/i915/display/intel_dp.c

6379

if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&

drivers/gpu/drm/i915/display/intel_dp.c

6380

dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))

drivers/gpu/drm/i915/display/intel_dp.c

6387

intel_dp_update_420(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

6389

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6390

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

6392

intel_dp->dfp.ycbcr420_passthrough =

drivers/gpu/drm/i915/display/intel_dp.c

6393

drm_dp_downstream_420_passthrough(intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

6394

intel_dp->downstream_ports);

drivers/gpu/drm/i915/display/intel_dp.c

6396

intel_dp->dfp.ycbcr_444_to_420 =

drivers/gpu/drm/i915/display/intel_dp.c

6397

intel_lspcon_active(dp_to_dig_port(intel_dp)) ||

drivers/gpu/drm/i915/display/intel_dp.c

6398

drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

6399

intel_dp->downstream_ports);

drivers/gpu/drm/i915/display/intel_dp.c

6400

intel_dp->dfp.rgb_to_ycbcr =

drivers/gpu/drm/i915/display/intel_dp.c

6401

drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

6402

intel_dp->downstream_ports,

drivers/gpu/drm/i915/display/intel_dp.c

6405

connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6410

str_yes_no(intel_dp->dfp.rgb_to_ycbcr),

drivers/gpu/drm/i915/display/intel_dp.c

6412

str_yes_no(intel_dp->dfp.ycbcr_444_to_420));

drivers/gpu/drm/i915/display/intel_dp.c

6416

intel_dp_set_edid(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

6418

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6419

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

6423

intel_dp_unset_edid(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6424

drm_edid = intel_dp_get_edid(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6435

intel_dp_update_dfp(intel_dp, drm_edid);

drivers/gpu/drm/i915/display/intel_dp.c

6436

intel_dp_update_420(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6438

drm_dp_cec_attach(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp.c

6443

intel_dp_unset_edid(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

6445

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

6447

drm_dp_cec_unset_edid(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp.c

6451

intel_dp->dfp.max_bpc = 0;

drivers/gpu/drm/i915/display/intel_dp.c

6452

intel_dp->dfp.max_dotclock = 0;

drivers/gpu/drm/i915/display/intel_dp.c

6453

intel_dp->dfp.min_tmds_clock = 0;

drivers/gpu/drm/i915/display/intel_dp.c

6454

intel_dp->dfp.max_tmds_clock = 0;

drivers/gpu/drm/i915/display/intel_dp.c

6456

intel_dp->dfp.pcon_max_frl_bw = 0;

drivers/gpu/drm/i915/display/intel_dp.c

6458

intel_dp->dfp.ycbcr_444_to_420 = false;

drivers/gpu/drm/i915/display/intel_dp.c

6466

intel_dp_sink_supports_as_sdp_v2(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

6491

if (drm_dp_dpcd_read_byte(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp.c

6498

if (intel_dp->psr.sink_panel_replay_support &&

drivers/gpu/drm/i915/display/intel_dp.c

6499

!intel_psr_pr_async_video_timing_supported(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6506

intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

6508

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6510

intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&

drivers/gpu/drm/i915/display/intel_dp.c

6511

drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

6513

if (!intel_dp->as_sdp_supported)

drivers/gpu/drm/i915/display/intel_dp.c

6517

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6518

intel_dp->as_sdp_v2_supported = true;

drivers/gpu/drm/i915/display/intel_dp.c

6520

intel_dp->as_sdp_v2_supported = intel_dp_sink_supports_as_sdp_v2(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6523

static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool force_on_external)

drivers/gpu/drm/i915/display/intel_dp.c

6525

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

6527

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

653

vbt_max_rate = vbt_max_link_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6533

if (intel_dp->is_mst)

drivers/gpu/drm/i915/display/intel_dp.c

6539

void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external)

drivers/gpu/drm/i915/display/intel_dp.c

6541

drm_dp_dpcd_set_probe(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp.c

6542

intel_dp_needs_dpcd_probe(intel_dp, force_on_external));

drivers/gpu/drm/i915/display/intel_dp.c

6552

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

6553

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6571

intel_pps_vdd_on(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6574

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6575

status = edp_detect(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6577

status = intel_dp_detect_dpcd(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6582

!intel_dp_mst_verify_dpcd_state(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6594

intel_dp_test_reset(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6604

intel_dp->psr.sink_panel_replay_support = false;

drivers/gpu/drm/i915/display/intel_dp.c

6610

intel_dp_mst_disconnect(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6612

intel_dp_tunnel_disconnect(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6617

intel_dp_init_source_oui(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6619

ret = intel_dp_tunnel_detect(intel_dp, ctx);

drivers/gpu/drm/i915/display/intel_dp.c

662

intel_dp->source_rates = source_rates;

drivers/gpu/drm/i915/display/intel_dp.c

6629

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

663

intel_dp->num_source_rates = size;

drivers/gpu/drm/i915/display/intel_dp.c

6630

intel_psr_init_dpcd(intel_dp, connector);

drivers/gpu/drm/i915/display/intel_dp.c

6632

intel_dp_detect_dsc_caps(intel_dp, connector);

drivers/gpu/drm/i915/display/intel_dp.c

6634

intel_dp_detect_sdp_caps(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6636

if (intel_dp->reset_link_params) {

drivers/gpu/drm/i915/display/intel_dp.c

6637

intel_dp_reset_link_params(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6638

intel_dp->reset_link_params = false;

drivers/gpu/drm/i915/display/intel_dp.c

6641

intel_dp_mst_configure(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6643

intel_dp_print_rates(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6645

if (intel_dp->is_mst) {

drivers/gpu/drm/i915/display/intel_dp.c

6663

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6664

intel_dp_check_link_state(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6671

intel_dp->aux.i2c_nack_count = 0;

drivers/gpu/drm/i915/display/intel_dp.c

6672

intel_dp->aux.i2c_defer_count = 0;

drivers/gpu/drm/i915/display/intel_dp.c

6674

intel_dp_set_edid(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6675

if (intel_dp_is_edp(intel_dp) || connector->detect_edid)

drivers/gpu/drm/i915/display/intel_dp.c

6679

if (status != connector_status_connected && !intel_dp->is_mst)

drivers/gpu/drm/i915/display/intel_dp.c

6680

intel_dp_unset_edid(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6682

intel_dp_dpcd_set_probe(intel_dp, false);

drivers/gpu/drm/i915/display/intel_dp.c

6684

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6687

intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

6688

intel_dp->downstream_ports);

drivers/gpu/drm/i915/display/intel_dp.c

6690

intel_pps_vdd_off(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6700

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

6708

intel_dp_unset_edid(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6713

intel_dp_set_edid(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6715

intel_dp_dpcd_set_probe(intel_dp, false);

drivers/gpu/drm/i915/display/intel_dp.c

6722

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

6729

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6739

intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

6740

intel_dp->downstream_ports);

drivers/gpu/drm/i915/display/intel_dp.c

6755

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

6756

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6764

intel_dp->aux.name, connector->base.kdev->kobj.name);

drivers/gpu/drm/i915/display/intel_dp.c

6766

intel_dp->aux.dev = connector->base.kdev;

drivers/gpu/drm/i915/display/intel_dp.c

6767

ret = drm_dp_aux_register(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp.c

6769

drm_dp_cec_register_connector(&intel_dp->aux, &connector->base);

drivers/gpu/drm/i915/display/intel_dp.c

6790

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

6792

drm_dp_cec_unregister_connector(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp.c

6793

drm_dp_aux_unregister(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp.c

6815

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_dp.c

6821

intel_dp_tunnel_destroy(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6823

intel_pps_vdd_off_sync(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6829

intel_pps_wait_power_cycle(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6831

intel_dp_aux_fini(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6836

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

6838

intel_pps_vdd_off_sync(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6840

intel_dp_tunnel_suspend(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6845

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

6847

intel_pps_wait_power_cycle(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6967

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp.c

6974

if (intel_dp_mst_source_support(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

6975

ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp.c

6984

intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

701

static int intel_dp_link_config_rate(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

704

return intel_dp_common_rate(intel_dp, lc->link_rate_idx);

drivers/gpu/drm/i915/display/intel_dp.c

7054

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_dp.c

7060

!intel_pps_have_panel_power_or_vdd(intel_dp))) {

drivers/gpu/drm/i915/display/intel_dp.c

7089

intel_dp_dpcd_set_probe(intel_dp, true);

drivers/gpu/drm/i915/display/intel_dp.c

7091

intel_dp_read_dprx_caps(intel_dp, dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

7093

intel_dp->reset_link_params = true;

drivers/gpu/drm/i915/display/intel_dp.c

7094

intel_dp_invalidate_source_oui(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

7099

if (intel_dp->is_mst) {

drivers/gpu/drm/i915/display/intel_dp.c

7100

if (!intel_dp_check_mst_status(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

7102

} else if (!intel_dp_short_pulse(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

712

static int intel_dp_link_config_bw(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

715

return drm_dp_max_dprx_data_rate(intel_dp_link_config_rate(intel_dp, lc),

drivers/gpu/drm/i915/display/intel_dp.c

7157

intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *_connector)

drivers/gpu/drm/i915/display/intel_dp.c

7160

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

7161

enum port port = dp_to_dig_port(intel_dp)->base.port;

drivers/gpu/drm/i915/display/intel_dp.c

7163

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

7176

if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {

drivers/gpu/drm/i915/display/intel_dp.c

7183

if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))

drivers/gpu/drm/i915/display/intel_dp.c

7191

intel_edp_add_properties(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

7193

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

7194

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

7206

static void intel_edp_backlight_setup(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

7209

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

721

struct intel_dp *intel_dp = (struct intel_dp *)p; /* remove const */

drivers/gpu/drm/i915/display/intel_dp.c

7213

pipe = vlv_pps_backlight_initial_pipe(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

7218

static bool intel_edp_init_connector(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

7221

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

7223

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

7227

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

724

int bw_a = intel_dp_link_config_bw(intel_dp, lc_a);

drivers/gpu/drm/i915/display/intel_dp.c

7248

if (!intel_pps_init(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

725

int bw_b = intel_dp_link_config_bw(intel_dp, lc_b);

drivers/gpu/drm/i915/display/intel_dp.c

7269

intel_alpm_init(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

7272

has_dpcd = intel_edp_init_dpcd(intel_dp, connector);

drivers/gpu/drm/i915/display/intel_dp.c

730

return intel_dp_link_config_rate(intel_dp, lc_a) -

drivers/gpu/drm/i915/display/intel_dp.c

731

intel_dp_link_config_rate(intel_dp, lc_b);

drivers/gpu/drm/i915/display/intel_dp.c

7311

if (DISPLAY_VER(display) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&

drivers/gpu/drm/i915/display/intel_dp.c

7312

(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==

drivers/gpu/drm/i915/display/intel_dp.c

734

static void intel_dp_link_config_init(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

7348

intel_edp_mso_init(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

736

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

7369

intel_edp_backlight_setup(intel_dp, connector);

drivers/gpu/drm/i915/display/intel_dp.c

7371

intel_edp_add_properties(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

7373

intel_pps_init_late(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

7378

intel_pps_vdd_off_sync(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

7389

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_dp.c

7401

intel_dp->reset_link_params = true;

drivers/gpu/drm/i915/display/intel_dp.c

7404

intel_dp->DP = intel_de_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/intel_dp.c

7405

intel_dp->attached_connector = connector;

drivers/gpu/drm/i915/display/intel_dp.c

742

if (drm_WARN_ON(display->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp))))

drivers/gpu/drm/i915/display/intel_dp.c

7426

intel_dp_set_default_sink_rates(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

7427

intel_dp_set_default_max_sink_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

7430

vlv_pps_pipe_init(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

7432

intel_dp_aux_init(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

7433

connector->dp.dsc_decompression_aux = &intel_dp->aux;

drivers/gpu/drm/i915/display/intel_dp.c

7441

type, &intel_dp->aux.ddc);

drivers/gpu/drm/i915/display/intel_dp.c

745

num_common_lane_configs = ilog2(intel_dp_max_common_lane_count(intel_dp)) + 1;

drivers/gpu/drm/i915/display/intel_dp.c

7459

if (!intel_edp_init_connector(intel_dp, connector)) {

drivers/gpu/drm/i915/display/intel_dp.c

7460

intel_dp_aux_fini(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

7464

intel_dp_set_source_rates(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

7465

intel_dp_set_common_link_params(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

7466

intel_dp_reset_link_params(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

747

if (drm_WARN_ON(display->drm, intel_dp->num_common_rates * num_common_lane_configs >

drivers/gpu/drm/i915/display/intel_dp.c

7471

intel_dp_add_properties(intel_dp, &connector->base);

drivers/gpu/drm/i915/display/intel_dp.c

7473

if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

748

ARRAY_SIZE(intel_dp->link.configs)))

drivers/gpu/drm/i915/display/intel_dp.c

7480

intel_dp->frl.is_trained = false;

drivers/gpu/drm/i915/display/intel_dp.c

7481

intel_dp->frl.trained_rate_gbps = 0;

drivers/gpu/drm/i915/display/intel_dp.c

7483

intel_psr_init(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

7498

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_dp.c

7503

intel_dp_aux_fini(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

751

intel_dp->link.num_configs = intel_dp->num_common_rates * num_common_lane_configs;

drivers/gpu/drm/i915/display/intel_dp.c

7515

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_dp.c

7520

intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

7522

if (!intel_dp_mst_source_support(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

7525

if (intel_dp->is_mst)

drivers/gpu/drm/i915/display/intel_dp.c

7526

drm_dp_mst_topology_mgr_suspend(&intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp.c

753

lc = &intel_dp->link.configs[0];

drivers/gpu/drm/i915/display/intel_dp.c

7538

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_dp.c

754

for (i = 0; i < intel_dp->num_common_rates; i++) {

drivers/gpu/drm/i915/display/intel_dp.c

7544

intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

7546

if (!intel_dp_mst_source_support(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

7549

ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst.mgr, true);

drivers/gpu/drm/i915/display/intel_dp.c

7551

intel_dp->is_mst = false;

drivers/gpu/drm/i915/display/intel_dp.c

7552

drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, false);

drivers/gpu/drm/i915/display/intel_dp.c

7577

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

7580

intel_psr_compute_config_late(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

7586

intel_alpm_lobf_compute_config_late(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

763

sort_r(intel_dp->link.configs, intel_dp->link.num_configs,

drivers/gpu/drm/i915/display/intel_dp.c

764

sizeof(intel_dp->link.configs[0]),

drivers/gpu/drm/i915/display/intel_dp.c

7641

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

7643

if (!intel_dp_can_join(intel_dp, num_joined_pipes))

drivers/gpu/drm/i915/display/intel_dp.c

766

intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

769

void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count)

drivers/gpu/drm/i915/display/intel_dp.c

771

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

774

if (drm_WARN_ON(display->drm, idx < 0 || idx >= intel_dp->link.num_configs))

drivers/gpu/drm/i915/display/intel_dp.c

777

lc = &intel_dp->link.configs[idx];

drivers/gpu/drm/i915/display/intel_dp.c

779

*link_rate = intel_dp_link_config_rate(intel_dp, lc);

drivers/gpu/drm/i915/display/intel_dp.c

783

int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count)

drivers/gpu/drm/i915/display/intel_dp.c

785

int link_rate_idx = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates,

drivers/gpu/drm/i915/display/intel_dp.c

790

for (i = 0; i < intel_dp->link.num_configs; i++) {

drivers/gpu/drm/i915/display/intel_dp.c

791

const struct intel_dp_link_config *lc = &intel_dp->link.configs[i];

drivers/gpu/drm/i915/display/intel_dp.c

802

static bool intel_dp_set_common_rates(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

804

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

805

int num_old_common_rates = intel_dp->num_common_rates;

drivers/gpu/drm/i915/display/intel_dp.c

809

!intel_dp->num_source_rates || !intel_dp->num_sink_rates);

drivers/gpu/drm/i915/display/intel_dp.c

812

static_assert(__same_type(old_common_rates[0], intel_dp->common_rates[0]) &&

drivers/gpu/drm/i915/display/intel_dp.c

813

sizeof(old_common_rates) == sizeof(intel_dp->common_rates));

drivers/gpu/drm/i915/display/intel_dp.c

814

memcpy(old_common_rates, intel_dp->common_rates,

drivers/gpu/drm/i915/display/intel_dp.c

817

intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,

drivers/gpu/drm/i915/display/intel_dp.c

818

intel_dp->num_source_rates,

drivers/gpu/drm/i915/display/intel_dp.c

819

intel_dp->sink_rates,

drivers/gpu/drm/i915/display/intel_dp.c

820

intel_dp->num_sink_rates,

drivers/gpu/drm/i915/display/intel_dp.c

821

intel_dp->common_rates);

drivers/gpu/drm/i915/display/intel_dp.c

824

if (drm_WARN_ON(display->drm, intel_dp->num_common_rates == 0)) {

drivers/gpu/drm/i915/display/intel_dp.c

825

intel_dp->common_rates[0] = 162000;

drivers/gpu/drm/i915/display/intel_dp.c

826

intel_dp->num_common_rates = 1;

drivers/gpu/drm/i915/display/intel_dp.c

829

return num_old_common_rates != intel_dp->num_common_rates ||

drivers/gpu/drm/i915/display/intel_dp.c

830

memcmp(old_common_rates, intel_dp->common_rates,

drivers/gpu/drm/i915/display/intel_dp.c

835

static bool intel_dp_set_common_link_params(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

839

if (intel_dp_set_common_rates(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

842

if (intel_dp_set_max_common_lane_count(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

845

intel_dp_link_config_init(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

850

bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,

drivers/gpu/drm/i915/display/intel_dp.c

859

link_rate > intel_dp->link.max_rate)

drivers/gpu/drm/i915/display/intel_dp.c

863

lane_count > intel_dp_max_lane_count(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.h

106

int intel_dp_max_link_rate(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

107

int intel_dp_max_lane_count(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

109

int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);

drivers/gpu/drm/i915/display/intel_dp.h

110

int intel_dp_max_common_rate(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

111

int intel_dp_max_common_lane_count(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

112

int intel_dp_common_rate(struct intel_dp *intel_dp, int index);

drivers/gpu/drm/i915/display/intel_dp.h

114

int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count);

drivers/gpu/drm/i915/display/intel_dp.h

115

void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count);

drivers/gpu/drm/i915/display/intel_dp.h

116

void intel_dp_update_sink_caps(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

117

void intel_dp_reset_link_params(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

119

void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,

drivers/gpu/drm/i915/display/intel_dp.h

131

int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

135

bool intel_dp_has_joiner(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

158

bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16);

drivers/gpu/drm/i915/display/intel_dp.h

167

bool intel_dp_supports_fec(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

173

bool intel_dp_supports_fec(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

177

bool intel_dp_supports_dsc(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

191

void intel_dp_check_frl_training(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

192

void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

195

void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

196

void intel_dp_wait_source_oui(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

200

bool intel_dp_compute_config_limits(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

212

bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,

drivers/gpu/drm/i915/display/intel_dp.h

214

bool intel_dp_has_connector(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

223

void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external);

drivers/gpu/drm/i915/display/intel_dp.h

24

struct intel_dp;

drivers/gpu/drm/i915/display/intel_dp.h

56

void intel_dp_set_link_params(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

58

int intel_dp_get_active_pipes(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

63

void intel_dp_check_link_state(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

64

void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode);

drivers/gpu/drm/i915/display/intel_dp.h

65

void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

82

int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

90

bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

91

bool intel_dp_is_edp(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

105

static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp_aux.c

107

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

108

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

126

static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp_aux.c

128

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

129

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

140

return ilk_get_aux_clock_divider(intel_dp, index);

drivers/gpu/drm/i915/display/intel_dp_aux.c

143

static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp_aux.c

161

int intel_dp_aux_fw_sync_len(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_aux.c

174

if (intel_has_dpcd_quirk(intel_dp, QUIRK_FW_SYNC_LEN))

drivers/gpu/drm/i915/display/intel_dp_aux.c

190

static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_aux.c

194

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

214

static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_aux.c

218

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

219

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

234

DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(intel_dp_aux_fw_sync_len(intel_dp)) |

drivers/gpu/drm/i915/display/intel_dp_aux.c

251

intel_dp_aux_xfer(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_aux.c

256

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

257

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

269

ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

271

ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);

drivers/gpu/drm/i915/display/intel_dp_aux.c

279

if (!intel_dp_is_edp(intel_dp) &&

drivers/gpu/drm/i915/display/intel_dp_aux.c

299

if (intel_dp_is_edp(intel_dp) ||

drivers/gpu/drm/i915/display/intel_dp_aux.c

301

pps_wakeref = intel_pps_lock(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

309

vdd = intel_pps_vdd_on_unlocked(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

316

cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);

drivers/gpu/drm/i915/display/intel_dp_aux.c

318

intel_pps_check_power_unlocked(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

338

if (status != intel_dp->aux_busy_last_status) {

drivers/gpu/drm/i915/display/intel_dp_aux.c

341

intel_dp->aux.name, status);

drivers/gpu/drm/i915/display/intel_dp_aux.c

342

intel_dp->aux_busy_last_status = status;

drivers/gpu/drm/i915/display/intel_dp_aux.c

355

while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {

drivers/gpu/drm/i915/display/intel_dp_aux.c

356

u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,

drivers/gpu/drm/i915/display/intel_dp_aux.c

373

status = intel_dp_aux_wait_done(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

401

intel_dp->aux.name, status);

drivers/gpu/drm/i915/display/intel_dp_aux.c

413

intel_dp->aux.name, status);

drivers/gpu/drm/i915/display/intel_dp_aux.c

424

intel_dp->aux.name, status);

drivers/gpu/drm/i915/display/intel_dp_aux.c

440

intel_dp->aux.name, recv_bytes);

drivers/gpu/drm/i915/display/intel_dp_aux.c

454

cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);

drivers/gpu/drm/i915/display/intel_dp_aux.c

457

intel_pps_vdd_off_unlocked(intel_dp, false);

drivers/gpu/drm/i915/display/intel_dp_aux.c

460

intel_pps_unlock(intel_dp, pps_wakeref);

drivers/gpu/drm/i915/display/intel_dp_aux.c

499

struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);

drivers/gpu/drm/i915/display/intel_dp_aux.c

500

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

523

ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,

drivers/gpu/drm/i915/display/intel_dp_aux.c

546

ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,

drivers/gpu/drm/i915/display/intel_dp_aux.c

569

static intel_reg_t vlv_aux_ctl_reg(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_aux.c

571

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

585

static intel_reg_t vlv_aux_data_reg(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp_aux.c

587

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

59

intel_dp_aux_wait_done(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_aux.c

601

static intel_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_aux.c

603

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

61

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

617

static intel_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp_aux.c

619

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

62

intel_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

633

static intel_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_aux.c

635

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

651

static intel_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp_aux.c

653

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

669

static intel_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_aux.c

671

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

688

static intel_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp_aux.c

690

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

707

static intel_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_aux.c

709

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

729

static intel_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp_aux.c

731

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

751

static intel_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_aux.c

753

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

754

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

771

static intel_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp_aux.c

773

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

774

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

791

void intel_dp_aux_fini(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_aux.c

793

if (cpu_latency_qos_request_active(&intel_dp->pm_qos))

drivers/gpu/drm/i915/display/intel_dp_aux.c

794

cpu_latency_qos_remove_request(&intel_dp->pm_qos);

drivers/gpu/drm/i915/display/intel_dp_aux.c

796

kfree(intel_dp->aux.name);

drivers/gpu/drm/i915/display/intel_dp_aux.c

799

void intel_dp_aux_init(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_aux.c

801

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

802

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

808

intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

809

intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

811

intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

812

intel_dp->aux_ch_data_reg = tgl_aux_data_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

814

intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

815

intel_dp->aux_ch_data_reg = skl_aux_data_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

817

intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

818

intel_dp->aux_ch_data_reg = ilk_aux_data_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

820

intel_dp->aux_ch_ctl_reg = vlv_aux_ctl_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

821

intel_dp->aux_ch_data_reg = vlv_aux_data_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

823

intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

824

intel_dp->aux_ch_data_reg = g4x_aux_data_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

828

intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;

drivers/gpu/drm/i915/display/intel_dp_aux.c

830

intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;

drivers/gpu/drm/i915/display/intel_dp_aux.c

832

intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;

drivers/gpu/drm/i915/display/intel_dp_aux.c

834

intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;

drivers/gpu/drm/i915/display/intel_dp_aux.c

837

intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;

drivers/gpu/drm/i915/display/intel_dp_aux.c

839

intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;

drivers/gpu/drm/i915/display/intel_dp_aux.c

841

intel_dp->aux.drm_dev = display->drm;

drivers/gpu/drm/i915/display/intel_dp_aux.c

842

drm_dp_aux_init(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp_aux.c

845

intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %s/%s",

drivers/gpu/drm/i915/display/intel_dp_aux.c

849

intel_dp->aux.transfer = intel_dp_aux_transfer;

drivers/gpu/drm/i915/display/intel_dp_aux.c

850

cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);

drivers/gpu/drm/i915/display/intel_dp_aux.c

852

intel_dp_dpcd_set_probe(intel_dp, true);

drivers/gpu/drm/i915/display/intel_dp_aux.c

86

intel_dp->aux.name, timeout_ms, status);

drivers/gpu/drm/i915/display/intel_dp_aux.c

91

static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp_aux.c

93

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.h

13

struct intel_dp;

drivers/gpu/drm/i915/display/intel_dp_aux.h

16

void intel_dp_aux_fini(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.h

17

void intel_dp_aux_init(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.h

23

int intel_dp_aux_fw_sync_len(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

115

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

116

struct drm_dp_aux *aux = &intel_dp->aux;

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

121

intel_dp_wait_source_oui(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

178

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

182

if (drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &tmp) != 1) {

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

200

if (drm_dp_dpcd_read(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

216

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

222

if (drm_dp_dpcd_write(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

249

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

261

ret = drm_dp_dpcd_write(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

309

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

314

intel_dp_wait_source_oui(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

316

ret = drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &old_ctrl);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

341

drm_dp_dpcd_writeb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, ctrl) != 1)

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

386

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

395

ret = drm_dp_dpcd_write(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

452

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

459

ret = drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_PANEL_TARGET_LUMINANCE_VALUE, buf,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

462

drm_err(intel_dp->aux.drm_dev,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

480

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

488

drm_edp_backlight_set_level(&intel_dp->aux, &panel->backlight.edp.vesa.info, level);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

497

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

512

drm_edp_backlight_enable(&intel_dp->aux, &panel->backlight.edp.vesa.info, level);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

520

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

522

drm_edp_backlight_disable(&intel_dp->aux, &panel->backlight.edp.vesa.info);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

535

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

541

ret = drm_edp_backlight_init(&intel_dp->aux, &panel->backlight.edp.vesa.info,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

544

intel_dp->edp_dpcd, &current_level, &current_mode,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

613

check_if_vesa_backlight_possible(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

618

if (!(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP))

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

621

ret = drm_dp_dpcd_read_byte(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &bit_min);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

629

ret = drm_dp_dpcd_read_byte(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &bit_max);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

644

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

647

if ((intel_dp->edp_dpcd[3] & DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE) &&

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

648

(intel_dp->edp_dpcd[3] & DP_EDP_SMOOTH_BRIGHTNESS_CAPABLE)) {

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

656

if (drm_edp_backlight_supported(intel_dp->edp_dpcd) &&

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

657

check_if_vesa_backlight_possible(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

686

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

724

if (intel_dp->edp_dpcd[0] >= DP_EDP_15)

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

740

if (try_intel_interface && intel_dp->edp_dpcd[0] <= DP_EDP_14b &&

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

403

struct intel_dp *dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

44

struct intel_dp *dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

521

struct intel_dp *dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

895

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

903

else if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1000

lt_err(intel_dp, dp_phy, "Failed to get link status\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1005

lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1010

intel_dp_dump_link_status(intel_dp, dp_phy, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1011

lt_dbg(intel_dp, dp_phy, "Same voltage tried 5 times\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1016

intel_dp_dump_link_status(intel_dp, dp_phy, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1017

lt_dbg(intel_dp, dp_phy, "Max Voltage Swing reached\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1022

intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1024

if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1025

lt_err(intel_dp, dp_phy, "Failed to update link training\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

103

ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1036

if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

104

intel_dp->lttpr_common_caps);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1040

intel_dp_dump_link_status(intel_dp, dp_phy, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1041

lt_err(intel_dp, dp_phy, "Failed clock recovery %d times, giving up!\n",

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1053

intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1063

delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1064

intel_dp->dpcd, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1067

training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1073

if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1075

lt_err(intel_dp, dp_phy, "Failed to start channel equalization\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

108

lt_dbg(intel_dp, DP_PHY_DPRX, "LTTPR common capabilities: %*ph\n",

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1082

if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1084

lt_err(intel_dp, dp_phy, "Failed to get link status\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

109

(int)sizeof(intel_dp->lttpr_common_caps),

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1091

intel_dp_dump_link_status(intel_dp, dp_phy, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1092

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

110

intel_dp->lttpr_common_caps);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1100

lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP Training successful\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1105

intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1107

if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1108

lt_err(intel_dp, dp_phy, "Failed to update link training\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1115

intel_dp_dump_link_status(intel_dp, dp_phy, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1116

lt_dbg(intel_dp, dp_phy, "Channel equalization failed 5 times\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1123

intel_dp_post_lt_adj_req(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

113

if (intel_dp->lttpr_common_caps[0] < 0x14)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1132

if (!intel_dp_use_post_lt_adj_req(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1135

if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1137

lt_err(intel_dp, DP_PHY_DPRX, "Failed to get link status\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1147

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1148

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1155

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1156

lt_dbg(intel_dp, DP_PHY_DPRX, "Channel EQ check failed. cannot continue POST_LT_ADJ_REQ\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1162

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1163

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1170

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1171

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1178

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1179

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1186

if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1188

lt_err(intel_dp, DP_PHY_DPRX, "Failed to get link status\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

119

intel_dp_reset_lttpr_common_caps(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1193

if (intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1197

if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1198

lt_err(intel_dp, DP_PHY_DPRX, "Failed to update link training\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1209

static void intel_dp_stop_post_lt_adj_req(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1214

if (!intel_dp_use_post_lt_adj_req(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1222

drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1225

static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1228

int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1231

return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1235

intel_dp_128b132b_intra_hop(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

124

intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1241

ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_STATUS, &sink_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1243

lt_dbg(intel_dp, DP_PHY_DPRX, "Failed to read sink status\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1266

void intel_dp_stop_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1269

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1270

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1273

intel_dp->link.active = true;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1275

intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1279

ret = poll_timeout_us(ret = intel_dp_128b132b_intra_hop(intel_dp, crtc_state),

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1283

lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1289

intel_dp->link.seq_train_failures < MAX_SEQ_TRAIN_FAILURES) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

129

intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE -

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1290

int delay_ms = intel_dp->link.seq_train_failures ? 0 : 2000;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1297

intel_dp_link_train_phy(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1303

if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1306

if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1312

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1320

static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1326

intel_panel_preferred_fixed_mode(intel_dp->attached_connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1332

max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1339

static bool reduce_link_params_in_bw_order(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1347

i = intel_dp_link_config_index(intel_dp, crtc_state->port_clock, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1349

intel_dp_link_config_get(intel_dp, i, &link_rate, &lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

135

bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1351

if ((intel_dp->link.force_rate &&

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1352

intel_dp->link.force_rate != link_rate) ||

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1353

(intel_dp->link.force_lane_count &&

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1354

intel_dp->link.force_lane_count != lane_count))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1369

static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

137

return intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE -

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1374

if (intel_dp->link.force_rate)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1377

rate_index = intel_dp_rate_index(intel_dp->common_rates,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1378

intel_dp->num_common_rates,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1384

new_rate = intel_dp_common_rate(intel_dp, rate_index - 1);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1393

static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1395

if (intel_dp->link.force_lane_count)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1404

static bool reduce_link_params_in_rate_lane_order(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1412

link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1414

lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1415

link_rate = intel_dp_max_common_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1427

static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1432

return reduce_link_params_in_bw_order(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1435

return reduce_link_params_in_rate_lane_order(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1439

static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1445

if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1446

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1448

intel_dp->use_max_params = true;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1452

if (!reduce_link_params(intel_dp, crtc_state, &new_link_rate, &new_lane_count))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1455

if (intel_dp_is_edp(intel_dp) &&

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1456

!intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate, new_lane_count)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1457

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1462

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1467

intel_dp->link.max_rate = new_link_rate;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1468

intel_dp->link.max_lane_count = new_lane_count;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1474

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1477

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1479

if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1480

lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1484

if (intel_dp->hobl_active) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1485

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1487

intel_dp->hobl_failed = true;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1488

} else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

150

static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1500

intel_dp_link_train_all_phys(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1510

ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1511

intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1518

ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1520

intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1521

intel_dp->set_idle_link_train(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1524

ret = intel_dp_post_lt_adj_req(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1526

intel_dp_stop_post_lt_adj_req(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1535

intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

155

if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1550

if (!intel_dp_reset_link_train(intel_dp, crtc_state, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1552

lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS1\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1556

delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1559

if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1560

lt_err(intel_dp, DP_PHY_DPRX, "Failed to read TX FFE presets\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1565

intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1566

if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1567

lt_err(intel_dp, DP_PHY_DPRX, "Failed to set initial TX FFE settings\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1572

if (!intel_dp_set_link_train(intel_dp, crtc_state, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1574

lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

158

lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1584

if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1585

lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1590

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1591

lt_err(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1597

lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq done\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1602

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1603

lt_err(intel_dp, DP_PHY_DPRX, "Lane channel eq timeout\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1614

delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1616

intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1619

if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1620

lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1626

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1627

lt_err(intel_dp, DP_PHY_DPRX, "Max loop count reached\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1635

if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1636

lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1641

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1642

lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1647

lt_dbg(intel_dp, DP_PHY_DPRX, "Interlane align done\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1652

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1653

lt_err(intel_dp, DP_PHY_DPRX, "Interlane align timeout\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1667

intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1674

if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1676

lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2 CDS\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1691

if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1692

lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1699

lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align done\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1704

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1705

lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1710

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1711

lt_err(intel_dp, DP_PHY_DPRX, "CDS timeout\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1723

intel_dp_128b132b_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

173

if (intel_dp->link.active) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1730

ret = poll_timeout_us(ret = intel_dp_128b132b_intra_hop(intel_dp, crtc_state),

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1734

lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1738

if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) &&

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1739

intel_dp_128b132b_lane_cds(intel_dp, crtc_state, lttpr_count))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

174

if (lttpr_count < 0 || intel_dp_lttpr_transparent_mode_enabled(intel_dp))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1742

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1757

intel_dp_program_link_training_pattern(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1760

intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1777

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1781

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1793

lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1799

intel_dp_prepare_link_train(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

180

ret = drm_dp_lttpr_init(&intel_dp->aux, lttpr_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1802

passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1804

passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1806

if (intel_dp->link.force_train_failure) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1807

intel_dp->link.force_train_failure--;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1808

lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training failure\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1810

intel_dp->link.seq_train_failures = 0;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1814

intel_dp->link.seq_train_failures++;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

182

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1829

lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1833

if (intel_dp->link.seq_train_failures < MAX_SEQ_TRAIN_FAILURES)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1836

if (intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1839

intel_dp->link.retrain_disabled = true;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1842

lt_err(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after failure\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1844

lt_dbg(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after forced failure\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1847

void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

185

intel_dp_set_lttpr_transparent_mode(intel_dp, true);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1860

drm_dp_dpcd_writeb(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1864

lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1871

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1881

if (intel_dp->link.active)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1882

current_rate = intel_dp->link_rate;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1883

force_rate = intel_dp->link.force_rate;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1891

for (i = 0; i < intel_dp->num_source_rates; i++)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1893

intel_dp->source_rates[i] == force_rate ? "[" : "",

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1894

intel_dp->source_rates[i],

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1895

intel_dp->source_rates[i] == current_rate ? "*" : "",

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1896

intel_dp->source_rates[i] == force_rate ? "]" : "");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

190

intel_dp_set_lttpr_transparent_mode(intel_dp, false);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1903

static int parse_link_rate(struct intel_dp *intel_dp, const char __user *ubuf, size_t len)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1923

if (intel_dp_rate_index(intel_dp->source_rates,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1924

intel_dp->num_source_rates,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1942

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1946

rate = parse_link_rate(intel_dp, ubuf, len);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

195

intel_dp_reset_lttpr_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1954

intel_dp_reset_link_params(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1955

intel_dp->link.force_rate = rate;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1969

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1979

if (intel_dp->link.active)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1980

current_lane_count = intel_dp->lane_count;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1981

force_lane_count = intel_dp->link.force_lane_count;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

200

static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2044

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

205

lttpr_count = intel_dp_init_lttpr_phys(intel_dp, dpcd);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2056

intel_dp_reset_link_params(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2057

intel_dp->link.force_lane_count = lane_count;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2071

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2078

*val = intel_dp->link.max_rate;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

208

intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

209

drm_dp_dump_lttpr_desc(&intel_dp->aux, DP_PHY_LTTPR(i));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2090

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2097

*val = intel_dp->link.max_lane_count;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2109

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2116

*val = intel_dp->link.force_train_failure;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2127

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2137

intel_dp->link.force_train_failure = val;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

215

int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE])

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2151

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2158

*val = intel_dp->link.force_retrain;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2169

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

217

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2176

intel_dp->link.force_retrain = val;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2180

intel_hpd_trigger_irq(dp_to_dig_port(intel_dp));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

219

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2192

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2199

seq_printf(m, "%s\n", str_yes_no(intel_dp->link.retrain_disabled));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

227

if (drm_dp_dpcd_probe(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

231

if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

255

int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

257

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

264

if (!intel_dp_is_edp(intel_dp) &&

drivers/gpu/drm/i915/display/intel_dp_link_training.c

267

int err = intel_dp_read_dprx_caps(intel_dp, dpcd);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

272

lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

279

if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

280

intel_dp_reset_lttpr_common_caps(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

302

static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

305

const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

313

static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

316

const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

325

intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

328

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

329

int lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

337

static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

341

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

348

if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

349

voltage_max = intel_dp->voltage_max(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

351

voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

360

static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

363

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

370

if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

371

preemph_max = intel_dp->preemph_max(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

373

preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

382

static bool has_per_lane_signal_levels(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

385

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

387

return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) ||

drivers/gpu/drm/i915/display/intel_dp_link_training.c

392

static u8 intel_dp_get_lane_adjust_tx_ffe_preset(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

400

if (has_per_lane_signal_levels(intel_dp, dp_phy)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

412

static u8 intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

423

if (has_per_lane_signal_levels(intel_dp, dp_phy)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

435

preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

441

voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

448

static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

455

return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

458

return intel_dp_get_lane_adjust_vswing_preemph(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

486

intel_dp_get_adjust_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

495

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

501

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

511

u8 new = intel_dp_get_lane_adjust_train(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

513

if (intel_dp->train_set[lane] == new)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

516

intel_dp->train_set[lane] = new;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

523

static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

532

intel_dp_set_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

537

int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

538

u8 buf[sizeof(intel_dp->train_set) + 1];

drivers/gpu/drm/i915/display/intel_dp_link_training.c

541

intel_dp_program_link_training_pattern(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

546

memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

549

return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

568

intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

576

lt_dbg(intel_dp, dp_phy, "Using DP training pattern TPS%c\n",

drivers/gpu/drm/i915/display/intel_dp_link_training.c

579

intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

607

void intel_dp_set_signal_levels(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

611

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

614

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

618

TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

620

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

625

TRAIN_SET_VSWING_ARGS(intel_dp->train_set),

drivers/gpu/drm/i915/display/intel_dp_link_training.c

626

TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

629

if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

634

intel_dp_reset_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

639

memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

640

intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

641

return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

645

intel_dp_update_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

65

static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

654

intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

656

ret = drm_dp_dpcd_write(&intel_dp->aux, reg,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

657

intel_dp->train_set, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

67

memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

695

static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

70

static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

701

u8 train_set_lane = intel_dp->train_set[lane];

drivers/gpu/drm/i915/display/intel_dp_link_training.c

715

void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

72

intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT -

drivers/gpu/drm/i915/display/intel_dp_link_training.c

725

drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

729

intel_dp_pr_with_as_sdp_enabled(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

732

return intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) &&

drivers/gpu/drm/i915/display/intel_dp_link_training.c

737

static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

753

intel_dp_link_training_set_mode(intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

756

intel_dp_pr_with_as_sdp_enabled(intel_dp, crtc_state));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

759

void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

76

static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

773

drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

785

drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

786

drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET, rate_select);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

79

return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1];

drivers/gpu/drm/i915/display/intel_dp_link_training.c

795

static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

799

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

814

drm_dp_tps4_supported(intel_dp->dpcd);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

819

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

82

static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

822

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

832

drm_dp_tps3_supported(intel_dp->dpcd);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

837

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

840

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

847

static bool intel_dp_use_post_lt_adj_req(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

850

return intel_dp->set_idle_link_train &&

drivers/gpu/drm/i915/display/intel_dp_link_training.c

851

drm_dp_post_lt_adj_req_supported(intel_dp->dpcd) &&

drivers/gpu/drm/i915/display/intel_dp_link_training.c

852

intel_dp_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX) != DP_TRAINING_PATTERN_4;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

855

static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

859

intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, crtc_state->lane_count,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

86

u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

861

intel_dp_use_post_lt_adj_req(intel_dp, crtc_state));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

869

intel_dp_prepare_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

874

if (intel_dp->prepare_link_retrain)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

875

intel_dp->prepare_link_retrain(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

877

intel_dp_compute_rate(intel_dp, crtc_state->port_clock,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

88

if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

89

lt_dbg(intel_dp, dp_phy, "failed to read the PHY caps\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

894

lt_dbg(intel_dp, DP_PHY_DPRX, "Reloading eDP link rates\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

896

drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

901

lt_dbg(intel_dp, DP_PHY_DPRX, "Using LINK_BW_SET value %02x\n",

drivers/gpu/drm/i915/display/intel_dp_link_training.c

904

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

911

intel_dp_update_downspread_ctrl(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

912

intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

93

lt_dbg(intel_dp, dp_phy, "PHY capabilities: %*ph\n",

drivers/gpu/drm/i915/display/intel_dp_link_training.c

94

(int)sizeof(intel_dp->lttpr_phy_caps[0]),

drivers/gpu/drm/i915/display/intel_dp_link_training.c

945

intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

948

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

959

intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

969

delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

970

intel_dp->dpcd, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

974

if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

977

lt_err(intel_dp, dp_phy, "Failed to enable link training\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

98

static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

989

if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

998

if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

14

struct intel_dp;

drivers/gpu/drm/i915/display/intel_dp_link_training.h

16

int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]);

drivers/gpu/drm/i915/display/intel_dp_link_training.h

17

int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.h

18

bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.h

20

void intel_dp_link_training_set_mode(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

23

void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

27

bool intel_dp_get_adjust_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

31

void intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

35

void intel_dp_set_signal_levels(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

39

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

41

void intel_dp_stop_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

45

intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

54

void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1039

struct intel_dp *intel_dp = to_primary_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1043

if (intel_dp_mst_active_streams(intel_dp) == 1)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1044

intel_dp->link.active = false;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1059

struct intel_dp *intel_dp = to_primary_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

106

static struct intel_dp *to_primary_dp(struct intel_encoder *encoder)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1063

drm_atomic_get_old_mst_topology_state(&state->base, &intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1065

drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1073

last_mst_stream = intel_dp_mst_dec_active_streams(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1087

drm_dp_remove_payload_part1(&intel_dp->mst.mgr, new_mst_state, new_payload);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1096

drm_dp_check_act_status(&intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1098

drm_dp_remove_payload_part2(&intel_dp->mst.mgr, new_mst_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1121

drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port,

drivers/gpu/drm/i915/display/intel_dp_mst.c

114

int intel_dp_mst_active_streams(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1153

struct intel_dp *intel_dp = to_primary_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1155

if (intel_dp_mst_active_streams(intel_dp) == 0 &&

drivers/gpu/drm/i915/display/intel_dp_mst.c

116

return intel_dp->mst.active_streams;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1166

struct intel_dp *intel_dp = to_primary_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1168

if (intel_dp_mst_active_streams(intel_dp) == 0)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1180

static bool intel_mst_probed_link_params_valid(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1183

return intel_dp->link.mst_probed_rate == link_rate &&

drivers/gpu/drm/i915/display/intel_dp_mst.c

1184

intel_dp->link.mst_probed_lane_count == lane_count;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1187

static void intel_mst_set_probed_link_params(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

119

static bool intel_dp_mst_dec_active_streams(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1190

intel_dp->link.mst_probed_rate = link_rate;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1191

intel_dp->link.mst_probed_lane_count = lane_count;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1194

static void intel_mst_reprobe_topology(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1197

if (intel_mst_probed_link_params_valid(intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1201

drm_dp_mst_topology_queue_probe(&intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1203

intel_mst_set_probed_link_params(intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

121

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1215

struct intel_dp *intel_dp = to_primary_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1219

drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1229

first_mst_stream = intel_dp_mst_inc_active_streams(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1234

intel_dp_set_power(intel_dp, DP_SET_POWER_D0);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1236

drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port, true);

drivers/gpu/drm/i915/display/intel_dp_mst.c

124

intel_dp->mst.active_streams, intel_dp->mst.active_streams - 1);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1244

intel_mst_reprobe_topology(intel_dp, pipe_config);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1247

ret = drm_dp_add_payload_part1(&intel_dp->mst.mgr, mst_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

126

if (drm_WARN_ON(display->drm, intel_dp->mst.active_streams == 0))

drivers/gpu/drm/i915/display/intel_dp_mst.c

129

return --intel_dp->mst.active_streams == 0;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1309

struct intel_dp *intel_dp = to_primary_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1312

drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1314

bool first_mst_stream = intel_dp_mst_active_streams(intel_dp) == 1;

drivers/gpu/drm/i915/display/intel_dp_mst.c

132

static bool intel_dp_mst_inc_active_streams(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_mst.c

134

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1343

drm_dp_check_act_status(&intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1348

ret = drm_dp_add_payload_part2(&intel_dp->mst.mgr,

drivers/gpu/drm/i915/display/intel_dp_mst.c

137

intel_dp->mst.active_streams, intel_dp->mst.active_streams + 1);

drivers/gpu/drm/i915/display/intel_dp_mst.c

139

return intel_dp->mst.active_streams++ == 0;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1401

struct intel_dp *intel_dp = connector->mst.dp;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1411

drm_edid = drm_dp_mst_edid_read(&connector->base, &intel_dp->mst.mgr, connector->mst.port);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1472

struct intel_dp *intel_dp = connector->mst.dp;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1473

struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst.mgr;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1511

max_link_clock = intel_dp_max_link_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1512

max_lanes = intel_dp_max_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1514

max_rate = intel_dp_max_link_data_rate(intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1617

struct intel_dp *intel_dp = connector->mst.dp;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1620

return &intel_dp->mst.stream_encoders[crtc->pipe]->base.base;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1629

struct intel_dp *intel_dp = connector->mst.dp;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1642

return drm_dp_mst_detect_port(&connector->base, ctx, &intel_dp->mst.mgr,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1678

static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1682

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1698

intel_dp->attached_connector->base.max_bpc_property;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1706

intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1779

struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1780

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1781

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1792

connector->mst.dp = intel_dp;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1802

intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, connector);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1810

&intel_dp->mst.stream_encoders[pipe]->base.base;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1817

ret = mst_topology_add_connector_properties(intel_dp, &connector->base, pathprop);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1840

struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1842

intel_hpd_trigger_irq(dp_to_dig_port(intel_dp));

drivers/gpu/drm/i915/display/intel_dp_mst.c

1909

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1913

intel_dp->mst.stream_encoders[pipe] = mst_stream_encoder_create(dig_port, pipe);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1921

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1925

if (!HAS_DP_MST(display) || intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp_mst.c

1934

intel_dp->mst.mgr.cbs = &mst_topology_cbs;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1938

ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst.mgr, display->drm,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1939

&intel_dp->aux, 16,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1942

intel_dp->mst.mgr.cbs = NULL;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1949

bool intel_dp_mst_source_support(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1951

return intel_dp->mst.mgr.cbs;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1957

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1959

if (!intel_dp_mst_source_support(intel_dp))

drivers/gpu/drm/i915/display/intel_dp_mst.c

1962

drm_dp_mst_topology_mgr_destroy(&intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1965

intel_dp->mst.mgr.cbs = NULL;

drivers/gpu/drm/i915/display/intel_dp_mst.c

2136

void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_mst.c

2138

int link_rate = intel_dp_max_link_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

2139

int lane_count = intel_dp_max_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

2143

if (intel_dp->link.active)

drivers/gpu/drm/i915/display/intel_dp_mst.c

2146

if (intel_mst_probed_link_params_valid(intel_dp, link_rate, lane_count))

drivers/gpu/drm/i915/display/intel_dp_mst.c

2149

intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select);

drivers/gpu/drm/i915/display/intel_dp_mst.c

2151

intel_dp_link_training_set_mode(intel_dp, link_rate, false, false);

drivers/gpu/drm/i915/display/intel_dp_mst.c

2152

intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count,

drivers/gpu/drm/i915/display/intel_dp_mst.c

2153

drm_dp_enhanced_frame_cap(intel_dp->dpcd), false);

drivers/gpu/drm/i915/display/intel_dp_mst.c

2155

intel_mst_set_probed_link_params(intel_dp, link_rate, lane_count);

drivers/gpu/drm/i915/display/intel_dp_mst.c

2170

bool intel_dp_mst_verify_dpcd_state(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_mst.c

2172

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

2173

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp_mst.c

2174

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

2179

if (!intel_dp->is_mst)

drivers/gpu/drm/i915/display/intel_dp_mst.c

2182

ret = drm_dp_dpcd_readb(intel_dp->mst.mgr.aux, DP_MSTM_CTRL, &val);

drivers/gpu/drm/i915/display/intel_dp_mst.c

248

int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

253

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

277

mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

301

!intel_dp_supports_fec(intel_dp, connector, crtc_state))

drivers/gpu/drm/i915/display/intel_dp_mst.c

331

if (dsc && !intel_dp_dsc_valid_compressed_bpp(intel_dp, bpp_x16)) {

drivers/gpu/drm/i915/display/intel_dp_mst.c

397

slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst.mgr,

drivers/gpu/drm/i915/display/intel_dp_mst.c

442

static int mst_stream_compute_link_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

454

return intel_dp_mtp_tu_compute_config(intel_dp, crtc_state, conn_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

460

static int mst_stream_dsc_compute_link_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

465

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

477

return intel_dp_mtp_tu_compute_config(intel_dp, crtc_state, conn_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

518

adjust_limits_for_dsc_hblank_expansion_quirk(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

532

if (intel_dp_supports_dsc(intel_dp, connector, crtc_state)) {

drivers/gpu/drm/i915/display/intel_dp_mst.c

578

mst_stream_compute_config_limits(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

587

if (!intel_dp_compute_config_limits(intel_dp, conn_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

592

return adjust_limits_for_dsc_hblank_expansion_quirk(intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

605

struct intel_dp *intel_dp = to_primary_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

618

dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||

drivers/gpu/drm/i915/display/intel_dp_mst.c

619

!mst_stream_compute_config_limits(intel_dp, conn_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

623

ret = mst_stream_compute_link_config(intel_dp, pipe_config,

drivers/gpu/drm/i915/display/intel_dp_mst.c

638

if (dsc_needed && !intel_dp_supports_dsc(intel_dp, connector, pipe_config)) {

drivers/gpu/drm/i915/display/intel_dp_mst.c

649

str_yes_no(intel_dp->force_dsc_en));

drivers/gpu/drm/i915/display/intel_dp_mst.c

652

if (!mst_stream_compute_config_limits(intel_dp, conn_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

661

drm_WARN(display->drm, intel_dp->force_dsc_bpc,

drivers/gpu/drm/i915/display/intel_dp_mst.c

669

ret = mst_stream_dsc_compute_link_config(intel_dp, pipe_config,

drivers/gpu/drm/i915/display/intel_dp_mst.c

674

ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,

drivers/gpu/drm/i915/display/intel_dp_mst.c

707

struct intel_dp *intel_dp = to_primary_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

716

!intel_dp_supports_fec(intel_dp, connector, pipe_config))

drivers/gpu/drm/i915/display/intel_dp_mst.c

762

intel_psr_compute_config(intel_dp, pipe_config, conn_state);

drivers/gpu/drm/i915/display/intel_dp_mst.c

764

return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,

drivers/gpu/drm/i915/display/intel_dp_mst.c

774

struct intel_dp *mst_port)

drivers/gpu/drm/i915/display/intel_dp_mst.c

933

struct intel_dp *intel_dp = to_primary_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

937

ffs(intel_dp_mst_transcoder_mask(state, intel_dp)) - 1;

drivers/gpu/drm/i915/display/intel_dp_mst.h

16

struct intel_dp;

drivers/gpu/drm/i915/display/intel_dp_mst.h

21

int intel_dp_mst_active_streams(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.h

24

bool intel_dp_mst_source_support(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.h

31

void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.h

32

bool intel_dp_mst_verify_dpcd_state(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.h

34

int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_test.c

103

if (!intel_dp_link_params_valid(intel_dp, test_link_rate,

drivers/gpu/drm/i915/display/intel_dp_test.c

107

intel_dp->compliance.test_lane_count = test_lane_count;

drivers/gpu/drm/i915/display/intel_dp_test.c

108

intel_dp->compliance.test_link_rate = test_link_rate;

drivers/gpu/drm/i915/display/intel_dp_test.c

113

static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_test.c

115

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

122

status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,

drivers/gpu/drm/i915/display/intel_dp_test.c

131

status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,

drivers/gpu/drm/i915/display/intel_dp_test.c

138

status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,

drivers/gpu/drm/i915/display/intel_dp_test.c

145

status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,

drivers/gpu/drm/i915/display/intel_dp_test.c

157

intel_dp->compliance.test_data.bpc = 6;

drivers/gpu/drm/i915/display/intel_dp_test.c

160

intel_dp->compliance.test_data.bpc = 8;

drivers/gpu/drm/i915/display/intel_dp_test.c

166

intel_dp->compliance.test_data.video_pattern = test_pattern;

drivers/gpu/drm/i915/display/intel_dp_test.c

167

intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);

drivers/gpu/drm/i915/display/intel_dp_test.c

168

intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);

drivers/gpu/drm/i915/display/intel_dp_test.c

170

intel_dp->compliance.test_active = true;

drivers/gpu/drm/i915/display/intel_dp_test.c

175

static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_test.c

177

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

179

struct intel_connector *intel_connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp_test.c

183

intel_dp->aux.i2c_defer_count > 6) {

drivers/gpu/drm/i915/display/intel_dp_test.c

191

if (intel_dp->aux.i2c_nack_count > 0 ||

drivers/gpu/drm/i915/display/intel_dp_test.c

192

intel_dp->aux.i2c_defer_count > 0)

drivers/gpu/drm/i915/display/intel_dp_test.c

195

intel_dp->aux.i2c_nack_count,

drivers/gpu/drm/i915/display/intel_dp_test.c

196

intel_dp->aux.i2c_defer_count);

drivers/gpu/drm/i915/display/intel_dp_test.c

197

intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;

drivers/gpu/drm/i915/display/intel_dp_test.c

205

if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,

drivers/gpu/drm/i915/display/intel_dp_test.c

21

void intel_dp_test_reset(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_test.c

211

intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;

drivers/gpu/drm/i915/display/intel_dp_test.c

215

intel_dp->compliance.test_active = true;

drivers/gpu/drm/i915/display/intel_dp_test.c

220

static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_test.c

223

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

225

&intel_dp->compliance.test_data.phytest;

drivers/gpu/drm/i915/display/intel_dp_test.c

227

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_test.c

27

memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));

drivers/gpu/drm/i915/display/intel_dp_test.c

306

static void intel_dp_process_phy_request(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_test.c

309

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

31

void intel_dp_test_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_test.c

311

&intel_dp->compliance.test_data.phytest;

drivers/gpu/drm/i915/display/intel_dp_test.c

314

if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_test.c

321

intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_test.c

324

intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);

drivers/gpu/drm/i915/display/intel_dp_test.c

326

intel_dp_phy_pattern_update(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_test.c

328

drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,

drivers/gpu/drm/i915/display/intel_dp_test.c

329

intel_dp->train_set, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp_test.c

331

drm_dp_set_phy_test_pattern(&intel_dp->aux, data,

drivers/gpu/drm/i915/display/intel_dp_test.c

332

intel_dp->dpcd[DP_DPCD_REV]);

drivers/gpu/drm/i915/display/intel_dp_test.c

335

static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_test.c

337

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

339

&intel_dp->compliance.test_data.phytest;

drivers/gpu/drm/i915/display/intel_dp_test.c

341

if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {

drivers/gpu/drm/i915/display/intel_dp_test.c

348

intel_dp->compliance.test_active = true;

drivers/gpu/drm/i915/display/intel_dp_test.c

35

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

353

void intel_dp_test_request(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_test.c

355

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

360

status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);

drivers/gpu/drm/i915/display/intel_dp_test.c

370

response = intel_dp_autotest_link_training(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

374

response = intel_dp_autotest_video_pattern(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

378

response = intel_dp_autotest_edid(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

38

if (intel_dp->compliance.test_data.bpc != 0) {

drivers/gpu/drm/i915/display/intel_dp_test.c

382

response = intel_dp_autotest_phy_pattern(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

39

int bpp = 3 * intel_dp->compliance.test_data.bpc;

drivers/gpu/drm/i915/display/intel_dp_test.c

391

intel_dp->compliance.test_type = request;

drivers/gpu/drm/i915/display/intel_dp_test.c

394

status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);

drivers/gpu/drm/i915/display/intel_dp_test.c

402

static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_test.c

406

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

420

if (!intel_dp_has_connector(intel_dp, conn_state))

drivers/gpu/drm/i915/display/intel_dp_test.c

454

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_test.c

464

ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);

drivers/gpu/drm/i915/display/intel_dp_test.c

484

intel_dp_process_phy_request(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_test.c

49

if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {

drivers/gpu/drm/i915/display/intel_dp_test.c

491

bool intel_dp_test_phy(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_test.c

493

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

498

if (!intel_dp->compliance.test_active ||

drivers/gpu/drm/i915/display/intel_dp_test.c

499

intel_dp->compliance.test_type != DP_TEST_LINK_PHY_TEST_PATTERN)

drivers/gpu/drm/i915/display/intel_dp_test.c

523

bool intel_dp_test_short_pulse(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_test.c

525

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

528

switch (intel_dp->compliance.test_type) {

drivers/gpu/drm/i915/display/intel_dp_test.c

55

if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,

drivers/gpu/drm/i915/display/intel_dp_test.c

56

intel_dp->compliance.test_lane_count)) {

drivers/gpu/drm/i915/display/intel_dp_test.c

560

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_dp_test.c

57

index = intel_dp_rate_index(intel_dp->common_rates,

drivers/gpu/drm/i915/display/intel_dp_test.c

58

intel_dp->num_common_rates,

drivers/gpu/drm/i915/display/intel_dp_test.c

585

intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_test.c

59

intel_dp->compliance.test_link_rate);

drivers/gpu/drm/i915/display/intel_dp_test.c

594

intel_dp->compliance.test_active = true;

drivers/gpu/drm/i915/display/intel_dp_test.c

596

intel_dp->compliance.test_active = false;

drivers/gpu/drm/i915/display/intel_dp_test.c

61

limits->min_rate = intel_dp->compliance.test_link_rate;

drivers/gpu/drm/i915/display/intel_dp_test.c

613

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_dp_test.c

62

limits->max_rate = intel_dp->compliance.test_link_rate;

drivers/gpu/drm/i915/display/intel_dp_test.c

628

intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_test.c

629

if (intel_dp->compliance.test_active)

drivers/gpu/drm/i915/display/intel_dp_test.c

64

limits->min_lane_count = intel_dp->compliance.test_lane_count;

drivers/gpu/drm/i915/display/intel_dp_test.c

65

limits->max_lane_count = intel_dp->compliance.test_lane_count;

drivers/gpu/drm/i915/display/intel_dp_test.c

663

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_dp_test.c

678

intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_test.c

679

if (intel_dp->compliance.test_type ==

drivers/gpu/drm/i915/display/intel_dp_test.c

682

intel_dp->compliance.test_data.edid);

drivers/gpu/drm/i915/display/intel_dp_test.c

683

else if (intel_dp->compliance.test_type ==

drivers/gpu/drm/i915/display/intel_dp_test.c

686

intel_dp->compliance.test_data.hdisplay);

drivers/gpu/drm/i915/display/intel_dp_test.c

688

intel_dp->compliance.test_data.vdisplay);

drivers/gpu/drm/i915/display/intel_dp_test.c

690

intel_dp->compliance.test_data.bpc);

drivers/gpu/drm/i915/display/intel_dp_test.c

691

} else if (intel_dp->compliance.test_type ==

drivers/gpu/drm/i915/display/intel_dp_test.c

694

intel_dp->compliance.test_data.phytest.phy_pattern);

drivers/gpu/drm/i915/display/intel_dp_test.c

696

intel_dp->compliance.test_data.phytest.num_lanes);

drivers/gpu/drm/i915/display/intel_dp_test.c

698

intel_dp->compliance.test_data.phytest.link_rate);

drivers/gpu/drm/i915/display/intel_dp_test.c

700

intel_dp->train_set[0]);

drivers/gpu/drm/i915/display/intel_dp_test.c

717

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_dp_test.c

732

intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_test.c

733

seq_printf(m, "%02lx\n", intel_dp->compliance.test_type);

drivers/gpu/drm/i915/display/intel_dp_test.c

75

static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_test.c

77

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

85

status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,

drivers/gpu/drm/i915/display/intel_dp_test.c

94

status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,

drivers/gpu/drm/i915/display/intel_dp_test.h

11

struct intel_dp;

drivers/gpu/drm/i915/display/intel_dp_test.h

14

void intel_dp_test_reset(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.h

15

void intel_dp_test_request(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.h

16

void intel_dp_test_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_test.h

19

bool intel_dp_test_phy(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.h

20

bool intel_dp_test_short_pulse(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

105

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

120

static int update_tunnel_state(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

125

old_bw = get_current_link_bw(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

127

err = __update_tunnel_state(intel_dp, false);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

131

return has_tunnel_bw_changed(intel_dp, old_bw) ? 1 : 0;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

141

static int allocate_initial_tunnel_bw_for_pipes(struct intel_dp *intel_dp, u8 pipe_mask)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

143

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

144

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

158

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

165

err = drm_dp_tunnel_alloc_bw(intel_dp->tunnel, tunnel_bw);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

169

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

177

static int allocate_initial_tunnel_bw(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

183

err = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

187

return allocate_initial_tunnel_bw_for_pipes(intel_dp, pipe_mask);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

198

static int detect_new_tunnel(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

200

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

201

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

206

old_bw = get_current_link_bw(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

209

&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

213

intel_dp->tunnel = tunnel;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

215

ret = drm_dp_tunnel_enable_bw_alloc(intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

222

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

230

ret = allocate_initial_tunnel_bw(intel_dp, ctx);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

232

intel_dp_tunnel_destroy(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

237

ret = __update_tunnel_state(intel_dp, true);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

241

return has_tunnel_bw_changed(intel_dp, old_bw) ? 1 : 0;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

266

int intel_dp_tunnel_detect(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

270

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

273

if (intel_dp->tunnel) {

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

274

ret = update_tunnel_state(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

279

intel_dp_tunnel_destroy(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

282

return detect_new_tunnel(intel_dp, ctx);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

294

bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

296

return drm_dp_tunnel_bw_alloc_is_enabled(intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

30

void intel_dp_tunnel_disconnect(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

307

bool intel_dp_tunnel_pr_optimization_supported(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

309

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

314

return drm_dp_tunnel_pr_optimization_supported(intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

32

drm_dp_tunnel_destroy(intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

323

void intel_dp_tunnel_suspend(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

325

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

326

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

327

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

329

if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

33

intel_dp->tunnel = NULL;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

334

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

338

drm_dp_tunnel_disable_bw_alloc(intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

340

intel_dp->tunnel_suspended = true;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

351

void intel_dp_tunnel_resume(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

355

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

356

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

357

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

362

if (!intel_dp->tunnel_suspended)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

365

intel_dp->tunnel_suspended = false;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

369

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

381

err = intel_dp_read_dprx_caps(intel_dp, dpcd);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

384

drm_dp_tunnel_set_io_error(intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

389

err = drm_dp_tunnel_enable_bw_alloc(intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

401

err = allocate_initial_tunnel_bw_for_pipes(intel_dp, pipe_mask);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

410

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

44

void intel_dp_tunnel_destroy(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

451

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

455

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

46

if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

469

if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

47

drm_dp_tunnel_disable_bw_alloc(intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

479

old_crtc_state->dp_tunnel_ref.tunnel == intel_dp->tunnel)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

484

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

488

intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

49

intel_dp_tunnel_disconnect(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

490

return add_inherited_tunnel(state, intel_dp->tunnel, old_crtc);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

561

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

566

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

57

static int get_current_link_bw(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

575

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

59

int rate = intel_dp_max_common_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

598

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

60

int lane_count = intel_dp_max_common_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

608

err = check_group_state(state, intel_dp, connector,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

616

err = check_group_state(state, intel_dp, connector,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

62

return intel_dp_max_link_data_rate(intel_dp, rate, lane_count);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

622

return check_inherited_tunnel_state(state, intel_dp, old_conn_state);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

640

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

645

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

65

static int __update_tunnel_state(struct intel_dp *intel_dp, bool force_sink_update)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

650

if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

655

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

662

ret = drm_dp_tunnel_atomic_set_stream_bw(&state->base, intel_dp->tunnel,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

667

drm_dp_tunnel_ref_get(intel_dp->tunnel,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

67

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

68

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

71

ret = drm_dp_tunnel_update_state(intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

75

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

83

(ret == 0 || !drm_dp_tunnel_bw_alloc_is_enabled(intel_dp->tunnel)))

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

86

intel_dp_update_sink_caps(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

91

static bool has_tunnel_bw_changed(struct intel_dp *intel_dp, int old_bw)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

93

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

94

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

97

new_bw = get_current_link_bw(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

120

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

19

struct intel_dp;

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

26

int intel_dp_tunnel_detect(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx);

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

27

void intel_dp_tunnel_disconnect(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

28

void intel_dp_tunnel_destroy(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

29

void intel_dp_tunnel_resume(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

32

void intel_dp_tunnel_suspend(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

34

bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

35

bool intel_dp_tunnel_pr_optimization_supported(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

41

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

52

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

63

intel_dp_tunnel_detect(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx)

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

68

static inline void intel_dp_tunnel_disconnect(struct intel_dp *intel_dp) {}

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

69

static inline void intel_dp_tunnel_destroy(struct intel_dp *intel_dp) {}

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

70

static inline void intel_dp_tunnel_resume(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

73

static inline void intel_dp_tunnel_suspend(struct intel_dp *intel_dp) {}

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

75

static inline bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

80

static inline bool intel_dp_tunnel_pr_optimization_supported(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

90

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1132

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1133

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

952

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

953

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

101

ident = &intel_dp->desc.ident;

drivers/gpu/drm/i915/display/intel_lspcon.c

135

struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);

drivers/gpu/drm/i915/display/intel_lspcon.c

136

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

140

ret = drm_dp_dpcd_read(&intel_dp->aux, get_hdr_status_reg(lspcon),

drivers/gpu/drm/i915/display/intel_lspcon.c

156

struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);

drivers/gpu/drm/i915/display/intel_lspcon.c

157

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

159

struct i2c_adapter *ddc = &intel_dp->aux.ddc;

drivers/gpu/drm/i915/display/intel_lspcon.c

161

if (drm_lspcon_get_mode(intel_dp->aux.drm_dev, ddc, &current_mode)) {

drivers/gpu/drm/i915/display/intel_lspcon.c

183

struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);

drivers/gpu/drm/i915/display/intel_lspcon.c

184

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

214

struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);

drivers/gpu/drm/i915/display/intel_lspcon.c

215

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

218

struct i2c_adapter *ddc = &intel_dp->aux.ddc;

drivers/gpu/drm/i915/display/intel_lspcon.c

220

err = drm_lspcon_get_mode(intel_dp->aux.drm_dev, ddc, &current_mode);

drivers/gpu/drm/i915/display/intel_lspcon.c

231

err = drm_lspcon_set_mode(intel_dp->aux.drm_dev, ddc, mode,

drivers/gpu/drm/i915/display/intel_lspcon.c

245

struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);

drivers/gpu/drm/i915/display/intel_lspcon.c

246

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

263

struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);

drivers/gpu/drm/i915/display/intel_lspcon.c

264

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

265

struct i2c_adapter *ddc = &intel_dp->aux.ddc;

drivers/gpu/drm/i915/display/intel_lspcon.c

278

adaptor_type = drm_dp_dual_mode_detect(intel_dp->aux.drm_dev, ddc);

drivers/gpu/drm/i915/display/intel_lspcon.c

309

struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);

drivers/gpu/drm/i915/display/intel_lspcon.c

310

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

311

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

499

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_lspcon.c

506

ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_lspcon.c

509

ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_lspcon.c

646

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_lspcon.c

653

infoframes_enabled = _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_lspcon.c

655

infoframes_enabled = _lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_lspcon.c

66

static struct intel_dp *lspcon_to_intel_dp(struct intel_lspcon *lspcon)

drivers/gpu/drm/i915/display/intel_lspcon.c

682

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_lspcon.c

684

struct drm_connector *connector = &intel_dp->attached_connector->base;

drivers/gpu/drm/i915/display/intel_lspcon.c

694

if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) {

drivers/gpu/drm/i915/display/intel_lspcon.c

91

struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);

drivers/gpu/drm/i915/display/intel_lspcon.c

92

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

96

if (drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, drm_dp_is_branch(intel_dp->dpcd))) {

drivers/gpu/drm/i915/display/intel_lt_phy.c

1296

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1299

intel_psr_pause(intel_dp);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1308

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1310

intel_psr_resume(intel_dp);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1339

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1341

return (intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);

drivers/gpu/drm/i915/display/intel_pps.c

1003

wait_panel_on(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1004

intel_dp->pps.last_power_on = jiffies;

drivers/gpu/drm/i915/display/intel_pps.c

1017

void intel_pps_on(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1019

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

1022

with_intel_pps_lock(intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1023

intel_pps_on_unlocked(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1026

void intel_pps_off_unlocked(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1028

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1029

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1035

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

1040

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

1042

drm_WARN(display->drm, !intel_dp->pps.want_panel_vdd,

drivers/gpu/drm/i915/display/intel_pps.c

1045

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

1047

pp = ilk_get_pp_control(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

105

intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN,

drivers/gpu/drm/i915/display/intel_pps.c

1053

pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1055

intel_dp->pps.want_panel_vdd = false;

drivers/gpu/drm/i915/display/intel_pps.c

1060

wait_panel_off(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1061

intel_dp->pps.panel_power_off_time = ktime_get_boottime();

drivers/gpu/drm/i915/display/intel_pps.c

1063

intel_dp_invalidate_source_oui(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1068

fetch_and_zero(&intel_dp->pps.vdd_wakeref));

drivers/gpu/drm/i915/display/intel_pps.c

107

pps_name(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

1071

void intel_pps_off(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1073

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

1076

with_intel_pps_lock(intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1077

intel_pps_off_unlocked(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1081

void intel_pps_backlight_on(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1083

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1091

wait_backlight_on(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1093

with_intel_pps_lock(intel_dp) {

drivers/gpu/drm/i915/display/intel_pps.c

1094

intel_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1097

pp = ilk_get_pp_control(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1106

void intel_pps_backlight_off(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1108

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1110

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

1113

with_intel_pps_lock(intel_dp) {

drivers/gpu/drm/i915/display/intel_pps.c

1114

intel_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1117

pp = ilk_get_pp_control(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1124

intel_dp->pps.last_backlight_off = jiffies;

drivers/gpu/drm/i915/display/intel_pps.c

1125

edp_wait_backlight_off(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

113

pps_name(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

1135

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_pps.c

1139

with_intel_pps_lock(intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1140

is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;

drivers/gpu/drm/i915/display/intel_pps.c

1148

intel_pps_backlight_on(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1150

intel_pps_backlight_off(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1153

static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1155

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1156

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1157

enum pipe pipe = intel_dp->pps.vlv_pps_pipe;

drivers/gpu/drm/i915/display/intel_pps.c

1160

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_pps.c

1165

intel_pps_vdd_off_sync_unlocked(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1178

pps_name(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

1183

intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;

drivers/gpu/drm/i915/display/intel_pps.c

119

DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;

drivers/gpu/drm/i915/display/intel_pps.c

1194

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_pps.c

1196

drm_WARN(display->drm, intel_dp->pps.vlv_active_pipe == pipe,

drivers/gpu/drm/i915/display/intel_pps.c

1201

if (intel_dp->pps.vlv_pps_pipe != pipe)

drivers/gpu/drm/i915/display/intel_pps.c

1210

vlv_detach_power_sequencer(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1214

static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1216

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1217

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_pps.c

1220

if (g4x_dp_port_enabled(display, intel_dp->output_reg,

drivers/gpu/drm/i915/display/intel_pps.c

1228

void vlv_pps_pipe_init(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1230

intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;

drivers/gpu/drm/i915/display/intel_pps.c

1231

intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1235

void vlv_pps_pipe_reset(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1237

with_intel_pps_lock(intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1238

intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1241

enum pipe vlv_pps_backlight_initial_pipe(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1250

pipe = vlv_active_pipe(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1253

pipe = intel_dp->pps.vlv_pps_pipe;

drivers/gpu/drm/i915/display/intel_pps.c

1266

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_pps.c

1271

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_pps.c

1273

if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE &&

drivers/gpu/drm/i915/display/intel_pps.c

1274

intel_dp->pps.vlv_pps_pipe != crtc->pipe) {

drivers/gpu/drm/i915/display/intel_pps.c

1280

vlv_detach_power_sequencer(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1289

intel_dp->pps.vlv_active_pipe = crtc->pipe;

drivers/gpu/drm/i915/display/intel_pps.c

1291

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

1295

intel_dp->pps.vlv_pps_pipe = crtc->pipe;

drivers/gpu/drm/i915/display/intel_pps.c

1299

pps_name(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

1303

pps_init_delays(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1304

pps_init_registers(intel_dp, true);

drivers/gpu/drm/i915/display/intel_pps.c

1311

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_pps.c

1313

with_intel_pps_lock(intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1314

intel_dp->pps.vlv_active_pipe = INVALID_PIPE;

drivers/gpu/drm/i915/display/intel_pps.c

1317

static void pps_vdd_init(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1319

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1320

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1324

if (!edp_have_panel_vdd(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

1336

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

1337

drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);

drivers/gpu/drm/i915/display/intel_pps.c

1338

intel_dp->pps.vdd_wakeref = intel_display_power_get(display,

drivers/gpu/drm/i915/display/intel_pps.c

1342

bool intel_pps_have_panel_power_or_vdd(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1346

with_intel_pps_lock(intel_dp) {

drivers/gpu/drm/i915/display/intel_pps.c

1347

have_power = edp_have_panel_power(intel_dp) ||

drivers/gpu/drm/i915/display/intel_pps.c

1348

edp_have_panel_vdd(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1354

static void pps_init_timestamps(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1362

intel_dp->pps.panel_power_off_time = 0;

drivers/gpu/drm/i915/display/intel_pps.c

1363

intel_dp->pps.last_power_on = jiffies;

drivers/gpu/drm/i915/display/intel_pps.c

1364

intel_dp->pps.last_backlight_off = jiffies;

drivers/gpu/drm/i915/display/intel_pps.c

1368

intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct intel_pps_delays *seq)

drivers/gpu/drm/i915/display/intel_pps.c

1370

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1374

intel_pps_get_registers(intel_dp, &regs);

drivers/gpu/drm/i915/display/intel_pps.c

1376

pp_ctl = ilk_get_pp_control(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1406

intel_pps_dump_state(struct intel_dp *intel_dp, const char *state_name,

drivers/gpu/drm/i915/display/intel_pps.c

1409

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1418

intel_pps_verify_state(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1420

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1422

struct intel_pps_delays *sw = &intel_dp->pps.pps_delays;

drivers/gpu/drm/i915/display/intel_pps.c

1424

intel_pps_readout_hw_state(intel_dp, &hw);

drivers/gpu/drm/i915/display/intel_pps.c

1432

intel_pps_dump_state(intel_dp, "sw", sw);

drivers/gpu/drm/i915/display/intel_pps.c

1433

intel_pps_dump_state(intel_dp, "hw", &hw);

drivers/gpu/drm/i915/display/intel_pps.c

1455

static void pps_init_delays_bios(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_pps.c

1458

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1462

if (!pps_delays_valid(&intel_dp->pps.bios_pps_delays))

drivers/gpu/drm/i915/display/intel_pps.c

1463

intel_pps_readout_hw_state(intel_dp, &intel_dp->pps.bios_pps_delays);

drivers/gpu/drm/i915/display/intel_pps.c

1465

*bios = intel_dp->pps.bios_pps_delays;

drivers/gpu/drm/i915/display/intel_pps.c

1467

intel_pps_dump_state(intel_dp, "bios", bios);

drivers/gpu/drm/i915/display/intel_pps.c

1470

static void pps_init_delays_vbt(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_pps.c

1473

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1474

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_pps.c

1494

intel_pps_dump_state(intel_dp, "vbt", vbt);

drivers/gpu/drm/i915/display/intel_pps.c

1497

static void pps_init_delays_spec(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_pps.c

1500

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1511

intel_pps_dump_state(intel_dp, "spec", spec);

drivers/gpu/drm/i915/display/intel_pps.c

1514

static void pps_init_delays(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1516

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1518

*final = &intel_dp->pps.pps_delays;

drivers/gpu/drm/i915/display/intel_pps.c

1526

pps_init_delays_bios(intel_dp, &cur);

drivers/gpu/drm/i915/display/intel_pps.c

1527

pps_init_delays_vbt(intel_dp, &vbt);

drivers/gpu/drm/i915/display/intel_pps.c

1528

pps_init_delays_spec(intel_dp, &spec);

drivers/gpu/drm/i915/display/intel_pps.c

153

intel_de_write(display, intel_dp->output_reg, DP);

drivers/gpu/drm/i915/display/intel_pps.c

154

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/intel_pps.c

1542

intel_dp->pps.panel_power_up_delay = pps_units_to_msecs(final->power_up);

drivers/gpu/drm/i915/display/intel_pps.c

1543

intel_dp->pps.backlight_on_delay = pps_units_to_msecs(final->backlight_on);

drivers/gpu/drm/i915/display/intel_pps.c

1544

intel_dp->pps.backlight_off_delay = pps_units_to_msecs(final->backlight_off);

drivers/gpu/drm/i915/display/intel_pps.c

1545

intel_dp->pps.panel_power_down_delay = pps_units_to_msecs(final->power_down);

drivers/gpu/drm/i915/display/intel_pps.c

1546

intel_dp->pps.panel_power_cycle_delay = pps_units_to_msecs(final->power_cycle);

drivers/gpu/drm/i915/display/intel_pps.c

1550

intel_dp->pps.panel_power_up_delay,

drivers/gpu/drm/i915/display/intel_pps.c

1551

intel_dp->pps.panel_power_down_delay,

drivers/gpu/drm/i915/display/intel_pps.c

1552

intel_dp->pps.panel_power_cycle_delay);

drivers/gpu/drm/i915/display/intel_pps.c

1555

intel_dp->pps.backlight_on_delay,

drivers/gpu/drm/i915/display/intel_pps.c

1556

intel_dp->pps.backlight_off_delay);

drivers/gpu/drm/i915/display/intel_pps.c

156

intel_de_write(display, intel_dp->output_reg, DP | DP_PORT_EN);

drivers/gpu/drm/i915/display/intel_pps.c

157

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/intel_pps.c

1576

static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd)

drivers/gpu/drm/i915/display/intel_pps.c

1578

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1582

enum port port = dp_to_dig_port(intel_dp)->base.port;

drivers/gpu/drm/i915/display/intel_pps.c

1583

const struct intel_pps_delays *seq = &intel_dp->pps.pps_delays;

drivers/gpu/drm/i915/display/intel_pps.c

1587

intel_pps_get_registers(intel_dp, &regs);

drivers/gpu/drm/i915/display/intel_pps.c

159

intel_de_write(display, intel_dp->output_reg, DP & ~DP_PORT_EN);

drivers/gpu/drm/i915/display/intel_pps.c

160

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/intel_pps.c

1602

u32 pp = ilk_get_pp_control(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1670

void intel_pps_encoder_reset(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1672

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1674

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

1677

with_intel_pps_lock(intel_dp) {

drivers/gpu/drm/i915/display/intel_pps.c

1683

vlv_initial_power_sequencer_setup(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1685

pps_init_delays(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1686

pps_init_registers(intel_dp, false);

drivers/gpu/drm/i915/display/intel_pps.c

1687

pps_vdd_init(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1689

if (edp_have_panel_vdd(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

1690

edp_panel_vdd_schedule_off(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1694

bool intel_pps_init(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1698

intel_dp->pps.initializing = true;

drivers/gpu/drm/i915/display/intel_pps.c

1699

INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);

drivers/gpu/drm/i915/display/intel_pps.c

1701

pps_init_timestamps(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1703

with_intel_pps_lock(intel_dp) {

drivers/gpu/drm/i915/display/intel_pps.c

1704

ret = pps_initial_setup(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1706

pps_init_delays(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1707

pps_init_registers(intel_dp, false);

drivers/gpu/drm/i915/display/intel_pps.c

1708

pps_vdd_init(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1714

static void pps_init_late(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1716

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1717

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_pps.c

1718

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_pps.c

1728

intel_dp->pps.pps_idx != connector->panel.vbt.backlight.controller,

drivers/gpu/drm/i915/display/intel_pps.c

1731

intel_dp->pps.pps_idx, connector->panel.vbt.backlight.controller);

drivers/gpu/drm/i915/display/intel_pps.c

1734

intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;

drivers/gpu/drm/i915/display/intel_pps.c

1737

void intel_pps_init_late(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1739

with_intel_pps_lock(intel_dp) {

drivers/gpu/drm/i915/display/intel_pps.c

1741

pps_init_late(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1743

memset(&intel_dp->pps.pps_delays, 0, sizeof(intel_dp->pps.pps_delays));

drivers/gpu/drm/i915/display/intel_pps.c

1744

pps_init_delays(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1745

pps_init_registers(intel_dp, false);

drivers/gpu/drm/i915/display/intel_pps.c

1747

intel_dp->pps.initializing = false;

drivers/gpu/drm/i915/display/intel_pps.c

1749

if (edp_have_panel_vdd(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

1750

edp_panel_vdd_schedule_off(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1785

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_pps.c

1791

intel_dp->pps.panel_power_up_delay);

drivers/gpu/drm/i915/display/intel_pps.c

1793

intel_dp->pps.panel_power_down_delay);

drivers/gpu/drm/i915/display/intel_pps.c

1795

intel_dp->pps.panel_power_cycle_delay);

drivers/gpu/drm/i915/display/intel_pps.c

1797

intel_dp->pps.backlight_on_delay);

drivers/gpu/drm/i915/display/intel_pps.c

1799

intel_dp->pps.backlight_off_delay);

drivers/gpu/drm/i915/display/intel_pps.c

180

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_pps.c

184

intel_dp->pps.vlv_active_pipe != INVALID_PIPE &&

drivers/gpu/drm/i915/display/intel_pps.c

185

intel_dp->pps.vlv_active_pipe !=

drivers/gpu/drm/i915/display/intel_pps.c

186

intel_dp->pps.vlv_pps_pipe);

drivers/gpu/drm/i915/display/intel_pps.c

188

if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE)

drivers/gpu/drm/i915/display/intel_pps.c

189

pipes &= ~(1 << intel_dp->pps.vlv_pps_pipe);

drivers/gpu/drm/i915/display/intel_pps.c

192

intel_dp->pps.vlv_pps_pipe != INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_pps.c

194

if (intel_dp->pps.vlv_active_pipe != INVALID_PIPE)

drivers/gpu/drm/i915/display/intel_pps.c

195

pipes &= ~(1 << intel_dp->pps.vlv_active_pipe);

drivers/gpu/drm/i915/display/intel_pps.c

206

vlv_power_sequencer_pipe(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

208

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

209

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

215

drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

217

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE &&

drivers/gpu/drm/i915/display/intel_pps.c

218

intel_dp->pps.vlv_active_pipe != intel_dp->pps.vlv_pps_pipe);

drivers/gpu/drm/i915/display/intel_pps.c

220

if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE)

drivers/gpu/drm/i915/display/intel_pps.c

221

return intel_dp->pps.vlv_pps_pipe;

drivers/gpu/drm/i915/display/intel_pps.c

233

intel_dp->pps.vlv_pps_pipe = pipe;

drivers/gpu/drm/i915/display/intel_pps.c

237

pps_name(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

241

pps_init_delays(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

242

pps_init_registers(intel_dp, true);

drivers/gpu/drm/i915/display/intel_pps.c

248

vlv_power_sequencer_kick(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

250

return intel_dp->pps.vlv_pps_pipe;

drivers/gpu/drm/i915/display/intel_pps.c

254

bxt_power_sequencer_idx(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

256

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

257

int pps_idx = intel_dp->pps.pps_idx;

drivers/gpu/drm/i915/display/intel_pps.c

262

drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

264

if (!intel_dp->pps.bxt_pps_reset)

drivers/gpu/drm/i915/display/intel_pps.c

267

intel_dp->pps.bxt_pps_reset = false;

drivers/gpu/drm/i915/display/intel_pps.c

273

pps_init_registers(intel_dp, false);

drivers/gpu/drm/i915/display/intel_pps.c

30

static void pps_init_delays(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

31

static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd);

drivers/gpu/drm/i915/display/intel_pps.c

319

vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

321

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

322

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

329

intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,

drivers/gpu/drm/i915/display/intel_pps.c

33

static const char *pps_name(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

332

if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)

drivers/gpu/drm/i915/display/intel_pps.c

333

intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,

drivers/gpu/drm/i915/display/intel_pps.c

336

if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)

drivers/gpu/drm/i915/display/intel_pps.c

337

intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,

drivers/gpu/drm/i915/display/intel_pps.c

341

if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE) {

drivers/gpu/drm/i915/display/intel_pps.c

35

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

351

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

36

struct intel_pps *pps = &intel_dp->pps;

drivers/gpu/drm/i915/display/intel_pps.c

374

static bool intel_pps_is_valid(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

376

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

378

if (intel_dp->pps.pps_idx == 1 &&

drivers/gpu/drm/i915/display/intel_pps.c

400

pps_initial_setup(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

402

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

403

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_pps.c

404

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_pps.c

409

vlv_initial_power_sequencer_setup(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

415

intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;

drivers/gpu/drm/i915/display/intel_pps.c

417

intel_dp->pps.pps_idx = 0;

drivers/gpu/drm/i915/display/intel_pps.c

419

if (drm_WARN_ON(display->drm, intel_dp->pps.pps_idx >= intel_num_pps(display)))

drivers/gpu/drm/i915/display/intel_pps.c

420

intel_dp->pps.pps_idx = -1;

drivers/gpu/drm/i915/display/intel_pps.c

423

if (intel_dp->pps.pps_idx < 0)

drivers/gpu/drm/i915/display/intel_pps.c

424

intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_pp_on);

drivers/gpu/drm/i915/display/intel_pps.c

426

if (intel_dp->pps.pps_idx < 0)

drivers/gpu/drm/i915/display/intel_pps.c

427

intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_vdd_on);

drivers/gpu/drm/i915/display/intel_pps.c

429

if (intel_dp->pps.pps_idx < 0) {

drivers/gpu/drm/i915/display/intel_pps.c

430

intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_any);

drivers/gpu/drm/i915/display/intel_pps.c

435

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

440

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

443

return intel_pps_is_valid(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

464

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_pps.c

466

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_pps.c

469

intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;

drivers/gpu/drm/i915/display/intel_pps.c

483

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_pps.c

486

intel_dp->pps.bxt_pps_reset = true;

drivers/gpu/drm/i915/display/intel_pps.c

498

static void intel_pps_get_registers(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_pps.c

501

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

507

pps_idx = vlv_power_sequencer_pipe(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

509

pps_idx = bxt_power_sequencer_idx(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

511

pps_idx = intel_dp->pps.pps_idx;

drivers/gpu/drm/i915/display/intel_pps.c

527

_pp_ctrl_reg(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

531

intel_pps_get_registers(intel_dp, &regs);

drivers/gpu/drm/i915/display/intel_pps.c

537

_pp_stat_reg(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

541

intel_pps_get_registers(intel_dp, &regs);

drivers/gpu/drm/i915/display/intel_pps.c

546

static bool edp_have_panel_power(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

548

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

553

intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)

drivers/gpu/drm/i915/display/intel_pps.c

556

return (intel_de_read(display, _pp_stat_reg(intel_dp)) & PP_ON) != 0;

drivers/gpu/drm/i915/display/intel_pps.c

559

static bool edp_have_panel_vdd(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

561

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

566

intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)

drivers/gpu/drm/i915/display/intel_pps.c

569

return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;

drivers/gpu/drm/i915/display/intel_pps.c

572

void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

574

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

575

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

577

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

580

if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {

drivers/gpu/drm/i915/display/intel_pps.c

584

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

588

pps_name(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

589

intel_de_read(display, _pp_stat_reg(intel_dp)),

drivers/gpu/drm/i915/display/intel_pps.c

590

intel_de_read(display, _pp_ctrl_reg(intel_dp)));

drivers/gpu/drm/i915/display/intel_pps.c

603

static void intel_pps_verify_state(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

605

static void wait_panel_status(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_pps.c

608

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

609

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

616

intel_pps_verify_state(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

618

pp_stat_reg = _pp_stat_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

619

pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

624

pps_name(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

636

pps_name(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

645

static void wait_panel_on(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

647

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

648

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

653

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

654

wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);

drivers/gpu/drm/i915/display/intel_pps.c

657

static void wait_panel_off(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

659

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

660

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

665

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

666

wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);

drivers/gpu/drm/i915/display/intel_pps.c

669

static void wait_panel_power_cycle(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

671

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

672

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

679

panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time);

drivers/gpu/drm/i915/display/intel_pps.c

681

remaining = max(0, intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration);

drivers/gpu/drm/i915/display/intel_pps.c

686

pps_name(intel_dp), remaining);

drivers/gpu/drm/i915/display/intel_pps.c

69

struct ref_tracker *intel_pps_lock(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

693

wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);

drivers/gpu/drm/i915/display/intel_pps.c

696

void intel_pps_wait_power_cycle(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

698

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

701

with_intel_pps_lock(intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

702

wait_panel_power_cycle(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

705

static void wait_backlight_on(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

707

wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on,

drivers/gpu/drm/i915/display/intel_pps.c

708

intel_dp->pps.backlight_on_delay);

drivers/gpu/drm/i915/display/intel_pps.c

71

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

711

static void edp_wait_backlight_off(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

713

wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off,

drivers/gpu/drm/i915/display/intel_pps.c

714

intel_dp->pps.backlight_off_delay);

drivers/gpu/drm/i915/display/intel_pps.c

721

static u32 ilk_get_pp_control(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

723

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

728

control = intel_de_read(display, _pp_ctrl_reg(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

742

bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

744

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

745

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

748

bool need_to_disable = !intel_dp->pps.want_panel_vdd;

drivers/gpu/drm/i915/display/intel_pps.c

750

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

755

cancel_delayed_work(&intel_dp->pps.panel_vdd_work);

drivers/gpu/drm/i915/display/intel_pps.c

756

intel_dp->pps.want_panel_vdd = true;

drivers/gpu/drm/i915/display/intel_pps.c

758

if (edp_have_panel_vdd(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

761

drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);

drivers/gpu/drm/i915/display/intel_pps.c

762

intel_dp->pps.vdd_wakeref = intel_display_power_get(display,

drivers/gpu/drm/i915/display/intel_pps.c

765

pp_stat_reg = _pp_stat_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

766

pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

770

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

772

if (!edp_have_panel_power(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

773

wait_panel_power_cycle(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

775

pp = ilk_get_pp_control(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

783

pps_name(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

789

if (!edp_have_panel_power(intel_dp)) {

drivers/gpu/drm/i915/display/intel_pps.c

793

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

794

msleep(intel_dp->pps.panel_power_up_delay);

drivers/gpu/drm/i915/display/intel_pps.c

807

void intel_pps_vdd_on(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

809

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

812

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

816

with_intel_pps_lock(intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

817

vdd = intel_pps_vdd_on_unlocked(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

819

dp_to_dig_port(intel_dp)->base.base.base.id,

drivers/gpu/drm/i915/display/intel_pps.c

820

dp_to_dig_port(intel_dp)->base.base.name,

drivers/gpu/drm/i915/display/intel_pps.c

821

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

824

static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

826

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

827

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

83

struct ref_tracker *intel_pps_unlock(struct intel_dp *intel_dp, struct ref_tracker *wakeref)

drivers/gpu/drm/i915/display/intel_pps.c

833

drm_WARN_ON(display->drm, intel_dp->pps.want_panel_vdd);

drivers/gpu/drm/i915/display/intel_pps.c

835

if (!edp_have_panel_vdd(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

840

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

842

pp = ilk_get_pp_control(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

845

pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

846

pp_stat_reg = _pp_stat_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

85

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

855

pps_name(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

860

intel_dp->pps.panel_power_off_time = ktime_get_boottime();

drivers/gpu/drm/i915/display/intel_pps.c

861

intel_dp_invalidate_source_oui(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

866

fetch_and_zero(&intel_dp->pps.vdd_wakeref));

drivers/gpu/drm/i915/display/intel_pps.c

869

void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

871

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

874

cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work);

drivers/gpu/drm/i915/display/intel_pps.c

879

with_intel_pps_lock(intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

880

intel_pps_vdd_off_sync_unlocked(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

887

struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps);

drivers/gpu/drm/i915/display/intel_pps.c

889

with_intel_pps_lock(intel_dp) {

drivers/gpu/drm/i915/display/intel_pps.c

890

if (!intel_dp->pps.want_panel_vdd)

drivers/gpu/drm/i915/display/intel_pps.c

891

intel_pps_vdd_off_sync_unlocked(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

895

static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

897

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

904

if (intel_dp->pps.initializing)

drivers/gpu/drm/i915/display/intel_pps.c

912

delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5);

drivers/gpu/drm/i915/display/intel_pps.c

914

&intel_dp->pps.panel_vdd_work, delay);

drivers/gpu/drm/i915/display/intel_pps.c

922

void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)

drivers/gpu/drm/i915/display/intel_pps.c

924

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

926

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

931

INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd,

drivers/gpu/drm/i915/display/intel_pps.c

933

dp_to_dig_port(intel_dp)->base.base.base.id,

drivers/gpu/drm/i915/display/intel_pps.c

934

dp_to_dig_port(intel_dp)->base.base.name,

drivers/gpu/drm/i915/display/intel_pps.c

935

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

937

intel_dp->pps.want_panel_vdd = false;

drivers/gpu/drm/i915/display/intel_pps.c

94

vlv_power_sequencer_kick(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

940

intel_pps_vdd_off_sync_unlocked(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

942

edp_panel_vdd_schedule_off(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

945

void intel_pps_vdd_off(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

947

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

950

with_intel_pps_lock(intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

951

intel_pps_vdd_off_unlocked(intel_dp, false);

drivers/gpu/drm/i915/display/intel_pps.c

954

void intel_pps_on_unlocked(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

956

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

96

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

962

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

966

dp_to_dig_port(intel_dp)->base.base.base.id,

drivers/gpu/drm/i915/display/intel_pps.c

967

dp_to_dig_port(intel_dp)->base.base.name,

drivers/gpu/drm/i915/display/intel_pps.c

968

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

97

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

970

if (drm_WARN(display->drm, edp_have_panel_power(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

972

dp_to_dig_port(intel_dp)->base.base.base.id,

drivers/gpu/drm/i915/display/intel_pps.c

973

dp_to_dig_port(intel_dp)->base.base.name,

drivers/gpu/drm/i915/display/intel_pps.c

974

pps_name(intel_dp)))

drivers/gpu/drm/i915/display/intel_pps.c

977

wait_panel_power_cycle(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

979

pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

98

enum pipe pipe = intel_dp->pps.vlv_pps_pipe;

drivers/gpu/drm/i915/display/intel_pps.c

980

pp = ilk_get_pp_control(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

15

struct intel_dp;

drivers/gpu/drm/i915/display/intel_pps.h

19

struct ref_tracker *intel_pps_lock(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

20

struct ref_tracker *intel_pps_unlock(struct intel_dp *intel_dp, struct ref_tracker *wakeref);

drivers/gpu/drm/i915/display/intel_pps.h

28

void intel_pps_backlight_on(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

29

void intel_pps_backlight_off(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

32

bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

33

void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);

drivers/gpu/drm/i915/display/intel_pps.h

34

void intel_pps_on_unlocked(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

35

void intel_pps_off_unlocked(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

36

void intel_pps_check_power_unlocked(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

38

void intel_pps_vdd_on(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

39

void intel_pps_vdd_off(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

40

void intel_pps_on(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

41

void intel_pps_off(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

42

void intel_pps_vdd_off_sync(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

43

bool intel_pps_have_panel_power_or_vdd(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

44

void intel_pps_wait_power_cycle(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

46

bool intel_pps_init(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

47

void intel_pps_init_late(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

48

void intel_pps_encoder_reset(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

50

void vlv_pps_pipe_init(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

51

void vlv_pps_pipe_reset(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

52

enum pipe vlv_pps_backlight_initial_pipe(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1000

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1001

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_psr.c

1026

static int psr2_block_count(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

1028

return psr2_block_count_lines(intel_dp->psr.io_wake_lines,

drivers/gpu/drm/i915/display/intel_psr.c

1029

intel_dp->psr.fast_wake_lines) / 4;

drivers/gpu/drm/i915/display/intel_psr.c

1032

static u8 frames_before_su_entry(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

1034

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_psr.c

1042

if (intel_dp->psr.entry_setup_frames >= frames_before_su_entry)

drivers/gpu/drm/i915/display/intel_psr.c

1043

frames_before_su_entry = intel_dp->psr.entry_setup_frames + 1;

drivers/gpu/drm/i915/display/intel_psr.c

1048

static bool intel_psr_allow_pr_bw_optimization(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

1050

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

1053

if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

1056

if (!intel_dp_tunnel_pr_optimization_supported(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

1062

static void dg2_activate_panel_replay(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

1064

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1065

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

1066

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

1070

if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

1074

if (intel_dp->psr.req_psr2_sdp_prior_scanline)

drivers/gpu/drm/i915/display/intel_psr.c

1081

if (intel_psr_allow_pr_bw_optimization(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

1087

PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

1090

intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), dp2_ctl_clear, dp2_ctl_set);

drivers/gpu/drm/i915/display/intel_psr.c

1093

static void hsw_activate_psr2(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

1095

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1096

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

1104

is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)

drivers/gpu/drm/i915/display/intel_psr.c

1107

idle_frames = psr_compute_idle_frames(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1116

val |= EDP_PSR2_FRAME_BEFORE_SU(frames_before_su_entry(intel_dp));

drivers/gpu/drm/i915/display/intel_psr.c

1118

val |= intel_psr2_get_tp_time(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1121

if (psr2_block_count(intel_dp) > 2)

drivers/gpu/drm/i915/display/intel_psr.c

1145

tmp = map[intel_dp->psr.io_wake_lines -

drivers/gpu/drm/i915/display/intel_psr.c

1149

tmp = map[intel_dp->psr.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];

drivers/gpu/drm/i915/display/intel_psr.c

1152

val |= LNL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines);

drivers/gpu/drm/i915/display/intel_psr.c

1154

val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines);

drivers/gpu/drm/i915/display/intel_psr.c

1155

val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines);

drivers/gpu/drm/i915/display/intel_psr.c

1157

val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines);

drivers/gpu/drm/i915/display/intel_psr.c

1158

val |= EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines);

drivers/gpu/drm/i915/display/intel_psr.c

1161

if (intel_dp->psr.req_psr2_sdp_prior_scanline)

drivers/gpu/drm/i915/display/intel_psr.c

1165

psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames);

drivers/gpu/drm/i915/display/intel_psr.c

1167

if (intel_dp->psr.psr2_sel_fetch_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

1178

if (intel_dp->psr.su_region_et_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

1212

static void psr2_program_idle_frames(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1215

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1216

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

1223

static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

1225

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1227

psr2_program_idle_frames(intel_dp, 0);

drivers/gpu/drm/i915/display/intel_psr.c

1231

static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

1233

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1236

psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp));

drivers/gpu/drm/i915/display/intel_psr.c

1241

struct intel_dp *intel_dp =

drivers/gpu/drm/i915/display/intel_psr.c

1242

container_of(work, typeof(*intel_dp), psr.dc3co_work.work);

drivers/gpu/drm/i915/display/intel_psr.c

1244

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

1246

if (delayed_work_pending(&intel_dp->psr.dc3co_work))

drivers/gpu/drm/i915/display/intel_psr.c

1249

tgl_psr2_disable_dc3co(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1251

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

1254

static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

1256

if (!intel_dp->psr.dc3co_exitline)

drivers/gpu/drm/i915/display/intel_psr.c

1259

cancel_delayed_work(&intel_dp->psr.dc3co_work);

drivers/gpu/drm/i915/display/intel_psr.c

1261

tgl_psr2_disable_dc3co(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1265

dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1268

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1269

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1280

tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1283

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1305

if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_psr.c

1325

static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1328

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1331

intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {

drivers/gpu/drm/i915/display/intel_psr.c

1343

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_psr.c

1344

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1398

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_psr.c

1402

if (intel_dp->edp_dpcd[0] >= DP_EDP_15)

drivers/gpu/drm/i915/display/intel_psr.c

1423

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_psr.c

1424

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1438

if (DISPLAY_VER(display) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b)

drivers/gpu/drm/i915/display/intel_psr.c

1446

static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1450

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1542

static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1548

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1577

static bool alpm_config_valid(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1583

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1585

if (!intel_alpm_compute_params(intel_dp, crtc_state)) {

drivers/gpu/drm/i915/display/intel_psr.c

1591

if (!wake_lines_fit_into_vblank(intel_dp, crtc_state, aux_less,

drivers/gpu/drm/i915/display/intel_psr.c

1601

static bool intel_psr2_config_valid(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1605

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1685

if (!alpm_config_valid(intel_dp, crtc_state, false, false, true))

drivers/gpu/drm/i915/display/intel_psr.c

1697

tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

1706

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_psr.c

1707

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1710

!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&

drivers/gpu/drm/i915/display/intel_psr.c

1717

if (!sel_update_global_enabled(intel_dp)) {

drivers/gpu/drm/i915/display/intel_psr.c

1723

if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_psr.c

1771

static bool _psr_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1775

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1779

if (!CAN_PSR(intel_dp) || !display->params.enable_psr)

drivers/gpu/drm/i915/display/intel_psr.c

1788

entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, conn_state, adjusted_mode);

drivers/gpu/drm/i915/display/intel_psr.c

1819

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_psr.c

1820

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1823

if (!CAN_PANEL_REPLAY(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

1829

if (!panel_replay_global_enabled(intel_dp)) {

drivers/gpu/drm/i915/display/intel_psr.c

1851

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

1878

if (!alpm_config_valid(intel_dp, crtc_state, true, true, false))

drivers/gpu/drm/i915/display/intel_psr.c

1884

static bool intel_psr_needs_wa_18037818876(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1887

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1894

void intel_psr_set_non_psr_pipes(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1897

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1920

void intel_psr_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1924

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1928

if (!psr_global_enabled(intel_dp)) {

drivers/gpu/drm/i915/display/intel_psr.c

1933

if (intel_dp->psr.sink_not_reliable) {

drivers/gpu/drm/i915/display/intel_psr.c

1961

_psr_compute_config(intel_dp, crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_psr.c

1975

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_psr.c

1981

intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_psr.c

1982

if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp)))

drivers/gpu/drm/i915/display/intel_psr.c

1985

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

1986

if (!intel_dp->psr.enabled)

drivers/gpu/drm/i915/display/intel_psr.c

1989

if (intel_dp->psr.panel_replay_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

1999

pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled;

drivers/gpu/drm/i915/display/intel_psr.c

2002

if (!intel_dp->psr.sel_update_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2012

pipe_config->enable_psr2_su_region_et = intel_dp->psr.su_region_et_enabled;

drivers/gpu/drm/i915/display/intel_psr.c

2020

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

2023

static void intel_psr_activate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

2025

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2026

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

2035

drm_WARN_ON(display->drm, intel_dp->psr.active);

drivers/gpu/drm/i915/display/intel_psr.c

2037

drm_WARN_ON(display->drm, !intel_dp->psr.enabled);

drivers/gpu/drm/i915/display/intel_psr.c

2039

lockdep_assert_held(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

2042

if (intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2043

dg2_activate_panel_replay(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2044

else if (intel_dp->psr.sel_update_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2045

hsw_activate_psr2(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2047

hsw_activate_psr1(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2049

intel_dp->psr.active = true;

drivers/gpu/drm/i915/display/intel_psr.c

2050

intel_dp->psr.no_psr_reason = NULL;

drivers/gpu/drm/i915/display/intel_psr.c

2057

static void wm_optimization_wa(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

2060

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2061

enum pipe pipe = intel_dp->psr.pipe;

drivers/gpu/drm/i915/display/intel_psr.c

2082

static void intel_psr_enable_source(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

2085

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2086

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

2094

hsw_psr_setup_aux(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

210

#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \

drivers/gpu/drm/i915/display/intel_psr.c

211

(intel_dp)->psr.source_support)

drivers/gpu/drm/i915/display/intel_psr.c

2110

if (DISPLAY_VER(display) < 20 || intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

2113

if (intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_psr.c

2144

psr_irq_control(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2150

if (intel_dp->psr.dc3co_exitline)

drivers/gpu/drm/i915/display/intel_psr.c

2154

intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE);

drivers/gpu/drm/i915/display/intel_psr.c

2158

intel_dp->psr.psr2_sel_fetch_enabled ?

drivers/gpu/drm/i915/display/intel_psr.c

2165

wm_optimization_wa(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2167

if (intel_dp->psr.sel_update_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

2178

if (!intel_dp->psr.panel_replay_enabled &&

drivers/gpu/drm/i915/display/intel_psr.c

2185

if (!intel_dp->psr.panel_replay_enabled &&

drivers/gpu/drm/i915/display/intel_psr.c

2199

!intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2200

intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true);

drivers/gpu/drm/i915/display/intel_psr.c

2202

intel_alpm_configure(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2208

static bool psr_interrupt_error_check(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

2210

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2211

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

2214

if (intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2226

val &= psr_irq_psr_error_bit_get(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2228

intel_dp->psr.sink_not_reliable = true;

drivers/gpu/drm/i915/display/intel_psr.c

2238

static void intel_psr_enable_locked(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

2241

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2242

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2245

drm_WARN_ON(display->drm, intel_dp->psr.enabled);

drivers/gpu/drm/i915/display/intel_psr.c

2247

intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update;

drivers/gpu/drm/i915/display/intel_psr.c

2248

intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;

drivers/gpu/drm/i915/display/intel_psr.c

2249

intel_dp->psr.busy_frontbuffer_bits = 0;

drivers/gpu/drm/i915/display/intel_psr.c

2250

intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;

drivers/gpu/drm/i915/display/intel_psr.c

2251

intel_dp->psr.transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

2254

intel_dp->psr.dc3co_exit_delay = val;

drivers/gpu/drm/i915/display/intel_psr.c

2255

intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;

drivers/gpu/drm/i915/display/intel_psr.c

2256

intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;

drivers/gpu/drm/i915/display/intel_psr.c

2257

intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et;

drivers/gpu/drm/i915/display/intel_psr.c

2258

intel_dp->psr.psr2_sel_fetch_cff_enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

2259

intel_dp->psr.req_psr2_sdp_prior_scanline =

drivers/gpu/drm/i915/display/intel_psr.c

2261

intel_dp->psr.active_non_psr_pipes = crtc_state->active_non_psr_pipes;

drivers/gpu/drm/i915/display/intel_psr.c

2262

intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used;

drivers/gpu/drm/i915/display/intel_psr.c

2263

intel_dp->psr.io_wake_lines = crtc_state->alpm_state.io_wake_lines;

drivers/gpu/drm/i915/display/intel_psr.c

2264

intel_dp->psr.fast_wake_lines = crtc_state->alpm_state.fast_wake_lines;

drivers/gpu/drm/i915/display/intel_psr.c

2265

intel_dp->psr.entry_setup_frames = crtc_state->entry_setup_frames;

drivers/gpu/drm/i915/display/intel_psr.c

2267

if (!psr_interrupt_error_check(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

2270

if (intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2274

intel_dp->psr.sel_update_enabled ? "2" : "1");

drivers/gpu/drm/i915/display/intel_psr.c

2289

intel_psr_enable_sink(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2291

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

2294

intel_psr_enable_source(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2295

intel_dp->psr.enabled = true;

drivers/gpu/drm/i915/display/intel_psr.c

2296

intel_dp->psr.pause_counter = 0;

drivers/gpu/drm/i915/display/intel_psr.c

2305

intel_dp->psr.link_ok = true;

drivers/gpu/drm/i915/display/intel_psr.c

2307

intel_psr_activate(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2310

static void intel_psr_exit(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

2312

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2313

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

2316

if (!intel_dp->psr.active) {

drivers/gpu/drm/i915/display/intel_psr.c

2330

if (intel_dp->psr.panel_replay_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

2331

intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

2333

} else if (intel_dp->psr.sel_update_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

2334

tgl_disallow_dc3co_on_psr2_exit(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2344

intel_dp->psr.pkg_c_latency_used)

drivers/gpu/drm/i915/display/intel_psr.c

2346

intel_dp->psr.pipe,

drivers/gpu/drm/i915/display/intel_psr.c

2355

intel_dp->psr.active = false;

drivers/gpu/drm/i915/display/intel_psr.c

2358

static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

2360

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2361

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

2365

if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||

drivers/gpu/drm/i915/display/intel_psr.c

2366

intel_dp->psr.panel_replay_enabled)) {

drivers/gpu/drm/i915/display/intel_psr.c

2380

static void intel_psr_disable_locked(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

2382

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2383

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

2385

lockdep_assert_held(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

2387

if (!intel_dp->psr.enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2390

if (intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2394

intel_dp->psr.sel_update_enabled ? "2" : "1");

drivers/gpu/drm/i915/display/intel_psr.c

2396

intel_psr_exit(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2397

intel_psr_wait_exit_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2405

LATENCY_REPORTING_REMOVED(intel_dp->psr.pipe), 0);

drivers/gpu/drm/i915/display/intel_psr.c

2407

if (intel_dp->psr.sel_update_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

2409

if (!intel_dp->psr.panel_replay_enabled &&

drivers/gpu/drm/i915/display/intel_psr.c

241

static bool psr_global_enabled(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

2419

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

2420

intel_snps_phy_update_psr_power_state(&dp_to_dig_port(intel_dp)->base, false);

drivers/gpu/drm/i915/display/intel_psr.c

2422

if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

2423

intel_alpm_disable(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2426

if (!intel_dp->psr.panel_replay_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

2427

drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);

drivers/gpu/drm/i915/display/intel_psr.c

2429

if (intel_dp->psr.sel_update_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

243

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_psr.c

2430

drm_dp_dpcd_writeb(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_psr.c

2437

!intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2438

intel_dmc_block_pkgc(display, intel_dp->psr.pipe, false);

drivers/gpu/drm/i915/display/intel_psr.c

2440

intel_dp->psr.enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

2441

intel_dp->psr.panel_replay_enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

2442

intel_dp->psr.sel_update_enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

2443

intel_dp->psr.psr2_sel_fetch_enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

2444

intel_dp->psr.su_region_et_enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

2445

intel_dp->psr.psr2_sel_fetch_cff_enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

2446

intel_dp->psr.active_non_psr_pipes = 0;

drivers/gpu/drm/i915/display/intel_psr.c

2447

intel_dp->psr.pkg_c_latency_used = 0;

drivers/gpu/drm/i915/display/intel_psr.c

245

switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {

drivers/gpu/drm/i915/display/intel_psr.c

2457

void intel_psr_disable(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

2460

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2465

if (drm_WARN_ON(display->drm, !CAN_PSR(intel_dp) &&

drivers/gpu/drm/i915/display/intel_psr.c

2466

!CAN_PANEL_REPLAY(intel_dp)))

drivers/gpu/drm/i915/display/intel_psr.c

2469

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

247

return intel_dp_is_edp(intel_dp) ?

drivers/gpu/drm/i915/display/intel_psr.c

2471

intel_psr_disable_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2473

intel_dp->psr.link_ok = false;

drivers/gpu/drm/i915/display/intel_psr.c

2475

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

2476

cancel_work_sync(&intel_dp->psr.work);

drivers/gpu/drm/i915/display/intel_psr.c

2477

cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);

drivers/gpu/drm/i915/display/intel_psr.c

2486

void intel_psr_pause(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

2488

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

2490

if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

2500

if (intel_dp->psr.pause_counter++ == 0) {

drivers/gpu/drm/i915/display/intel_psr.c

2501

intel_psr_exit(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2502

intel_psr_wait_exit_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2517

void intel_psr_resume(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

2519

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2520

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

2522

if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

2535

if (--intel_dp->psr.pause_counter == 0)

drivers/gpu/drm/i915/display/intel_psr.c

2536

intel_psr_activate(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

256

static bool sel_update_global_enabled(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

2560

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_psr.c

2565

intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

2567

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

2570

if (CAN_PANEL_REPLAY(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

2575

CAN_PSR(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

258

switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {

drivers/gpu/drm/i915/display/intel_psr.c

2646

static void intel_psr_force_update(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

2648

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2663

intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0);

drivers/gpu/drm/i915/display/intel_psr.c

267

static bool panel_replay_global_enabled(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

2679

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

2682

lockdep_assert_held(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

2684

if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

269

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

271

return !(intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE) &&

drivers/gpu/drm/i915/display/intel_psr.c

275

static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

277

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

280

EDP_PSR_ERROR(intel_dp->psr.transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

283

static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

285

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

288

EDP_PSR_POST_EXIT(intel_dp->psr.transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

2899

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

2901

if (!intel_dp_is_edp(intel_dp) &&

drivers/gpu/drm/i915/display/intel_psr.c

2902

intel_dp->psr.panel_replay_enabled &&

drivers/gpu/drm/i915/display/intel_psr.c

2903

intel_dp->psr.sel_update_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

291

static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

293

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

296

EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

299

static u32 psr_irq_mask_get(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

301

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

304

EDP_PSR_MASK(intel_dp->psr.transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

3183

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

3184

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

3209

intel_psr_disable_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3212

wm_optimization_wa(intel_dp, new_crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

3248

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

3249

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

3272

intel_psr_enable_locked(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

3275

wm_optimization_wa(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

3279

intel_psr_force_update(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3285

intel_dp->psr.busy_frontbuffer_bits = 0;

drivers/gpu/drm/i915/display/intel_psr.c

3361

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

3364

lockdep_assert_held(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3366

if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3369

if (intel_dp->psr.sel_update_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3394

static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3396

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3397

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

3402

if (!intel_dp->psr.enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3405

if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||

drivers/gpu/drm/i915/display/intel_psr.c

3406

intel_dp->psr.panel_replay_enabled)) {

drivers/gpu/drm/i915/display/intel_psr.c

3414

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3422

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3423

return err == 0 && intel_dp->psr.enabled && !intel_dp->psr.pause_counter;

drivers/gpu/drm/i915/display/intel_psr.c

3489

int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val)

drivers/gpu/drm/i915/display/intel_psr.c

3491

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3506

ret = mutex_lock_interruptible(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3510

old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;

drivers/gpu/drm/i915/display/intel_psr.c

3511

old_disable_bits = intel_dp->psr.debug &

drivers/gpu/drm/i915/display/intel_psr.c

3515

intel_dp->psr.debug = val;

drivers/gpu/drm/i915/display/intel_psr.c

3521

if (intel_dp->psr.enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3522

psr_irq_control(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3524

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3532

static void intel_psr_handle_irq(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3534

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

3536

intel_psr_disable_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3539

drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);

drivers/gpu/drm/i915/display/intel_psr.c

3544

struct intel_dp *intel_dp =

drivers/gpu/drm/i915/display/intel_psr.c

3545

container_of(work, typeof(*intel_dp), psr.work);

drivers/gpu/drm/i915/display/intel_psr.c

3547

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3549

if (!intel_dp->psr.enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3552

if (READ_ONCE(intel_dp->psr.irq_aux_error)) {

drivers/gpu/drm/i915/display/intel_psr.c

3553

intel_psr_handle_irq(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3557

if (intel_dp->psr.pause_counter)

drivers/gpu/drm/i915/display/intel_psr.c

3566

if (!__psr_wait_for_idle_locked(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

3574

if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active)

drivers/gpu/drm/i915/display/intel_psr.c

3577

intel_psr_activate(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3579

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3582

static void intel_psr_configure_full_frame_update(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3584

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3585

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

3587

if (!intel_dp->psr.psr2_sel_fetch_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3602

static void _psr_invalidate_handle(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3604

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3606

if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3607

if (!intel_dp->psr.psr2_sel_fetch_cff_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3608

intel_dp->psr.psr2_sel_fetch_cff_enabled = true;

drivers/gpu/drm/i915/display/intel_psr.c

3609

intel_psr_configure_full_frame_update(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3612

intel_psr_force_update(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3614

intel_psr_exit(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3641

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

3643

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3644

if (!intel_dp->psr.enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3645

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3650

INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);

drivers/gpu/drm/i915/display/intel_psr.c

3651

intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits;

drivers/gpu/drm/i915/display/intel_psr.c

3654

_psr_invalidate_handle(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3656

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3666

tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,

drivers/gpu/drm/i915/display/intel_psr.c

3669

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3671

if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.sel_update_enabled ||

drivers/gpu/drm/i915/display/intel_psr.c

3672

!intel_dp->psr.active)

drivers/gpu/drm/i915/display/intel_psr.c

3680

INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))

drivers/gpu/drm/i915/display/intel_psr.c

3683

tgl_psr2_enable_dc3co(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3684

mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work,

drivers/gpu/drm/i915/display/intel_psr.c

3685

intel_dp->psr.dc3co_exit_delay);

drivers/gpu/drm/i915/display/intel_psr.c

3688

static void _psr_flush_handle(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3690

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3698

intel_psr_exit(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3699

} else if (intel_dp->psr.psr2_sel_fetch_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3701

if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3703

if (intel_dp->psr.busy_frontbuffer_bits == 0)

drivers/gpu/drm/i915/display/intel_psr.c

3704

intel_dp->psr.psr2_sel_fetch_cff_enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

3716

intel_psr_configure_full_frame_update(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3718

intel_psr_force_update(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3723

intel_psr_force_update(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3726

if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)

drivers/gpu/drm/i915/display/intel_psr.c

3727

queue_work(display->wq.unordered, &intel_dp->psr.work);

drivers/gpu/drm/i915/display/intel_psr.c

3750

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

3752

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3753

if (!intel_dp->psr.enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3754

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3759

INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);

drivers/gpu/drm/i915/display/intel_psr.c

3760

intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits;

drivers/gpu/drm/i915/display/intel_psr.c

3767

if (intel_dp->psr.pause_counter)

drivers/gpu/drm/i915/display/intel_psr.c

3772

!intel_dp->psr.psr2_sel_fetch_enabled)) {

drivers/gpu/drm/i915/display/intel_psr.c

3773

tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin);

drivers/gpu/drm/i915/display/intel_psr.c

3781

_psr_flush_handle(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3783

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

379

static void psr_irq_control(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3795

void intel_psr_init(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3797

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3798

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_psr.c

3799

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

381

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3819

if ((HAS_DP20(display) && !intel_dp_is_edp(intel_dp)) ||

drivers/gpu/drm/i915/display/intel_psr.c

382

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

3821

intel_dp->psr.source_panel_replay_support = true;

drivers/gpu/drm/i915/display/intel_psr.c

3823

if (HAS_PSR(display) && intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

3824

intel_dp->psr.source_support = true;

drivers/gpu/drm/i915/display/intel_psr.c

3829

intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;

drivers/gpu/drm/i915/display/intel_psr.c

3831

INIT_WORK(&intel_dp->psr.work, intel_psr_work);

drivers/gpu/drm/i915/display/intel_psr.c

3832

INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);

drivers/gpu/drm/i915/display/intel_psr.c

3833

mutex_init(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3836

static int psr_get_status_and_error_status(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

3839

struct drm_dp_aux *aux = &intel_dp->aux;

drivers/gpu/drm/i915/display/intel_psr.c

3843

offset = intel_dp->psr.panel_replay_enabled ?

drivers/gpu/drm/i915/display/intel_psr.c

385

if (intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3850

offset = intel_dp->psr.panel_replay_enabled ?

drivers/gpu/drm/i915/display/intel_psr.c

3862

static void psr_alpm_check(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3864

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

3869

if (intel_alpm_get_error(intel_dp)) {

drivers/gpu/drm/i915/display/intel_psr.c

3870

intel_psr_disable_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3875

static void psr_capability_changed_check(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3877

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3878

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

388

mask = psr_irq_psr_error_bit_get(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3882

r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val);

drivers/gpu/drm/i915/display/intel_psr.c

3889

intel_psr_disable_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

389

if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)

drivers/gpu/drm/i915/display/intel_psr.c

3895

drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val);

drivers/gpu/drm/i915/display/intel_psr.c

390

mask |= psr_irq_post_exit_bit_get(intel_dp) |

drivers/gpu/drm/i915/display/intel_psr.c

3906

void intel_psr_short_pulse(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3908

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3909

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

391

psr_irq_pre_entry_bit_get(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3915

if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

3925

if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) {

drivers/gpu/drm/i915/display/intel_psr.c

3933

intel_psr_disable_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

394

psr_irq_mask_get(intel_dp), ~mask);

drivers/gpu/drm/i915/display/intel_psr.c

3956

drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);

drivers/gpu/drm/i915/display/intel_psr.c

3959

psr_alpm_check(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3960

psr_capability_changed_check(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3967

bool intel_psr_enabled(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3971

if (!CAN_PSR(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

3974

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3975

ret = intel_dp->psr.enabled;

drivers/gpu/drm/i915/display/intel_psr.c

3976

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3993

bool intel_psr_link_ok(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3997

if ((!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) ||

drivers/gpu/drm/i915/display/intel_psr.c

3998

!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

4001

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4002

ret = intel_dp->psr.link_ok;

drivers/gpu/drm/i915/display/intel_psr.c

4003

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4026

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

4028

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4049

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

4051

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4057

static void intel_psr_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

4059

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

4062

if (!intel_dp->psr.active || !intel_dp->psr.pkg_c_latency_used)

drivers/gpu/drm/i915/display/intel_psr.c

4065

dc5_dc6_blocked = is_dc5_dc6_blocked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

4067

if (intel_dp->psr.sel_update_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

4068

psr2_program_idle_frames(intel_dp, dc5_dc6_blocked ? 0 :

drivers/gpu/drm/i915/display/intel_psr.c

4069

psr_compute_idle_frames(intel_dp));

drivers/gpu/drm/i915/display/intel_psr.c

4072

intel_dp->psr.pipe,

drivers/gpu/drm/i915/display/intel_psr.c

4083

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

4085

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4087

if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled &&

drivers/gpu/drm/i915/display/intel_psr.c

4088

!intel_dp->psr.pkg_c_latency_used)

drivers/gpu/drm/i915/display/intel_psr.c

4089

intel_psr_apply_underrun_on_idle_wa_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

4091

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4144

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

4147

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4149

if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

4152

active_non_psr_pipes = intel_dp->psr.active_non_psr_pipes;

drivers/gpu/drm/i915/display/intel_psr.c

4159

if (active_non_psr_pipes == intel_dp->psr.active_non_psr_pipes)

drivers/gpu/drm/i915/display/intel_psr.c

4162

if ((enable && intel_dp->psr.active_non_psr_pipes) ||

drivers/gpu/drm/i915/display/intel_psr.c

4163

(!enable && !intel_dp->psr.active_non_psr_pipes) ||

drivers/gpu/drm/i915/display/intel_psr.c

4164

!intel_dp->psr.pkg_c_latency_used) {

drivers/gpu/drm/i915/display/intel_psr.c

4165

intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes;

drivers/gpu/drm/i915/display/intel_psr.c

4169

intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes;

drivers/gpu/drm/i915/display/intel_psr.c

4171

intel_psr_apply_underrun_on_idle_wa_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

4173

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4191

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

4193

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4194

if (CAN_PANEL_REPLAY(intel_dp)) {

drivers/gpu/drm/i915/display/intel_psr.c

4196

intel_dp->psr.vblank_wakeref =

drivers/gpu/drm/i915/display/intel_psr.c

4201

intel_dp->psr.vblank_wakeref);

drivers/gpu/drm/i915/display/intel_psr.c

4204

if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled &&

drivers/gpu/drm/i915/display/intel_psr.c

4205

intel_dp->psr.pkg_c_latency_used)

drivers/gpu/drm/i915/display/intel_psr.c

4206

intel_psr_apply_underrun_on_idle_wa_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

4208

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4213

psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)

drivers/gpu/drm/i915/display/intel_psr.c

4215

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

4216

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

4220

if ((intel_dp_is_edp(intel_dp) || DISPLAY_VER(display) >= 30) &&

drivers/gpu/drm/i915/display/intel_psr.c

4221

(intel_dp->psr.sel_update_enabled || intel_dp->psr.panel_replay_enabled)) {

drivers/gpu/drm/i915/display/intel_psr.c

4282

static void intel_psr_print_mode(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

4285

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

4314

static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

4317

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

4318

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

4319

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

4332

intel_psr_print_mode(intel_dp, m);

drivers/gpu/drm/i915/display/intel_psr.c

4344

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

435

void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)

drivers/gpu/drm/i915/display/intel_psr.c

4360

if (psr->panel_replay_enabled && intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

4363

psr_source_status(intel_dp, m);

drivers/gpu/drm/i915/display/intel_psr.c

437

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

438

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

441

if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) {

drivers/gpu/drm/i915/display/intel_psr.c

442

intel_dp->psr.last_entry_attempt = time_ns;

drivers/gpu/drm/i915/display/intel_psr.c

4425

struct intel_dp *intel_dp = NULL;

drivers/gpu/drm/i915/display/intel_psr.c

4433

intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

4437

if (!intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

4440

return intel_psr_status(m, intel_dp, intel_dp->attached_connector);

drivers/gpu/drm/i915/display/intel_psr.c

4455

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

4461

ret = intel_psr_debug_set(intel_dp, val);

drivers/gpu/drm/i915/display/intel_psr.c

4477

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

448

if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) {

drivers/gpu/drm/i915/display/intel_psr.c

4480

*val = READ_ONCE(intel_dp->psr.debug);

drivers/gpu/drm/i915/display/intel_psr.c

449

intel_dp->psr.last_exit = time_ns;

drivers/gpu/drm/i915/display/intel_psr.c

4502

static const char *psr_mode_str(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

4504

if (intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

4506

else if (intel_dp->psr.enabled)

drivers/gpu/drm/i915/display/intel_psr.c

4515

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_psr.c

4530

if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) {

drivers/gpu/drm/i915/display/intel_psr.c

4538

ret = psr_get_status_and_error_status(intel_dp, &status, &error_status);

drivers/gpu/drm/i915/display/intel_psr.c

4548

seq_printf(m, "Sink %s status: 0x%x [%s]\n", psr_mode_str(intel_dp), status, str);

drivers/gpu/drm/i915/display/intel_psr.c

4550

seq_printf(m, "Sink %s error status: 0x%x", psr_mode_str(intel_dp), error_status);

drivers/gpu/drm/i915/display/intel_psr.c

4559

seq_printf(m, "\t%s RFB storage error\n", psr_mode_str(intel_dp));

drivers/gpu/drm/i915/display/intel_psr.c

4561

seq_printf(m, "\t%s VSC SDP uncorrectable error\n", psr_mode_str(intel_dp));

drivers/gpu/drm/i915/display/intel_psr.c

4563

seq_printf(m, "\t%s Link CRC error\n", psr_mode_str(intel_dp));

drivers/gpu/drm/i915/display/intel_psr.c

4572

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_psr.c

4574

return intel_psr_status(m, intel_dp, connector);

drivers/gpu/drm/i915/display/intel_psr.c

4595

bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

4601

return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update ||

drivers/gpu/drm/i915/display/intel_psr.c

4605

bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

4608

return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay;

drivers/gpu/drm/i915/display/intel_psr.c

461

psr_event_print(display, val, intel_dp->psr.sel_update_enabled);

drivers/gpu/drm/i915/display/intel_psr.c

4611

void intel_psr_compute_config_late(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

4614

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

4618

if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_psr.c

4620

else if (intel_psr_needs_alpm(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_psr.c

465

if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) {

drivers/gpu/drm/i915/display/intel_psr.c

4656

if (intel_psr_needs_wa_18037818876(intel_dp, crtc_state)) {

drivers/gpu/drm/i915/display/intel_psr.c

4662

intel_psr_set_non_psr_pipes(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

469

intel_dp->psr.irq_aux_error = true;

drivers/gpu/drm/i915/display/intel_psr.c

4699

bool intel_psr_pr_async_video_timing_supported(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

4701

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_psr.c

480

0, psr_irq_psr_error_bit_get(intel_dp));

drivers/gpu/drm/i915/display/intel_psr.c

482

queue_work(display->wq.unordered, &intel_dp->psr.work);

drivers/gpu/drm/i915/display/intel_psr.c

486

static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

488

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

491

if (drm_dp_dpcd_readb(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_psr.c

500

static void _psr_compute_su_granularity(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

503

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

519

r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, sizeof(w));

drivers/gpu/drm/i915/display/intel_psr.c

530

r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1);

drivers/gpu/drm/i915/display/intel_psr.c

606

static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)

drivers/gpu/drm/i915/display/intel_psr.c

608

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

612

if (intel_dp->mst_detect == DRM_DP_MST)

drivers/gpu/drm/i915/display/intel_psr.c

615

if (intel_dp_is_edp(intel_dp) &&

drivers/gpu/drm/i915/display/intel_psr.c

616

intel_has_dpcd_quirk(intel_dp, QUIRK_DISABLE_EDP_PANEL_REPLAY)) {

drivers/gpu/drm/i915/display/intel_psr.c

622

ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT,

drivers/gpu/drm/i915/display/intel_psr.c

632

if (intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_psr.c

633

if (!intel_alpm_aux_less_wake_supported(intel_dp)) {

drivers/gpu/drm/i915/display/intel_psr.c

648

intel_dp->psr.sink_panel_replay_support = true;

drivers/gpu/drm/i915/display/intel_psr.c

666

static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)

drivers/gpu/drm/i915/display/intel_psr.c

668

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

671

ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, connector->dp.psr_caps.dpcd,

drivers/gpu/drm/i915/display/intel_psr.c

682

if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {

drivers/gpu/drm/i915/display/intel_psr.c

688

if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {

drivers/gpu/drm/i915/display/intel_psr.c

695

intel_dp->psr.sink_support = true;

drivers/gpu/drm/i915/display/intel_psr.c

697

connector->dp.psr_caps.sync_latency = intel_dp_get_sink_sync_latency(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

719

intel_alpm_aux_wake_supported(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

725

ret = drm_dp_dpcd_read_byte(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_psr.c

730

_psr_compute_su_granularity(intel_dp, connector);

drivers/gpu/drm/i915/display/intel_psr.c

734

void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)

drivers/gpu/drm/i915/display/intel_psr.c

736

_psr_init_dpcd(intel_dp, connector);

drivers/gpu/drm/i915/display/intel_psr.c

738

_panel_replay_init_dpcd(intel_dp, connector);

drivers/gpu/drm/i915/display/intel_psr.c

741

static void hsw_psr_setup_aux(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

743

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

744

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

762

aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);

drivers/gpu/drm/i915/display/intel_psr.c

765

aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg),

drivers/gpu/drm/i915/display/intel_psr.c

780

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_psr.c

781

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

783

if (DISPLAY_VER(display) < 20 || !intel_dp_is_edp(intel_dp) ||

drivers/gpu/drm/i915/display/intel_psr.c

784

intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE)

drivers/gpu/drm/i915/display/intel_psr.c

793

static void _panel_replay_enable_sink(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

815

drm_dp_dpcd_write(&intel_dp->aux, PANEL_REPLAY_CONFIG,

drivers/gpu/drm/i915/display/intel_psr.c

819

drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG3, panel_replay_config_3);

drivers/gpu/drm/i915/display/intel_psr.c

822

static void _psr_enable_sink(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

825

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

831

if (intel_dp->psr.link_standby)

drivers/gpu/drm/i915/display/intel_psr.c

844

if (intel_dp->psr.entry_setup_frames > 0)

drivers/gpu/drm/i915/display/intel_psr.c

846

drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);

drivers/gpu/drm/i915/display/intel_psr.c

849

drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);

drivers/gpu/drm/i915/display/intel_psr.c

852

static void intel_psr_enable_sink(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

855

intel_alpm_enable_sink(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

858

_panel_replay_enable_sink(intel_dp, crtc_state) :

drivers/gpu/drm/i915/display/intel_psr.c

859

_psr_enable_sink(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

861

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

862

drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);

drivers/gpu/drm/i915/display/intel_psr.c

865

void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

872

if (CAN_PANEL_REPLAY(intel_dp) && panel_replay_global_enabled(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

873

drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,

drivers/gpu/drm/i915/display/intel_psr.c

877

static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

879

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

880

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_psr.c

921

drm_dp_tps3_supported(intel_dp->dpcd))

drivers/gpu/drm/i915/display/intel_psr.c

929

static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

931

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

932

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_psr.c

947

static bool is_dc5_dc6_blocked(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

949

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

951

struct intel_crtc *crtc = intel_crtc_for_pipe(display, intel_dp->psr.pipe);

drivers/gpu/drm/i915/display/intel_psr.c

956

intel_dp->psr.active_non_psr_pipes ||

drivers/gpu/drm/i915/display/intel_psr.c

960

static void hsw_activate_psr1(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

962

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

963

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

967

val |= EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));

drivers/gpu/drm/i915/display/intel_psr.c

975

if (intel_dp->psr.link_standby)

drivers/gpu/drm/i915/display/intel_psr.c

978

val |= intel_psr1_get_tp_time(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

984

val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames);

drivers/gpu/drm/i915/display/intel_psr.c

992

is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)

drivers/gpu/drm/i915/display/intel_psr.c

994

intel_dp->psr.pipe,

drivers/gpu/drm/i915/display/intel_psr.c

998

static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.h

19

struct intel_dp;

drivers/gpu/drm/i915/display/intel_psr.h

25

#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \

drivers/gpu/drm/i915/display/intel_psr.h

26

(intel_dp)->psr.source_panel_replay_support)

drivers/gpu/drm/i915/display/intel_psr.h

31

void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector);

drivers/gpu/drm/i915/display/intel_psr.h

32

void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_psr.h

37

void intel_psr_disable(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.h

39

int intel_psr_debug_set(struct intel_dp *intel_dp, u64 value);

drivers/gpu/drm/i915/display/intel_psr.h

46

void intel_psr_init(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_psr.h

47

void intel_psr_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.h

52

void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);

drivers/gpu/drm/i915/display/intel_psr.h

53

void intel_psr_short_pulse(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_psr.h

57

bool intel_psr_enabled(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_psr.h

63

void intel_psr_pause(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_psr.h

64

void intel_psr_resume(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_psr.h

72

bool intel_psr_link_ok(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_psr.h

82

bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_psr.h

83

bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.h

85

void intel_psr_compute_config_late(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.h

89

bool intel_psr_pr_async_video_timing_supported(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_quirks.c

116

void (*hook)(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_quirks.c

19

static void intel_set_dpcd_quirk(struct intel_dp *intel_dp, enum intel_quirk_id quirk)

drivers/gpu/drm/i915/display/intel_quirks.c

21

intel_dp->quirks.mask |= BIT(quirk);

drivers/gpu/drm/i915/display/intel_quirks.c

313

void intel_init_dpcd_quirks(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_quirks.c

316

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_quirks.c

333

q->hook(intel_dp);

drivers/gpu/drm/i915/display/intel_quirks.c

342

bool intel_has_dpcd_quirk(struct intel_dp *intel_dp, enum intel_quirk_id quirk)

drivers/gpu/drm/i915/display/intel_quirks.c

344

return intel_dp->quirks.mask & BIT(quirk);

drivers/gpu/drm/i915/display/intel_quirks.c

75

static void quirk_fw_sync_len(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_quirks.c

77

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_quirks.c

79

intel_set_dpcd_quirk(intel_dp, QUIRK_FW_SYNC_LEN);

drivers/gpu/drm/i915/display/intel_quirks.c

89

static void quirk_disable_edp_panel_replay(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_quirks.c

91

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_quirks.c

93

intel_set_dpcd_quirk(intel_dp, QUIRK_DISABLE_EDP_PANEL_REPLAY);

drivers/gpu/drm/i915/display/intel_quirks.h

12

struct intel_dp;

drivers/gpu/drm/i915/display/intel_quirks.h

29

void intel_init_dpcd_quirks(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_quirks.h

32

bool intel_has_dpcd_quirk(struct intel_dp *intel_dp, enum intel_quirk_id quirk);

drivers/gpu/drm/i915/display/intel_tc.c

1766

struct intel_dp *intel_dp = enc_to_intel_dp(&dig_port->base);

drivers/gpu/drm/i915/display/intel_tc.c

1775

ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);

drivers/gpu/drm/i915/display/intel_vrr.c

38

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_vrr.c

425

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_vrr.c

426

bool is_edp = intel_dp_is_edp(intel_dp);

drivers/gpu/drm/i915/display/intel_vrr.c

57

intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_vrr.c

66

if (drm_dp_is_branch(intel_dp->dpcd))

drivers/gpu/drm/i915/display/intel_vrr.c

69

if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd))