intr_type
enum ps3_interrupt_type *intr_type, unsigned int *interrupt_id);
enum ps3_interrupt_type intr_type, unsigned int *interrupt_id);
enum ps3_interrupt_type intr_type;
repo->dev_index, res_index, &intr_type, &interrupt_id);
intr_type, interrupt_id);
enum ps3_interrupt_type *intr_type, unsigned int *interrupt_id)
*intr_type = v1;
enum ps3_interrupt_type intr_type, unsigned int *interrupt_id)
pr_devel("%s:%d: find intr_type %u\n", __func__, __LINE__, intr_type);
if (t == intr_type) {
__func__, __LINE__, intr_type, res_index);
u32 intr_type = intr_info & INTR_INFO_INTR_TYPE_MASK;
if (CC(intr_type == INTR_TYPE_RESERVED) ||
CC(intr_type == INTR_TYPE_OTHER_EVENT &&
if (CC(intr_type == INTR_TYPE_NMI_INTR && vector != NMI_VECTOR) ||
CC(intr_type == INTR_TYPE_HARD_EXCEPTION && vector > 31) ||
CC(intr_type == INTR_TYPE_OTHER_EVENT && vector != 0))
if (!prot_mode || intr_type != INTR_TYPE_HARD_EXCEPTION) {
switch (intr_type) {
#define HL_USR_INTR_STRUCT_INIT(usr_intr, hdev, intr_id, intr_type) \
usr_intr.type = intr_type; \
u32 intr_type, engine_id;
intr_type = le32_to_cpu(data->intr_type);
switch (intr_type) {
GAUDI2_ENG_ID_TO_STR(engine_id), intr_type, q->queue_index);
u32 irq_type = ctrl->intr_type[line];
ctrl->intr_type[line] = type;
u8 intr_type[REALTEK_GPIO_MAX];
enum nvkm_intr_type intr_type = NVKM_INTR_SUBDEV;
intr = gr->func->oneinit_intr(gr, &intr_type);
ret = nvkm_inth_add(intr, intr_type, NVKM_INTR_PRIO_NORMAL, &gr->base.engine.subdev,
if (!mbox->intr_type)
reg = MAILBOX_IRQENABLE(mdev->intr_type, usr);
reg = MAILBOX_IRQENABLE(mdev->intr_type, usr);
u32 intr_type, info_count;
intr_type = mdev->mbox_data->intr_type;
fifo->irqenable = MAILBOX_IRQENABLE(intr_type, tx_usr);
fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, tx_usr);
fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, tx_usr);
fifo->irqenable = MAILBOX_IRQENABLE(intr_type, rx_usr);
fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, rx_usr);
fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, rx_usr);
mbox->intr_type = intr_type;
mdev->intr_type = intr_type;
u32 intr_type;
u32 intr_type;
u32 intr_type;
u32 intr_type;
if ((ib->intr_type == BNA_INTR_T_INTX)) { \
if (ib->intr_type == BNA_INTR_T_INTX) { \
cfg_req->ib_cfg.msix = (rxp->cq.ib.intr_type == BNA_INTR_T_MSIX)
res_info[BNA_RX_RES_T_INTR].res_u.intr_info.intr_type = BNA_INTR_T_MSIX;
rxp->cq.ib.intr_type = intr_info->intr_type;
if (intr_info->intr_type == BNA_INTR_T_MSIX)
rxp->cq.ccb->intr_type = rxp->cq.ib.intr_type;
cfg_req->ib_cfg.msix = (txq->ib.intr_type == BNA_INTR_T_MSIX)
res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.intr_type =
txq->ib.intr_type = intr_info->intr_type;
if (intr_info->intr_type == BNA_INTR_T_INTX)
txq->tcb->intr_type = txq->ib.intr_type;
enum bna_intr_type intr_type;
enum bna_intr_type intr_type;
enum bna_intr_type intr_type;
enum bna_intr_type intr_type;
intr_info->intr_type = BNA_INTR_T_MSIX;
intr_info->intr_type = BNA_INTR_T_INTX;
if (tx_info->tcb[0]->intr_type == BNA_INTR_T_MSIX)
if (intr_info->intr_type == BNA_INTR_T_MSIX) {
if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX)
if (intr_info->intr_type == BNA_INTR_T_MSIX) {
enum fman_intr_type intr_type)
if (intr_type == FMAN_INTR_TYPE_ERR)
if (intr_type == FMAN_INTR_TYPE_ERR)
u8 mod_id, enum fman_intr_type intr_type,
event = get_module_event(module, mod_id, intr_type);
u8 mod_id, enum fman_intr_type intr_type)
event = get_module_event(module, mod_id, intr_type);
u8 mod_id, enum fman_intr_type intr_type,
u8 mod_id, enum fman_intr_type intr_type);
if (!HINIC_IS_VF(hwdev->hwif) && dev_cap->intr_type != INTR_MSIX_TYPE)
u8 intr_type;
enum dpmaif_hw_intr_type intr_type, unsigned int intr_queue)
para->intr_types[para->intr_cnt] = intr_type;
octep_hp_cmd_name(hp_cmd->intr_type),
switch (hp_cmd->intr_type) {
hp_cmd->intr_type = type;
enum octep_hp_intr_type intr_type;
enum intr_type_t intr_type;
(phba->intr_type != MSIX))
phba->intr_type = MSIX;
if (cfg_mode >= 1 && phba->intr_type == NONE) {
phba->intr_type = MSI;
if (phba->intr_type == NONE) {
phba->intr_type = INTx;
if (phba->intr_type == MSIX)
phba->intr_type = NONE;
phba->intr_type = MSIX;
if (cfg_mode >= 1 && phba->intr_type == NONE) {
phba->intr_type = MSI;
if (phba->intr_type == NONE) {
phba->intr_type = INTx;
if (phba->intr_type == MSIX) {
phba->intr_type = NONE;
if (phba->intr_type != MSIX) {
if (phba->intr_type == MSIX) {
if (phba->intr_type == MSIX) {
if (phba->intr_type == MSIX) {
if (phba->intr_type == MSIX)
if (phba->intr_type == MSIX)
if ((q->phba->intr_type == INTx) && (arm == LPFC_QUEUE_REARM))
if ((q->phba->intr_type == INTx) && (arm == LPFC_QUEUE_REARM))
phba->intr_type != MSIX)
if (!phba->nvmet_support && phba->intr_type == MSIX)
intel_soc_dts_iosf_init(enum intel_soc_dts_interrupt_type intr_type,
sensors->intr_type = intr_type;
if (sensors->intr_type == INTEL_SOC_DTS_INTERRUPT_MSI)
enum intel_soc_dts_interrupt_type intr_type;
intel_soc_dts_iosf_init(enum intel_soc_dts_interrupt_type intr_type,
int intr_type;
intr_type = usb_endpoint_interrupt_type(desc);
if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
__le32 intr_type; /* enum hl_engine_arc_interrupt_type */