intr_reg
u32 intr_reg;
intr_reg = i2x.mb_head_ptr_reg + 4;
intr_reg, ret);
txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
int intr_reg = qid < RX_DONE_HIGH_OFFSET ? QDMA_INT_REG_IDX1
airoha_qdma_irq_enable(&qdma->irq_banks[i], intr_reg,
static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg,
intr_reg->intr_control = 0;
intr_reg->intr_control |= rx_delay_interval &
intr_reg->intr_control |=
intr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;
struct ena_eth_io_intr_reg *intr_reg)
writel(intr_reg->intr_control, io_cq->unmask_reg);
struct ena_eth_io_intr_reg intr_reg;
ena_com_update_intr_reg(&intr_reg,
ena_com_unmask_intr(tx_ring->ena_com_io_cq, &intr_reg);
struct idpf_intr_reg *intr = &adapter->mb_vector.intr_reg;
struct idpf_intr_reg *intr = &q_vector->intr_reg;
struct idpf_intr_reg *intr = &adapter->mb_vector.intr_reg;
writel(0, q_vector->intr_reg.dyn_ctl);
writel(0, q_vector[q_idx].intr_reg.dyn_ctl);
u32 itr_val = q_vector->intr_reg.dyn_ctl_intena_m;
itr_val |= q_vector->intr_reg.dyn_ctl_swint_trig_m |
q_vector->intr_reg.dyn_ctl_sw_itridx_ena_m;
itr_val |= (type << q_vector->intr_reg.dyn_ctl_itridx_s) |
(itr << (q_vector->intr_reg.dyn_ctl_intrvl_s - 1));
writel(intval, q_vector->intr_reg.dyn_ctl);
struct idpf_intr_reg *intr_reg;
intr_reg = &q_vector->intr_reg;
tx ? intr_reg->tx_itr : intr_reg->rx_itr);
reg = &q_vector->intr_reg;
struct idpf_intr_reg intr_reg;
struct idpf_intr_reg *intr = &adapter->mb_vector.intr_reg;
struct idpf_intr_reg *intr = &q_vector->intr_reg;
u8 intr_reg;
ret = ccg_read(uc, CCGX_RAB_INTR_REG, &intr_reg, sizeof(intr_reg));
if (!intr_reg)
else if (!(intr_reg & UCSI_READ_INT))
ccg_write(uc, CCGX_RAB_INTR_REG, &intr_reg, sizeof(intr_reg));