drivers/gpu/drm/gma500/cdv_intel_dp.c

1005

intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1007

lane_count = intel_dp->lane_count;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1010

lane_count = intel_dp->lane_count;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1041

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1044

intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1045

intel_dp->DP |= intel_dp->color_range;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1048

intel_dp->DP |= DP_SYNC_HS_HIGH;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1050

intel_dp->DP |= DP_SYNC_VS_HIGH;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1052

intel_dp->DP |= DP_LINK_TRAIN_OFF;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1054

switch (intel_dp->lane_count) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1056

intel_dp->DP |= DP_PORT_WIDTH_1;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1059

intel_dp->DP |= DP_PORT_WIDTH_2;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1062

intel_dp->DP |= DP_PORT_WIDTH_4;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1065

if (intel_dp->has_audio)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1066

intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1068

memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1069

intel_dp->link_configuration[0] = intel_dp->link_bw;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1070

intel_dp->link_configuration[1] = intel_dp->lane_count;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1075

if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&

drivers/gpu/drm/gma500/cdv_intel_dp.c

1076

(intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1077

intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1078

intel_dp->DP |= DP_ENHANCED_FRAMING;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1083

intel_dp->DP |= DP_PIPEB_SELECT;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1085

REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN));

drivers/gpu/drm/gma500/cdv_intel_dp.c

1086

DRM_DEBUG_KMS("DP expected reg is %x\n", intel_dp->DP);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1107

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1111

if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1169

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1171

uint32_t dp_reg = REG_READ(intel_dp->output_reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1230

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1233

intel_dp->link_status,

drivers/gpu/drm/gma500/cdv_intel_dp.c

1275

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1280

for (lane = 0; lane < intel_dp->lane_count; lane++) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1281

uint8_t this_v = cdv_intel_get_adjust_request_voltage(intel_dp->link_status, lane);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1282

uint8_t this_p = cdv_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1297

intel_dp->train_set[lane] = v | p;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1334

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1339

lane_align = cdv_intel_dp_link_status(intel_dp->link_status,

drivers/gpu/drm/gma500/cdv_intel_dp.c

1343

for (lane = 0; lane < intel_dp->lane_count; lane++) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1344

lane_status = cdv_intel_get_lane_status(intel_dp->link_status, lane);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1358

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1360

REG_WRITE(intel_dp->output_reg, dp_reg_value);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1361

REG_READ(intel_dp->output_reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1382

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1386

intel_dp->train_set,

drivers/gpu/drm/gma500/cdv_intel_dp.c

1387

intel_dp->lane_count);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1389

if (ret != intel_dp->lane_count) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1391

intel_dp->train_set[0], intel_dp->lane_count);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1401

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1405

if (intel_dp->output_reg == DP_B)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1467

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1473

uint32_t DP = intel_dp->DP;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1481

REG_WRITE(intel_dp->output_reg, reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1482

REG_READ(intel_dp->output_reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1488

intel_dp->link_configuration,

drivers/gpu/drm/gma500/cdv_intel_dp.c

1491

memset(intel_dp->train_set, 0, 4);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1502

intel_dp->train_set[0],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1503

intel_dp->link_configuration[0],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1504

intel_dp->link_configuration[1]);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1509

cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1519

intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1520

intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1522

if (cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1529

for (i = 0; i < intel_dp->lane_count; i++)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1530

if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1532

if (i == intel_dp->lane_count)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1536

if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1542

voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1550

DRM_DEBUG_KMS("failure in DP pattern 1 training, train set %x\n", intel_dp->train_set[0]);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1553

intel_dp->DP = DP;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1560

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1563

uint32_t DP = intel_dp->DP;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1575

intel_dp->train_set[0],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1576

intel_dp->link_configuration[0],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1577

intel_dp->link_configuration[1]);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1592

cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1601

intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1602

intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1605

if (!cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1633

REG_WRITE(intel_dp->output_reg, reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1634

REG_READ(intel_dp->output_reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1643

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1644

uint32_t DP = intel_dp->DP;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1646

if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1654

REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1656

REG_READ(intel_dp->output_reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1660

REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1661

REG_READ(intel_dp->output_reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1666

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1670

if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd,

drivers/gpu/drm/gma500/cdv_intel_dp.c

1671

sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))

drivers/gpu/drm/gma500/cdv_intel_dp.c

1673

if (intel_dp->dpcd[DP_DPCD_REV] != 0)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1678

intel_dp->dpcd[0], intel_dp->dpcd[1],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1679

intel_dp->dpcd[2], intel_dp->dpcd[3]);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1693

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1698

intel_dp->has_audio = false;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1709

if (intel_dp->force_audio) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1710

intel_dp->has_audio = intel_dp->force_audio > 0;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1712

edid = drm_get_edid(connector, &intel_dp->adapter);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1714

intel_dp->has_audio = drm_detect_monitor_audio(edid);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1727

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1733

edid = drm_get_edid(connector, &intel_dp->adapter);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1746

if (edp && !intel_dp->panel_fixed_mode) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1751

intel_dp->panel_fixed_mode =

drivers/gpu/drm/gma500/cdv_intel_dp.c

1760

if (!intel_dp->panel_fixed_mode && dev_priv->lfp_lvds_vbt_mode) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1761

intel_dp->panel_fixed_mode =

drivers/gpu/drm/gma500/cdv_intel_dp.c

1763

if (intel_dp->panel_fixed_mode) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1764

intel_dp->panel_fixed_mode->type |=

drivers/gpu/drm/gma500/cdv_intel_dp.c

1768

if (intel_dp->panel_fixed_mode != NULL) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

1770

mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1783

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1791

edid = drm_get_edid(connector, &intel_dp->adapter);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1809

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1820

if (i == intel_dp->force_audio)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1823

intel_dp->force_audio = i;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1830

if (has_audio == intel_dp->has_audio)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1833

intel_dp->has_audio = has_audio;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1838

if (val == !!intel_dp->color_range)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1841

intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1863

struct cdv_intel_dp *intel_dp = gma_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1867

kfree(intel_dp->panel_fixed_mode);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1868

intel_dp->panel_fixed_mode = NULL;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1870

i2c_del_adapter(&intel_dp->adapter);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1952

struct cdv_intel_dp *intel_dp;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1962

intel_dp = kzalloc_obj(struct cdv_intel_dp);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1963

if (!intel_dp)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1983

gma_encoder->dev_priv=intel_dp;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1984

intel_dp->encoder = gma_encoder;

drivers/gpu/drm/gma500/cdv_intel_dp.c

1985

intel_dp->output_reg = output_reg;

drivers/gpu/drm/gma500/cdv_intel_dp.c

2052

intel_dp->panel_power_up_delay = cur.t1_t3 / 10;

drivers/gpu/drm/gma500/cdv_intel_dp.c

2053

intel_dp->backlight_on_delay = cur.t8 / 10;

drivers/gpu/drm/gma500/cdv_intel_dp.c

2054

intel_dp->backlight_off_delay = cur.t9 / 10;

drivers/gpu/drm/gma500/cdv_intel_dp.c

2055

intel_dp->panel_power_down_delay = cur.t10 / 10;

drivers/gpu/drm/gma500/cdv_intel_dp.c

2056

intel_dp->panel_power_cycle_delay = (cur.t11_t12 - 1) * 100;

drivers/gpu/drm/gma500/cdv_intel_dp.c

2059

intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,

drivers/gpu/drm/gma500/cdv_intel_dp.c

2060

intel_dp->panel_power_cycle_delay);

drivers/gpu/drm/gma500/cdv_intel_dp.c

2063

intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);

drivers/gpu/drm/gma500/cdv_intel_dp.c

2068

intel_dp->dpcd,

drivers/gpu/drm/gma500/cdv_intel_dp.c

2069

sizeof(intel_dp->dpcd));

drivers/gpu/drm/gma500/cdv_intel_dp.c

2079

intel_dp->dpcd[0], intel_dp->dpcd[1],

drivers/gpu/drm/gma500/cdv_intel_dp.c

2080

intel_dp->dpcd[2], intel_dp->dpcd[3]);

drivers/gpu/drm/gma500/cdv_intel_dp.c

324

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

327

if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

328

max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;

drivers/gpu/drm/gma500/cdv_intel_dp.c

342

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

343

int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];

drivers/gpu/drm/gma500/cdv_intel_dp.c

380

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

383

if (intel_dp->panel_on) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

394

msleep(intel_dp->panel_power_up_delay);

drivers/gpu/drm/gma500/cdv_intel_dp.c

415

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

418

if (intel_dp->panel_on)

drivers/gpu/drm/gma500/cdv_intel_dp.c

431

intel_dp->panel_on = false;

drivers/gpu/drm/gma500/cdv_intel_dp.c

433

intel_dp->panel_on = true;

drivers/gpu/drm/gma500/cdv_intel_dp.c

434

msleep(intel_dp->panel_power_up_delay);

drivers/gpu/drm/gma500/cdv_intel_dp.c

443

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

452

intel_dp->panel_on = false;

drivers/gpu/drm/gma500/cdv_intel_dp.c

467

msleep(intel_dp->panel_power_cycle_delay);

drivers/gpu/drm/gma500/cdv_intel_dp.c

494

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

504

msleep(intel_dp->backlight_off_delay);

drivers/gpu/drm/gma500/cdv_intel_dp.c

512

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

517

if (is_edp(encoder) && intel_dp->panel_fixed_mode) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

518

if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)

drivers/gpu/drm/gma500/cdv_intel_dp.c

520

if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)

drivers/gpu/drm/gma500/cdv_intel_dp.c

571

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

572

uint32_t output_reg = intel_dp->output_reg;

drivers/gpu/drm/gma500/cdv_intel_dp.c

752

struct cdv_intel_dp *intel_dp = container_of(adapter,

drivers/gpu/drm/gma500/cdv_intel_dp.c

755

struct gma_encoder *encoder = intel_dp->encoder;

drivers/gpu/drm/gma500/cdv_intel_dp.c

848

struct cdv_intel_dp *intel_dp = encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

853

intel_dp->algo.running = false;

drivers/gpu/drm/gma500/cdv_intel_dp.c

854

intel_dp->algo.address = 0;

drivers/gpu/drm/gma500/cdv_intel_dp.c

855

intel_dp->algo.aux_ch = cdv_intel_dp_i2c_aux_ch;

drivers/gpu/drm/gma500/cdv_intel_dp.c

857

memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));

drivers/gpu/drm/gma500/cdv_intel_dp.c

858

intel_dp->adapter.owner = THIS_MODULE;

drivers/gpu/drm/gma500/cdv_intel_dp.c

859

strscpy(intel_dp->adapter.name, name);

drivers/gpu/drm/gma500/cdv_intel_dp.c

860

intel_dp->adapter.algo_data = &intel_dp->algo;

drivers/gpu/drm/gma500/cdv_intel_dp.c

861

intel_dp->adapter.dev.parent = connector->base.kdev;

drivers/gpu/drm/gma500/cdv_intel_dp.c

865

ret = i2c_dp_aux_add_bus(&intel_dp->adapter);

drivers/gpu/drm/gma500/cdv_intel_dp.c

896

struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;

drivers/gpu/drm/gma500/cdv_intel_dp.c

904

if (is_edp(intel_encoder) && intel_dp->panel_fixed_mode) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

905

cdv_intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);

drivers/gpu/drm/gma500/cdv_intel_dp.c

906

refclock = intel_dp->panel_fixed_mode->clock;

drivers/gpu/drm/gma500/cdv_intel_dp.c

915

intel_dp->link_bw = bws[clock];

drivers/gpu/drm/gma500/cdv_intel_dp.c

916

intel_dp->lane_count = lane_count;

drivers/gpu/drm/gma500/cdv_intel_dp.c

917

adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);

drivers/gpu/drm/gma500/cdv_intel_dp.c

920

intel_dp->link_bw, intel_dp->lane_count,

drivers/gpu/drm/gma500/cdv_intel_dp.c

928

intel_dp->lane_count = max_lane_count;

drivers/gpu/drm/gma500/cdv_intel_dp.c

929

intel_dp->link_bw = bws[max_clock];

drivers/gpu/drm/gma500/cdv_intel_dp.c

930

adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);

drivers/gpu/drm/gma500/cdv_intel_dp.c

933

intel_dp->link_bw, intel_dp->lane_count,

drivers/gpu/drm/gma500/cdv_intel_dp.c

999

struct cdv_intel_dp *intel_dp;

drivers/gpu/drm/i915/display/g4x_dp.c

102

intel_dp_set_link_params(intel_dp,

drivers/gpu/drm/i915/display/g4x_dp.c

1035

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

1036

u8 train_set = intel_dp->train_set[0];

drivers/gpu/drm/i915/display/g4x_dp.c

1044

intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);

drivers/gpu/drm/i915/display/g4x_dp.c

1045

intel_dp->DP |= signal_levels;

drivers/gpu/drm/i915/display/g4x_dp.c

1047

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

1048

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

1083

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

1084

u8 train_set = intel_dp->train_set[0];

drivers/gpu/drm/i915/display/g4x_dp.c

1092

intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;

drivers/gpu/drm/i915/display/g4x_dp.c

1093

intel_dp->DP |= signal_levels;

drivers/gpu/drm/i915/display/g4x_dp.c

1095

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

1096

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

1135

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

1136

u8 train_set = intel_dp->train_set[0];

drivers/gpu/drm/i915/display/g4x_dp.c

1144

intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;

drivers/gpu/drm/i915/display/g4x_dp.c

1145

intel_dp->DP |= signal_levels;

drivers/gpu/drm/i915/display/g4x_dp.c

1147

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

1148

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

1167

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

1170

if (intel_dp_test_phy(intel_dp))

drivers/gpu/drm/i915/display/g4x_dp.c

1175

intel_dp_check_link_state(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

125

intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;

drivers/gpu/drm/i915/display/g4x_dp.c

1265

struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));

drivers/gpu/drm/i915/display/g4x_dp.c

1267

intel_dp->DP = intel_de_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

1269

intel_dp->reset_link_params = true;

drivers/gpu/drm/i915/display/g4x_dp.c

1270

intel_dp_invalidate_source_oui(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

1273

vlv_pps_pipe_reset(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

1275

intel_pps_encoder_reset(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

128

intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;

drivers/gpu/drm/i915/display/g4x_dp.c

129

intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);

drivers/gpu/drm/i915/display/g4x_dp.c

135

intel_dp->DP |= DP_SYNC_HS_HIGH;

drivers/gpu/drm/i915/display/g4x_dp.c

137

intel_dp->DP |= DP_SYNC_VS_HIGH;

drivers/gpu/drm/i915/display/g4x_dp.c

138

intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

drivers/gpu/drm/i915/display/g4x_dp.c

141

intel_dp->DP |= DP_ENHANCED_FRAMING;

drivers/gpu/drm/i915/display/g4x_dp.c

143

intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);

drivers/gpu/drm/i915/display/g4x_dp.c

145

intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

drivers/gpu/drm/i915/display/g4x_dp.c

153

intel_dp->DP |= DP_COLOR_RANGE_16_235;

drivers/gpu/drm/i915/display/g4x_dp.c

156

intel_dp->DP |= DP_SYNC_HS_HIGH;

drivers/gpu/drm/i915/display/g4x_dp.c

158

intel_dp->DP |= DP_SYNC_VS_HIGH;

drivers/gpu/drm/i915/display/g4x_dp.c

159

intel_dp->DP |= DP_LINK_TRAIN_OFF;

drivers/gpu/drm/i915/display/g4x_dp.c

162

intel_dp->DP |= DP_ENHANCED_FRAMING;

drivers/gpu/drm/i915/display/g4x_dp.c

165

intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);

drivers/gpu/drm/i915/display/g4x_dp.c

167

intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);

drivers/gpu/drm/i915/display/g4x_dp.c

171

static void assert_dp_port(struct intel_dp *intel_dp, bool state)

drivers/gpu/drm/i915/display/g4x_dp.c

173

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

174

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

175

bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN;

drivers/gpu/drm/i915/display/g4x_dp.c

195

static void ilk_edp_pll_on(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/g4x_dp.c

198

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

202

assert_dp_port_disabled(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

208

intel_dp->DP &= ~EDP_PLL_FREQ_MASK;

drivers/gpu/drm/i915/display/g4x_dp.c

211

intel_dp->DP |= EDP_PLL_FREQ_162MHZ;

drivers/gpu/drm/i915/display/g4x_dp.c

213

intel_dp->DP |= EDP_PLL_FREQ_270MHZ;

drivers/gpu/drm/i915/display/g4x_dp.c

215

intel_de_write(display, DP_A, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

228

intel_dp->DP |= EDP_PLL_ENABLE;

drivers/gpu/drm/i915/display/g4x_dp.c

230

intel_de_write(display, DP_A, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

235

static void ilk_edp_pll_off(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/g4x_dp.c

238

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

241

assert_dp_port_disabled(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

246

intel_dp->DP &= ~EDP_PLL_ENABLE;

drivers/gpu/drm/i915/display/g4x_dp.c

248

intel_de_write(display, DP_A, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

304

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

313

ret = g4x_dp_port_enabled(display, intel_dp->output_reg,

drivers/gpu/drm/i915/display/g4x_dp.c

340

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

350

tmp = intel_de_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

405

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/g4x_dp.c

416

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

421

(intel_de_read(display, intel_dp->output_reg) &

drivers/gpu/drm/i915/display/g4x_dp.c

427

intel_dp->DP &= ~DP_PORT_EN;

drivers/gpu/drm/i915/display/g4x_dp.c

428

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

429

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

445

intel_dp->DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);

drivers/gpu/drm/i915/display/g4x_dp.c

446

intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |

drivers/gpu/drm/i915/display/g4x_dp.c

448

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

449

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

451

intel_dp->DP &= ~DP_PORT_EN;

drivers/gpu/drm/i915/display/g4x_dp.c

452

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

453

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

460

msleep(intel_dp->pps.panel_power_down_delay);

drivers/gpu/drm/i915/display/g4x_dp.c

471

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

477

intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;

drivers/gpu/drm/i915/display/g4x_dp.c

478

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

488

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

496

intel_dp->DP &= ~DP_AUDIO_OUTPUT_ENABLE;

drivers/gpu/drm/i915/display/g4x_dp.c

497

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

505

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

507

intel_dp->link.active = false;

drivers/gpu/drm/i915/display/g4x_dp.c

513

intel_pps_vdd_on(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

515

intel_dp_set_power(intel_dp, DP_SET_POWER_D3);

drivers/gpu/drm/i915/display/g4x_dp.c

516

intel_pps_off(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

540

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

553

ilk_edp_pll_off(intel_dp, old_crtc_state);

drivers/gpu/drm/i915/display/g4x_dp.c

576

cpt_set_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/g4x_dp.c

580

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

582

intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;

drivers/gpu/drm/i915/display/g4x_dp.c

586

intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

drivers/gpu/drm/i915/display/g4x_dp.c

589

intel_dp->DP |= DP_LINK_TRAIN_PAT_1_CPT;

drivers/gpu/drm/i915/display/g4x_dp.c

592

intel_dp->DP |= DP_LINK_TRAIN_PAT_2_CPT;

drivers/gpu/drm/i915/display/g4x_dp.c

599

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

600

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

604

cpt_set_idle_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/g4x_dp.c

607

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

609

intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;

drivers/gpu/drm/i915/display/g4x_dp.c

610

intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;

drivers/gpu/drm/i915/display/g4x_dp.c

612

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

613

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

617

g4x_set_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/g4x_dp.c

621

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

623

intel_dp->DP &= ~DP_LINK_TRAIN_MASK;

drivers/gpu/drm/i915/display/g4x_dp.c

627

intel_dp->DP |= DP_LINK_TRAIN_OFF;

drivers/gpu/drm/i915/display/g4x_dp.c

630

intel_dp->DP |= DP_LINK_TRAIN_PAT_1;

drivers/gpu/drm/i915/display/g4x_dp.c

633

intel_dp->DP |= DP_LINK_TRAIN_PAT_2;

drivers/gpu/drm/i915/display/g4x_dp.c

640

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

641

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

645

g4x_set_idle_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/g4x_dp.c

648

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

650

intel_dp->DP &= ~DP_LINK_TRAIN_MASK;

drivers/gpu/drm/i915/display/g4x_dp.c

651

intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;

drivers/gpu/drm/i915/display/g4x_dp.c

653

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

654

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

657

static void intel_dp_enable_port(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/g4x_dp.c

660

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

664

intel_dp_program_link_training_pattern(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/g4x_dp.c

673

intel_dp->DP |= DP_PORT_EN;

drivers/gpu/drm/i915/display/g4x_dp.c

675

intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

drivers/gpu/drm/i915/display/g4x_dp.c

676

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

685

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

686

u32 dp_reg = intel_de_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

691

with_intel_pps_lock(intel_dp) {

drivers/gpu/drm/i915/display/g4x_dp.c

695

intel_dp_enable_port(intel_dp, pipe_config);

drivers/gpu/drm/i915/display/g4x_dp.c

697

intel_pps_vdd_on_unlocked(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

698

intel_pps_on_unlocked(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

699

intel_pps_vdd_off_unlocked(intel_dp, true);

drivers/gpu/drm/i915/display/g4x_dp.c

711

intel_dp_set_power(intel_dp, DP_SET_POWER_D0);

drivers/gpu/drm/i915/display/g4x_dp.c

712

intel_dp_configure_protocol_converter(intel_dp, pipe_config);

drivers/gpu/drm/i915/display/g4x_dp.c

713

intel_dp_check_frl_training(intel_dp);

drivers/gpu/drm/i915/display/g4x_dp.c

714

intel_dp_pcon_dsc_configure(intel_dp, pipe_config);

drivers/gpu/drm/i915/display/g4x_dp.c

715

intel_dp_start_link_train(state, intel_dp, pipe_config);

drivers/gpu/drm/i915/display/g4x_dp.c

716

intel_dp_stop_link_train(intel_dp, pipe_config);

drivers/gpu/drm/i915/display/g4x_dp.c

741

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

748

ilk_edp_pll_on(intel_dp, pipe_config);

drivers/gpu/drm/i915/display/g4x_dp.c

802

static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/g4x_dp.c

808

static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/g4x_dp.c

814

static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/g4x_dp.c

819

static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/g4x_dp.c

827

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

830

u8 train_set = intel_dp->train_set[0];

drivers/gpu/drm/i915/display/g4x_dp.c

913

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.c

916

u8 train_set = intel_dp->train_set[0];

drivers/gpu/drm/i915/display/g4x_dp.c

97

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/g4x_dp.h

17

struct intel_dp;

drivers/gpu/drm/i915/display/intel_alpm.c

118

_lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.c

121

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

148

static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.c

151

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

164

if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_alpm.c

200

bool intel_alpm_compute_params(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.c

203

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

208

int precharge = intel_dp_aux_fw_sync_len(intel_dp) - preamble;

drivers/gpu/drm/i915/display/intel_alpm.c

232

if (!_lnl_compute_alpm_params(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_alpm.c

245

void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.c

249

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

254

if (intel_dp->alpm.lobf_disable_debug) {

drivers/gpu/drm/i915/display/intel_alpm.c

259

if (intel_dp->alpm.sink_alpm_error)

drivers/gpu/drm/i915/display/intel_alpm.c

262

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_alpm.c

268

if (!intel_dp->as_sdp_supported)

drivers/gpu/drm/i915/display/intel_alpm.c

27

bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_alpm.c

278

if (!(intel_alpm_aux_wake_supported(intel_dp) ||

drivers/gpu/drm/i915/display/intel_alpm.c

279

intel_alpm_aux_less_wake_supported(intel_dp)))

drivers/gpu/drm/i915/display/intel_alpm.c

282

if (!intel_alpm_compute_params(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_alpm.c

289

if (intel_alpm_aux_less_wake_supported(intel_dp))

drivers/gpu/drm/i915/display/intel_alpm.c

29

return intel_dp->alpm_dpcd & DP_ALPM_CAP;

drivers/gpu/drm/i915/display/intel_alpm.c

298

static void lnl_alpm_configure(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.c

301

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

305

if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&

drivers/gpu/drm/i915/display/intel_alpm.c

309

mutex_lock(&intel_dp->alpm.lock);

drivers/gpu/drm/i915/display/intel_alpm.c

314

if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {

drivers/gpu/drm/i915/display/intel_alpm.c

32

bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_alpm.c

320

if (intel_dp->as_sdp_supported) {

drivers/gpu/drm/i915/display/intel_alpm.c

34

return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP;

drivers/gpu/drm/i915/display/intel_alpm.c

345

mutex_unlock(&intel_dp->alpm.lock);

drivers/gpu/drm/i915/display/intel_alpm.c

348

void intel_alpm_configure(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.c

351

lnl_alpm_configure(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_alpm.c

352

intel_dp->alpm.transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_alpm.c

355

void intel_alpm_port_configure(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.c

358

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

359

enum port port = dp_to_dig_port(intel_dp)->base.port;

drivers/gpu/drm/i915/display/intel_alpm.c

365

if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {

drivers/gpu/drm/i915/display/intel_alpm.c

37

bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.c

40

return intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) ||

drivers/gpu/drm/i915/display/intel_alpm.c

404

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_alpm.c

409

intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_alpm.c

41

(crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));

drivers/gpu/drm/i915/display/intel_alpm.c

411

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_alpm.c

415

mutex_lock(&intel_dp->alpm.lock);

drivers/gpu/drm/i915/display/intel_alpm.c

418

mutex_unlock(&intel_dp->alpm.lock);

drivers/gpu/drm/i915/display/intel_alpm.c

423

void intel_alpm_enable_sink(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.c

428

if (!intel_psr_needs_alpm(intel_dp, crtc_state) && !crtc_state->has_lobf)

drivers/gpu/drm/i915/display/intel_alpm.c

434

intel_alpm_aux_less_wake_supported(intel_dp)))

drivers/gpu/drm/i915/display/intel_alpm.c

437

drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val);

drivers/gpu/drm/i915/display/intel_alpm.c

44

void intel_alpm_init(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_alpm.c

456

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_alpm.c

46

mutex_init(&intel_dp->alpm.lock);

drivers/gpu/drm/i915/display/intel_alpm.c

461

intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_alpm.c

463

if (intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_alpm.c

464

intel_alpm_enable_sink(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_alpm.c

465

intel_alpm_configure(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_alpm.c

510

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_alpm.c

512

*val = intel_dp->alpm.lobf_disable_debug;

drivers/gpu/drm/i915/display/intel_alpm.c

521

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_alpm.c

523

intel_dp->alpm.lobf_disable_debug = val;

drivers/gpu/drm/i915/display/intel_alpm.c

548

void intel_alpm_disable(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_alpm.c

550

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

551

enum transcoder cpu_transcoder = intel_dp->alpm.transcoder;

drivers/gpu/drm/i915/display/intel_alpm.c

553

if (DISPLAY_VER(display) < 20 || !intel_dp->alpm_dpcd)

drivers/gpu/drm/i915/display/intel_alpm.c

556

mutex_lock(&intel_dp->alpm.lock);

drivers/gpu/drm/i915/display/intel_alpm.c

562

mutex_unlock(&intel_dp->alpm.lock);

drivers/gpu/drm/i915/display/intel_alpm.c

565

bool intel_alpm_get_error(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_alpm.c

567

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.c

568

struct drm_dp_aux *aux = &intel_dp->aux;

drivers/gpu/drm/i915/display/intel_alpm.h

11

struct intel_dp;

drivers/gpu/drm/i915/display/intel_alpm.h

18

void intel_alpm_init(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.h

19

bool intel_alpm_compute_params(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.h

21

void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.h

24

void intel_alpm_configure(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.h

26

void intel_alpm_enable_sink(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.h

30

void intel_alpm_port_configure(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.h

35

bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.h

36

bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.h

37

bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_alpm.h

39

void intel_alpm_disable(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_alpm.h

40

bool intel_alpm_get_error(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_cdclk.c

2627

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_cdclk.c

2629

intel_psr_pause(intel_dp);

drivers/gpu/drm/i915/display/intel_cdclk.c

2641

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_cdclk.c

2643

mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,

drivers/gpu/drm/i915/display/intel_cdclk.c

2650

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_cdclk.c

2652

mutex_unlock(&intel_dp->aux.hw_mutex);

drivers/gpu/drm/i915/display/intel_cdclk.c

2657

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_cdclk.c

2659

intel_psr_resume(intel_dp);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

111

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

114

intel_psr_pause(intel_dp);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

124

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

126

intel_psr_resume(intel_dp);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2055

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2057

(intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);

drivers/gpu/drm/i915/display/intel_ddi.c

1128

static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

1131

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

1132

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_ddi.c

1152

static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_ddi.c

1183

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1186

intel_dp->hobl_active = is_hobl_buf_trans(trans);

drivers/gpu/drm/i915/display/intel_ddi.c

1188

intel_dp->hobl_active ? val : 0);

drivers/gpu/drm/i915/display/intel_ddi.c

1468

static int translate_signal_level(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

1471

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

1491

static int intel_ddi_dp_level(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

1495

u8 train_set = intel_dp->train_set[lane];

drivers/gpu/drm/i915/display/intel_ddi.c

1503

return translate_signal_level(intel_dp, signal_levels);

drivers/gpu/drm/i915/display/intel_ddi.c

1536

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

1553

intel_dp->DP &= ~DDI_BUF_EMP_MASK;

drivers/gpu/drm/i915/display/intel_ddi.c

1554

intel_dp->DP |= signal_levels;

drivers/gpu/drm/i915/display/intel_ddi.c

1556

intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP);

drivers/gpu/drm/i915/display/intel_ddi.c

2317

static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

2321

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

2326

if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,

drivers/gpu/drm/i915/display/intel_ddi.c

2333

static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

2337

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

2342

if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION,

drivers/gpu/drm/i915/display/intel_ddi.c

2348

drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS,

drivers/gpu/drm/i915/display/intel_ddi.c

2381

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2405

ret = wait_for_fec_detected(&intel_dp->aux, enabled);

drivers/gpu/drm/i915/display/intel_ddi.c

2629

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2634

intel_dp_set_link_params(intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

2657

intel_pps_on(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

2681

intel_dp_set_power(intel_dp, DP_SET_POWER_D0);

drivers/gpu/drm/i915/display/intel_ddi.c

2683

transparent_mode = intel_dp_lttpr_transparent_mode_enabled(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

2684

drm_dp_lttpr_wake_timeout_setup(&intel_dp->aux, transparent_mode);

drivers/gpu/drm/i915/display/intel_ddi.c

2686

intel_dp_configure_protocol_converter(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2697

intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);

drivers/gpu/drm/i915/display/intel_ddi.c

2699

intel_dp_check_frl_training(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

2700

intel_dp_pcon_dsc_configure(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2721

intel_dp_start_link_train(state, intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2725

intel_dp_stop_link_train(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2733

ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);

drivers/gpu/drm/i915/display/intel_ddi.c

2748

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2753

intel_dp_set_link_params(intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

2771

intel_pps_on(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

2845

intel_dp_set_power(intel_dp, DP_SET_POWER_D0);

drivers/gpu/drm/i915/display/intel_ddi.c

2847

intel_dp_configure_protocol_converter(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2857

intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);

drivers/gpu/drm/i915/display/intel_ddi.c

2859

intel_dp_check_frl_training(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

2860

intel_dp_pcon_dsc_configure(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2869

intel_dp_start_link_train(state, intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2873

intel_dp_stop_link_train(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2880

ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu);

drivers/gpu/drm/i915/display/intel_ddi.c

2895

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

2906

intel_dp_set_link_params(intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

2916

intel_pps_on(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

2936

intel_dp_set_power(intel_dp, DP_SET_POWER_D0);

drivers/gpu/drm/i915/display/intel_ddi.c

2937

intel_dp_configure_protocol_converter(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2942

intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true);

drivers/gpu/drm/i915/display/intel_ddi.c

2943

intel_dp_start_link_train(state, intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

2946

intel_dp_stop_link_train(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3132

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_ddi.c

3145

intel_dp_set_power(intel_dp, DP_SET_POWER_D3);

drivers/gpu/drm/i915/display/intel_ddi.c

3163

intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false);

drivers/gpu/drm/i915/display/intel_ddi.c

3175

intel_pps_vdd_on(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

3176

intel_pps_off(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

3231

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3248

drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0);

drivers/gpu/drm/i915/display/intel_ddi.c

3256

drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0);

drivers/gpu/drm/i915/display/intel_ddi.c

3372

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3377

intel_dp_stop_link_train(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3539

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3547

drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0);

drivers/gpu/drm/i915/display/intel_ddi.c

357

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3575

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

3579

intel_dp->link.active = false;

drivers/gpu/drm/i915/display/intel_ddi.c

3582

intel_psr_disable(intel_dp, old_crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3583

intel_alpm_disable(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

3589

intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,

drivers/gpu/drm/i915/display/intel_ddi.c

361

intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) |

drivers/gpu/drm/i915/display/intel_ddi.c

365

intel_dp->DP |= DDI_BUF_PORT_REVERSAL;

drivers/gpu/drm/i915/display/intel_ddi.c

367

intel_dp->DP |= DDI_A_4_LANES;

drivers/gpu/drm/i915/display/intel_ddi.c

371

intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;

drivers/gpu/drm/i915/display/intel_ddi.c

3727

static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

373

intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;

drivers/gpu/drm/i915/display/intel_ddi.c

3731

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

3767

intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;

drivers/gpu/drm/i915/display/intel_ddi.c

3769

intel_ddi_buf_enable(encoder, intel_dp->DP);

drivers/gpu/drm/i915/display/intel_ddi.c

377

intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);

drivers/gpu/drm/i915/display/intel_ddi.c

3770

intel_dp->DP |= DDI_BUF_CTL_ENABLE;

drivers/gpu/drm/i915/display/intel_ddi.c

3776

intel_alpm_port_configure(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_ddi.c

3785

static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

3788

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

3789

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

379

intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;

drivers/gpu/drm/i915/display/intel_ddi.c

3813

intel_ddi_buf_enable(encoder, intel_dp->DP);

drivers/gpu/drm/i915/display/intel_ddi.c

3814

intel_dp->DP |= DDI_BUF_CTL_ENABLE;

drivers/gpu/drm/i915/display/intel_ddi.c

3817

static void intel_ddi_set_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

3821

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

3822

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_ddi.c

3849

static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_ddi.c

385

intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay);

drivers/gpu/drm/i915/display/intel_ddi.c

3852

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

3853

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_ddi.c

4152

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

4158

if (intel_dp_mst_active_streams(intel_dp))

drivers/gpu/drm/i915/display/intel_ddi.c

4676

struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));

drivers/gpu/drm/i915/display/intel_ddi.c

4679

intel_dp->reset_link_params = true;

drivers/gpu/drm/i915/display/intel_ddi.c

4680

intel_dp_invalidate_source_oui(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

4682

intel_pps_encoder_reset(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

4832

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_ddi.c

4838

if (intel_dp_test_phy(intel_dp))

drivers/gpu/drm/i915/display/intel_ddi.c

4849

intel_dp_check_link_state(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

5064

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

5065

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

5085

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

5086

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_ddi.c

890

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi.c

903

intel_dp_mst_active_streams(intel_dp))

drivers/gpu/drm/i915/display/intel_ddi.h

18

struct intel_dp;

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1189

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1190

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1192

return connector->panel.vbt.edp.hobl && !intel_dp->hobl_failed;

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1197

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

1198

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1043

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1051

intel_dp->force_dsc_bpc = dsc_bpc;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1110

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1118

intel_dp->force_dsc_output_format = dsc_output_format;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1145

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1161

intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1163

str_yes_no(intel_dp->force_dsc_fractional_bpp_en));

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1179

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

1195

intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

217

struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

219

seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

223

drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,

drivers/gpu/drm/i915/display/intel_display_debugfs.c

224

connector->detect_edid, &intel_dp->aux);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

895

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

930

intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

946

drm_dp_dsc_sink_max_slice_count((connector->dp.dsc_dpcd), intel_dp_is_edp(intel_dp)));

drivers/gpu/drm/i915/display/intel_display_debugfs.c

948

str_yes_no(intel_dp->force_dsc_en));

drivers/gpu/drm/i915/display/intel_display_debugfs.c

949

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_display_debugfs.c

968

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

984

intel_dp->force_dsc_en = dsc_enable;

drivers/gpu/drm/i915/display/intel_display_irq.c

1290

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_display_irq.c

1294

intel_dp->psr.transcoder);

drivers/gpu/drm/i915/display/intel_display_irq.c

1303

intel_psr_irq_handler(intel_dp, psr_iir);

drivers/gpu/drm/i915/display/intel_display_irq.c

960

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_display_irq.c

964

intel_psr_irq_handler(intel_dp, psr_iir);

drivers/gpu/drm/i915/display/intel_display_types.h

1878

u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);

drivers/gpu/drm/i915/display/intel_display_types.h

1883

u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,

drivers/gpu/drm/i915/display/intel_display_types.h

1886

i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);

drivers/gpu/drm/i915/display/intel_display_types.h

1887

i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);

drivers/gpu/drm/i915/display/intel_display_types.h

1890

void (*prepare_link_retrain)(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_display_types.h

1892

void (*set_link_train)(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_display_types.h

1895

void (*set_idle_link_train)(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_display_types.h

1898

u8 (*preemph_max)(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_display_types.h

1899

u8 (*voltage_max)(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_display_types.h

1967

struct intel_dp dp;

drivers/gpu/drm/i915/display/intel_display_types.h

2093

static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)

drivers/gpu/drm/i915/display/intel_display_types.h

2098

static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector)

drivers/gpu/drm/i915/display/intel_display_types.h

2134

dp_to_dig_port(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_display_types.h

2136

return container_of(intel_dp, struct intel_digital_port, dp);

drivers/gpu/drm/i915/display/intel_display_types.h

2297

__assoc(intel_dp, p), \

drivers/gpu/drm/i915/display/intel_display_types.h

599

struct intel_dp *dp;

drivers/gpu/drm/i915/display/intel_dp.c

1070

static bool source_can_output(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

1073

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1098

dfp_can_convert_from_rgb(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

1101

if (!drm_dp_is_branch(intel_dp->dpcd))

drivers/gpu/drm/i915/display/intel_dp.c

1105

return intel_dp->dfp.rgb_to_ycbcr;

drivers/gpu/drm/i915/display/intel_dp.c

1108

return intel_dp->dfp.rgb_to_ycbcr &&

drivers/gpu/drm/i915/display/intel_dp.c

1109

intel_dp->dfp.ycbcr_444_to_420;

drivers/gpu/drm/i915/display/intel_dp.c

1115

dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

1118

if (!drm_dp_is_branch(intel_dp->dpcd))

drivers/gpu/drm/i915/display/intel_dp.c

1122

return intel_dp->dfp.ycbcr_444_to_420;

drivers/gpu/drm/i915/display/intel_dp.c

1128

dfp_can_convert(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

1134

return dfp_can_convert_from_rgb(intel_dp, sink_format);

drivers/gpu/drm/i915/display/intel_dp.c

1136

return dfp_can_convert_from_ycbcr444(intel_dp, sink_format);

drivers/gpu/drm/i915/display/intel_dp.c

1150

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

1152

intel_dp->force_dsc_output_format;

drivers/gpu/drm/i915/display/intel_dp.c

1155

if (source_can_output(intel_dp, force_dsc_output_format) &&

drivers/gpu/drm/i915/display/intel_dp.c

1156

(!drm_dp_is_branch(intel_dp->dpcd) ||

drivers/gpu/drm/i915/display/intel_dp.c

1158

dfp_can_convert(intel_dp, force_dsc_output_format, sink_format)))

drivers/gpu/drm/i915/display/intel_dp.c

1165

dfp_can_convert_from_rgb(intel_dp, sink_format))

drivers/gpu/drm/i915/display/intel_dp.c

1169

dfp_can_convert_from_ycbcr444(intel_dp, sink_format))

drivers/gpu/drm/i915/display/intel_dp.c

1175

drm_WARN_ON(display->drm, !source_can_output(intel_dp, output_format));

drivers/gpu/drm/i915/display/intel_dp.c

1246

static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

1248

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

1250

int max_tmds_clock = intel_dp->dfp.max_tmds_clock;

drivers/gpu/drm/i915/display/intel_dp.c

1260

intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

1272

min_tmds_clock = intel_dp->dfp.min_tmds_clock;

drivers/gpu/drm/i915/display/intel_dp.c

1273

max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1289

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

1295

if (intel_dp->dfp.pcon_max_frl_bw) {

drivers/gpu/drm/i915/display/intel_dp.c

1302

max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;

drivers/gpu/drm/i915/display/intel_dp.c

1313

if (intel_dp->dfp.max_dotclock &&

drivers/gpu/drm/i915/display/intel_dp.c

1314

target_clock > intel_dp->dfp.max_dotclock)

drivers/gpu/drm/i915/display/intel_dp.c

1320

status = intel_dp_tmds_clock_valid(intel_dp, target_clock,

drivers/gpu/drm/i915/display/intel_dp.c

1329

status = intel_dp_tmds_clock_valid(intel_dp, target_clock,

drivers/gpu/drm/i915/display/intel_dp.c

133

bool intel_dp_is_edp(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

1339

bool intel_dp_needs_joiner(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

1344

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1347

if (!intel_dp_has_joiner(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

135

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1358

int intel_dp_num_joined_pipes(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

1362

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1368

intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 4))

drivers/gpu/drm/i915/display/intel_dp.c

1372

intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 2))

drivers/gpu/drm/i915/display/intel_dp.c

140

static void intel_dp_unset_edid(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1404

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

1428

if (intel_dp_is_edp(intel_dp) && fixed_mode) {

drivers/gpu/drm/i915/display/intel_dp.c

1436

num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,

drivers/gpu/drm/i915/display/intel_dp.c

1453

max_link_clock = intel_dp_max_link_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1454

max_lanes = intel_dp_max_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1456

max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes);

drivers/gpu/drm/i915/display/intel_dp.c

1476

if (intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

1530

static void intel_dp_print_rates(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

1532

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1538

seq_buf_print_array(&s, intel_dp->source_rates, intel_dp->num_source_rates);

drivers/gpu/drm/i915/display/intel_dp.c

1542

seq_buf_print_array(&s, intel_dp->sink_rates, intel_dp->num_sink_rates);

drivers/gpu/drm/i915/display/intel_dp.c

1546

seq_buf_print_array(&s, intel_dp->common_rates, intel_dp->num_common_rates);

drivers/gpu/drm/i915/display/intel_dp.c

1550

static int forced_link_rate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

1552

int len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.force_rate);

drivers/gpu/drm/i915/display/intel_dp.c

1555

return intel_dp_common_rate(intel_dp, 0);

drivers/gpu/drm/i915/display/intel_dp.c

1557

return intel_dp_common_rate(intel_dp, len - 1);

drivers/gpu/drm/i915/display/intel_dp.c

1561

intel_dp_max_link_rate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

1565

if (intel_dp->link.force_rate)

drivers/gpu/drm/i915/display/intel_dp.c

1566

return forced_link_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1568

len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate);

drivers/gpu/drm/i915/display/intel_dp.c

1570

return intel_dp_common_rate(intel_dp, len - 1);

drivers/gpu/drm/i915/display/intel_dp.c

1574

intel_dp_min_link_rate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

1576

if (intel_dp->link.force_rate)

drivers/gpu/drm/i915/display/intel_dp.c

1577

return forced_link_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1579

return intel_dp_common_rate(intel_dp, 0);

drivers/gpu/drm/i915/display/intel_dp.c

1582

int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)

drivers/gpu/drm/i915/display/intel_dp.c

1584

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1585

int i = intel_dp_rate_index(intel_dp->sink_rates,

drivers/gpu/drm/i915/display/intel_dp.c

1586

intel_dp->num_sink_rates, rate);

drivers/gpu/drm/i915/display/intel_dp.c

1594

void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,

drivers/gpu/drm/i915/display/intel_dp.c

1597

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1604

if (intel_dp->use_rate_select) {

drivers/gpu/drm/i915/display/intel_dp.c

1607

intel_dp_rate_select(intel_dp, port_clock);

drivers/gpu/drm/i915/display/intel_dp.c

1614

bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

1616

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

1621

static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

1624

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1625

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

1637

bool intel_dp_supports_fec(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

1641

return intel_dp_source_supports_fec(intel_dp, pipe_config) &&

drivers/gpu/drm/i915/display/intel_dp.c

1645

bool intel_dp_supports_dsc(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

1653

!intel_dp_supports_fec(intel_dp, connector, crtc_state))

drivers/gpu/drm/i915/display/intel_dp.c

1659

static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

1682

intel_dp_has_hdmi_sink(intel_dp)) &&

drivers/gpu/drm/i915/display/intel_dp.c

1683

intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,

drivers/gpu/drm/i915/display/intel_dp.c

1691

static int intel_dp_max_bpp(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

1695

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1696

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

1701

if (intel_dp->dfp.max_bpc)

drivers/gpu/drm/i915/display/intel_dp.c

1702

bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);

drivers/gpu/drm/i915/display/intel_dp.c

1704

if (intel_dp->dfp.min_tmds_clock) {

drivers/gpu/drm/i915/display/intel_dp.c

1707

max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,

drivers/gpu/drm/i915/display/intel_dp.c

1716

if (intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

172

static int max_dprx_rate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

174

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

1758

intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

177

if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

1772

for (i = 0; i < intel_dp->num_common_rates; i++) {

drivers/gpu/drm/i915/display/intel_dp.c

1773

link_rate = intel_dp_common_rate(intel_dp, i);

drivers/gpu/drm/i915/display/intel_dp.c

178

max_rate = drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp.c

1788

link_avail = intel_dp_max_link_data_rate(intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

180

max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);

drivers/gpu/drm/i915/display/intel_dp.c

188

if (intel_dp_is_edp(intel_dp) && intel_has_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2))

drivers/gpu/drm/i915/display/intel_dp.c

194

static int max_dprx_lane_count(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

196

if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

197

return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp.c

1974

static bool is_bw_sufficient_for_dsc_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

1983

available_bw = intel_dp_max_link_data_rate(intel_dp, link_clock, lane_count);

drivers/gpu/drm/i915/display/intel_dp.c

199

return drm_dp_max_lane_count(intel_dp->dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

1991

static int dsc_compute_link_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

2001

for (i = 0; i < intel_dp->num_common_rates; i++) {

drivers/gpu/drm/i915/display/intel_dp.c

2002

link_rate = intel_dp_common_rate(intel_dp, i);

drivers/gpu/drm/i915/display/intel_dp.c

202

static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

2024

ret = intel_dp_mtp_tu_compute_config(intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

2036

if (!is_bw_sufficient_for_dsc_config(intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

204

intel_dp->sink_rates[0] = 162000;

drivers/gpu/drm/i915/display/intel_dp.c

205

intel_dp->num_sink_rates = 1;

drivers/gpu/drm/i915/display/intel_dp.c

209

static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

2111

static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

2113

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2121

if (intel_dp->force_dsc_en)

drivers/gpu/drm/i915/display/intel_dp.c

2157

bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16)

drivers/gpu/drm/i915/display/intel_dp.c

2159

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2162

if (intel_dp->force_dsc_fractional_bpp_en && !fxp_q4_to_frac(bpp_x16))

drivers/gpu/drm/i915/display/intel_dp.c

217

if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {

drivers/gpu/drm/i915/display/intel_dp.c

221

memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));

drivers/gpu/drm/i915/display/intel_dp.c

2212

static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

2218

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

222

intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);

drivers/gpu/drm/i915/display/intel_dp.c

2230

if (intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

2240

if (!intel_dp_dsc_valid_compressed_bpp(intel_dp, bpp_x16))

drivers/gpu/drm/i915/display/intel_dp.c

2243

ret = dsc_compute_link_config(intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

2250

if (intel_dp->force_dsc_fractional_bpp_en &&

drivers/gpu/drm/i915/display/intel_dp.c

2277

int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

2280

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2283

if (!intel_dp->force_dsc_bpc)

drivers/gpu/drm/i915/display/intel_dp.c

2286

forced_bpp = intel_dp->force_dsc_bpc * 3;

drivers/gpu/drm/i915/display/intel_dp.c

2290

intel_dp->force_dsc_bpc);

drivers/gpu/drm/i915/display/intel_dp.c

2296

intel_dp->force_dsc_bpc);

drivers/gpu/drm/i915/display/intel_dp.c

230

max_rate = max_dprx_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2301

static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

2309

forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);

drivers/gpu/drm/i915/display/intel_dp.c

231

max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);

drivers/gpu/drm/i915/display/intel_dp.c

2315

ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state,

drivers/gpu/drm/i915/display/intel_dp.c

2347

int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

2353

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2376

ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,

drivers/gpu/drm/i915/display/intel_dp.c

238

intel_dp->sink_rates[i] = dp_rates[i];

drivers/gpu/drm/i915/display/intel_dp.c

2386

if (intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

245

if (drm_dp_128b132b_supported(intel_dp->dpcd)) {

drivers/gpu/drm/i915/display/intel_dp.c

248

BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);

drivers/gpu/drm/i915/display/intel_dp.c

250

drm_dp_dpcd_readb(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp.c

2503

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

2508

dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

253

if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {

drivers/gpu/drm/i915/display/intel_dp.c

2545

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

255

if (intel_dp->lttpr_common_caps[0] >= 0x20 &&

drivers/gpu/drm/i915/display/intel_dp.c

256

intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -

drivers/gpu/drm/i915/display/intel_dp.c

2563

return is_bw_sufficient_for_dsc_config(intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

2581

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

2585

const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

260

uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -

drivers/gpu/drm/i915/display/intel_dp.c

2664

intel_dp_compute_config_limits(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

2671

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2676

limits->min_rate = intel_dp_min_link_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2677

limits->max_rate = intel_dp_max_link_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2681

limits->min_lane_count = intel_dp_min_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2682

limits->max_lane_count = intel_dp_max_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

269

intel_dp->sink_rates[i++] = 1000000;

drivers/gpu/drm/i915/display/intel_dp.c

2696

limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

2701

if (intel_dp_supports_dsc(intel_dp, connector, crtc_state) &&

drivers/gpu/drm/i915/display/intel_dp.c

2709

str_yes_no(intel_dp_supports_dsc(intel_dp, connector,

drivers/gpu/drm/i915/display/intel_dp.c

271

intel_dp->sink_rates[i++] = 1350000;

drivers/gpu/drm/i915/display/intel_dp.c

2716

if (is_mst || intel_dp->use_max_params) {

drivers/gpu/drm/i915/display/intel_dp.c

273

intel_dp->sink_rates[i++] = 2000000;

drivers/gpu/drm/i915/display/intel_dp.c

2732

intel_dp_test_compute_config(intel_dp, crtc_state, limits);

drivers/gpu/drm/i915/display/intel_dp.c

276

intel_dp->num_sink_rates = i;

drivers/gpu/drm/i915/display/intel_dp.c

2778

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

2785

!intel_dp_supports_fec(intel_dp, connector, pipe_config))

drivers/gpu/drm/i915/display/intel_dp.c

2788

num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,

drivers/gpu/drm/i915/display/intel_dp.c

279

static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

2796

dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||

drivers/gpu/drm/i915/display/intel_dp.c

2797

!intel_dp_compute_config_limits(intel_dp, conn_state, pipe_config,

drivers/gpu/drm/i915/display/intel_dp.c

2807

ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,

drivers/gpu/drm/i915/display/intel_dp.c

281

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2810

ret = intel_dp_mtp_tu_compute_config(intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

282

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

2820

if (dsc_needed && !intel_dp_supports_dsc(intel_dp, connector, pipe_config)) {

drivers/gpu/drm/i915/display/intel_dp.c

2829

str_yes_no(intel_dp->force_dsc_en));

drivers/gpu/drm/i915/display/intel_dp.c

283

struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2831

if (!intel_dp_compute_config_limits(intel_dp, conn_state, pipe_config,

drivers/gpu/drm/i915/display/intel_dp.c

2837

ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,

drivers/gpu/drm/i915/display/intel_dp.c

2850

intel_dp_max_link_data_rate(intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

286

intel_dp_set_dpcd_sink_rates(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

288

if (intel_dp->num_sink_rates)

drivers/gpu/drm/i915/display/intel_dp.c

296

intel_dp_set_default_sink_rates(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

2989

static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

299

static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

2996

if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)

drivers/gpu/drm/i915/display/intel_dp.c

301

intel_dp->max_sink_lane_count = 1;

drivers/gpu/drm/i915/display/intel_dp.c

3016

static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

3022

if ((!intel_dp->colorimetry_support ||

drivers/gpu/drm/i915/display/intel_dp.c

304

static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

306

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

307

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

3078

intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

308

struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3082

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

311

intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

313

switch (intel_dp->max_sink_lane_count) {

drivers/gpu/drm/i915/display/intel_dp.c

3198

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

3199

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

324

intel_dp->max_sink_lane_count);

drivers/gpu/drm/i915/display/intel_dp.c

3255

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

3258

if (intel_dp->needs_modeset_retry)

drivers/gpu/drm/i915/display/intel_dp.c

326

intel_dp_set_default_max_sink_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3261

intel_dp->needs_modeset_retry = true;

drivers/gpu/drm/i915/display/intel_dp.c

3264

intel_connector_queue_modeset_retry_work(intel_dp->attached_connector);

drivers/gpu/drm/i915/display/intel_dp.c

3273

if (connector->mst.dp == intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

3375

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

3377

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

3381

if (intel_dp_is_edp(intel_dp) && fixed_mode) {

drivers/gpu/drm/i915/display/intel_dp.c

3410

if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||

drivers/gpu/drm/i915/display/intel_dp.c

3425

drm_dp_enhanced_frame_cap(intel_dp->dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

3434

if (intel_dp->mso_link_count) {

drivers/gpu/drm/i915/display/intel_dp.c

3435

int n = intel_dp->mso_link_count;

drivers/gpu/drm/i915/display/intel_dp.c

3436

int overlap = intel_dp->mso_pixel_overlap;

drivers/gpu/drm/i915/display/intel_dp.c

344

static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

347

return intel_dp_rate_limit_len(intel_dp->common_rates,

drivers/gpu/drm/i915/display/intel_dp.c

3475

intel_dp_compute_as_sdp(intel_dp, pipe_config);

drivers/gpu/drm/i915/display/intel_dp.c

3476

intel_psr_compute_config(intel_dp, pipe_config, conn_state);

drivers/gpu/drm/i915/display/intel_dp.c

3477

intel_alpm_lobf_compute_config(intel_dp, pipe_config, conn_state);

drivers/gpu/drm/i915/display/intel_dp.c

3479

intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);

drivers/gpu/drm/i915/display/intel_dp.c

348

intel_dp->num_common_rates, max_rate);

drivers/gpu/drm/i915/display/intel_dp.c

3480

intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);

drivers/gpu/drm/i915/display/intel_dp.c

3482

return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,

drivers/gpu/drm/i915/display/intel_dp.c

3486

void intel_dp_set_link_params(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

3489

memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));

drivers/gpu/drm/i915/display/intel_dp.c

3490

intel_dp->link.active = false;

drivers/gpu/drm/i915/display/intel_dp.c

3491

intel_dp->needs_modeset_retry = false;

drivers/gpu/drm/i915/display/intel_dp.c

3492

intel_dp->link_rate = link_rate;

drivers/gpu/drm/i915/display/intel_dp.c

3493

intel_dp->lane_count = lane_count;

drivers/gpu/drm/i915/display/intel_dp.c

3496

void intel_dp_reset_link_params(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

3498

intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3499

intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3500

intel_dp->link.mst_probed_lane_count = 0;

drivers/gpu/drm/i915/display/intel_dp.c

3501

intel_dp->link.mst_probed_rate = 0;

drivers/gpu/drm/i915/display/intel_dp.c

3502

intel_dp->link.retrain_disabled = false;

drivers/gpu/drm/i915/display/intel_dp.c

3503

intel_dp->link.seq_train_failures = 0;

drivers/gpu/drm/i915/display/intel_dp.c

351

int intel_dp_common_rate(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp.c

3511

struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));

drivers/gpu/drm/i915/display/intel_dp.c

3513

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

3519

intel_pps_backlight_on(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3525

struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));

drivers/gpu/drm/i915/display/intel_dp.c

3526

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3528

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

353

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3533

intel_pps_backlight_off(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3537

static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

3547

return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&

drivers/gpu/drm/i915/display/intel_dp.c

3548

drm_dp_is_branch(intel_dp->dpcd) &&

drivers/gpu/drm/i915/display/intel_dp.c

3549

intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;

drivers/gpu/drm/i915/display/intel_dp.c

356

index < 0 || index >= intel_dp->num_common_rates))

drivers/gpu/drm/i915/display/intel_dp.c

359

return intel_dp->common_rates[index];

drivers/gpu/drm/i915/display/intel_dp.c

363

int intel_dp_max_common_rate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

365

return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);

drivers/gpu/drm/i915/display/intel_dp.c

3726

intel_dp_init_source_oui(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

3728

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3732

if (READ_ONCE(intel_dp->oui_valid))

drivers/gpu/drm/i915/display/intel_dp.c

3735

WRITE_ONCE(intel_dp->oui_valid, true);

drivers/gpu/drm/i915/display/intel_dp.c

3741

if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)

drivers/gpu/drm/i915/display/intel_dp.c

3746

intel_dp->last_oui_write = jiffies;

drivers/gpu/drm/i915/display/intel_dp.c

3750

if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) {

drivers/gpu/drm/i915/display/intel_dp.c

3752

WRITE_ONCE(intel_dp->oui_valid, false);

drivers/gpu/drm/i915/display/intel_dp.c

3755

intel_dp->last_oui_write = jiffies;

drivers/gpu/drm/i915/display/intel_dp.c

3758

void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

3760

WRITE_ONCE(intel_dp->oui_valid, false);

drivers/gpu/drm/i915/display/intel_dp.c

3763

void intel_dp_wait_source_oui(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

3765

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3766

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

3773

wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,

drivers/gpu/drm/i915/display/intel_dp.c

3778

void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)

drivers/gpu/drm/i915/display/intel_dp.c

3780

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3781

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

3785

if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)

drivers/gpu/drm/i915/display/intel_dp.c

3789

if (downstream_hpd_needs_d0(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

3792

ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);

drivers/gpu/drm/i915/display/intel_dp.c

3794

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3799

intel_dp_init_source_oui(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

380

int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

3806

ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);

drivers/gpu/drm/i915/display/intel_dp.c

382

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3824

intel_dp_get_dpcd(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3837

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

384

int sink_max = intel_dp->max_sink_lane_count;

drivers/gpu/drm/i915/display/intel_dp.c

3844

if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) {

drivers/gpu/drm/i915/display/intel_dp.c

3845

intel_dp_get_dpcd(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3849

intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);

drivers/gpu/drm/i915/display/intel_dp.c

3852

intel_dp_reset_link_params(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3853

intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp.c

3854

intel_dp->link.active = true;

drivers/gpu/drm/i915/display/intel_dp.c

386

int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);

drivers/gpu/drm/i915/display/intel_dp.c

3862

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

3869

if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,

drivers/gpu/drm/i915/display/intel_dp.c

3893

if (CAN_PANEL_REPLAY(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

3904

static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

3906

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

3910

memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));

drivers/gpu/drm/i915/display/intel_dp.c

3912

if (!drm_dp_is_branch(intel_dp->dpcd))

drivers/gpu/drm/i915/display/intel_dp.c

3915

if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,

drivers/gpu/drm/i915/display/intel_dp.c

3916

intel_dp->pcon_dsc_dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

3917

sizeof(intel_dp->pcon_dsc_dpcd)) < 0)

drivers/gpu/drm/i915/display/intel_dp.c

3922

(int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

394

static int forced_lane_count(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

3957

static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

3959

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

396

return clamp(intel_dp->link.force_lane_count, 1, intel_dp_max_common_lane_count(intel_dp));

drivers/gpu/drm/i915/display/intel_dp.c

3980

intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

3983

if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&

drivers/gpu/drm/i915/display/intel_dp.c

3984

drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&

drivers/gpu/drm/i915/display/intel_dp.c

399

int intel_dp_max_lane_count(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

3991

static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

3993

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4000

max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;

drivers/gpu/drm/i915/display/intel_dp.c

4003

max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4015

if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))

drivers/gpu/drm/i915/display/intel_dp.c

4018

ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);

drivers/gpu/drm/i915/display/intel_dp.c

4022

ret = poll_timeout_us(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux),

drivers/gpu/drm/i915/display/intel_dp.c

4028

ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,

drivers/gpu/drm/i915/display/intel_dp.c

403

if (intel_dp->link.force_lane_count)

drivers/gpu/drm/i915/display/intel_dp.c

4032

ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,

drivers/gpu/drm/i915/display/intel_dp.c

4036

ret = drm_dp_pcon_frl_enable(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp.c

404

lane_count = forced_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4043

ret = poll_timeout_us(is_active = intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),

drivers/gpu/drm/i915/display/intel_dp.c

4051

intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);

drivers/gpu/drm/i915/display/intel_dp.c

4052

intel_dp->frl.is_trained = true;

drivers/gpu/drm/i915/display/intel_dp.c

4054

intel_dp->frl.trained_rate_gbps);

drivers/gpu/drm/i915/display/intel_dp.c

4059

static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

406

lane_count = intel_dp->link.max_lane_count;

drivers/gpu/drm/i915/display/intel_dp.c

4061

if (drm_dp_is_branch(intel_dp->dpcd) &&

drivers/gpu/drm/i915/display/intel_dp.c

4062

intel_dp_has_hdmi_sink(intel_dp) &&

drivers/gpu/drm/i915/display/intel_dp.c

4063

intel_dp_hdmi_sink_max_frl(intel_dp) > 0)

drivers/gpu/drm/i915/display/intel_dp.c

4070

int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4078

ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);

drivers/gpu/drm/i915/display/intel_dp.c

4084

ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);

drivers/gpu/drm/i915/display/intel_dp.c

4091

void intel_dp_check_frl_training(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4093

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4100

if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||

drivers/gpu/drm/i915/display/intel_dp.c

4101

!intel_dp_is_hdmi_2_1_sink(intel_dp) ||

drivers/gpu/drm/i915/display/intel_dp.c

4102

intel_dp->frl.is_trained)

drivers/gpu/drm/i915/display/intel_dp.c

4105

if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {

drivers/gpu/drm/i915/display/intel_dp.c

4110

ret = intel_dp_pcon_set_tmds_mode(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4111

mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);

drivers/gpu/drm/i915/display/intel_dp.c

4130

intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

4133

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

4137

int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

4138

int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

4146

intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

4150

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

4154

int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

4164

intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

4167

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4168

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

4178

if (!intel_dp_is_hdmi_2_1_sink(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

4188

if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||

drivers/gpu/drm/i915/display/intel_dp.c

419

static int intel_dp_min_lane_count(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4196

num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

4203

bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp.c

421

if (intel_dp->link.force_lane_count)

drivers/gpu/drm/i915/display/intel_dp.c

4215

ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);

drivers/gpu/drm/i915/display/intel_dp.c

422

return forced_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4220

void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

4223

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4228

if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)

drivers/gpu/drm/i915/display/intel_dp.c

4231

if (!drm_dp_is_branch(intel_dp->dpcd))

drivers/gpu/drm/i915/display/intel_dp.c

4234

tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0;

drivers/gpu/drm/i915/display/intel_dp.c

4236

if (drm_dp_dpcd_writeb(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp.c

4240

str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));

drivers/gpu/drm/i915/display/intel_dp.c

4272

if (drm_dp_dpcd_writeb(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp.c

4276

str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));

drivers/gpu/drm/i915/display/intel_dp.c

4280

if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)

drivers/gpu/drm/i915/display/intel_dp.c

4286

static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4290

if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,

drivers/gpu/drm/i915/display/intel_dp.c

4398

intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)

drivers/gpu/drm/i915/display/intel_dp.c

4400

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4406

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

4407

intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],

drivers/gpu/drm/i915/display/intel_dp.c

4410

intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],

drivers/gpu/drm/i915/display/intel_dp.c

4411

&intel_dp->desc, drm_dp_is_branch(intel_dp->dpcd),

drivers/gpu/drm/i915/display/intel_dp.c

4419

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

4420

int n = intel_dp->mso_link_count;

drivers/gpu/drm/i915/display/intel_dp.c

4421

int overlap = intel_dp->mso_pixel_overlap;

drivers/gpu/drm/i915/display/intel_dp.c

4443

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

4444

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

4467

static void intel_edp_mso_init(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4469

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4470

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

4474

if (intel_dp->edp_dpcd[0] < DP_EDP_14)

drivers/gpu/drm/i915/display/intel_dp.c

4477

if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {

drivers/gpu/drm/i915/display/intel_dp.c

4484

if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {

drivers/gpu/drm/i915/display/intel_dp.c

4492

mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,

drivers/gpu/drm/i915/display/intel_dp.c

4501

intel_dp->mso_link_count = mso;

drivers/gpu/drm/i915/display/intel_dp.c

4502

intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;

drivers/gpu/drm/i915/display/intel_dp.c

4506

intel_edp_set_data_override_rates(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4508

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

4509

int *sink_rates = intel_dp->sink_rates;

drivers/gpu/drm/i915/display/intel_dp.c

4512

for (i = 0; i < intel_dp->num_sink_rates; i++) {

drivers/gpu/drm/i915/display/intel_dp.c

4514

intel_dp->sink_rates[i]))

drivers/gpu/drm/i915/display/intel_dp.c

4517

sink_rates[count++] = intel_dp->sink_rates[i];

drivers/gpu/drm/i915/display/intel_dp.c

4519

intel_dp->num_sink_rates = count;

drivers/gpu/drm/i915/display/intel_dp.c

4523

intel_edp_set_sink_rates(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4525

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4527

intel_dp->num_sink_rates = 0;

drivers/gpu/drm/i915/display/intel_dp.c

4529

if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {

drivers/gpu/drm/i915/display/intel_dp.c

4533

drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,

drivers/gpu/drm/i915/display/intel_dp.c

4559

intel_dp->sink_rates[i] = rate;

drivers/gpu/drm/i915/display/intel_dp.c

4561

intel_dp->num_sink_rates = i;

drivers/gpu/drm/i915/display/intel_dp.c

4568

if (intel_dp->num_sink_rates)

drivers/gpu/drm/i915/display/intel_dp.c

4569

intel_dp->use_rate_select = true;

drivers/gpu/drm/i915/display/intel_dp.c

4571

intel_dp_set_sink_rates(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4573

intel_edp_set_data_override_rates(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4577

intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)

drivers/gpu/drm/i915/display/intel_dp.c

4579

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4583

drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);

drivers/gpu/drm/i915/display/intel_dp.c

4585

if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)

drivers/gpu/drm/i915/display/intel_dp.c

4588

drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,

drivers/gpu/drm/i915/display/intel_dp.c

4589

drm_dp_is_branch(intel_dp->dpcd));

drivers/gpu/drm/i915/display/intel_dp.c

4590

intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);

drivers/gpu/drm/i915/display/intel_dp.c

4592

intel_dp->colorimetry_support =

drivers/gpu/drm/i915/display/intel_dp.c

4593

intel_dp_get_colorimetry_status(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4604

if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,

drivers/gpu/drm/i915/display/intel_dp.c

4605

intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==

drivers/gpu/drm/i915/display/intel_dp.c

4606

sizeof(intel_dp->edp_dpcd)) {

drivers/gpu/drm/i915/display/intel_dp.c

4608

(int)sizeof(intel_dp->edp_dpcd),

drivers/gpu/drm/i915/display/intel_dp.c

4609

intel_dp->edp_dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

4611

intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;

drivers/gpu/drm/i915/display/intel_dp.c

4618

intel_dp_init_source_oui(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4621

ret = drm_dp_dpcd_read_byte(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,

drivers/gpu/drm/i915/display/intel_dp.c

4622

&intel_dp->alpm_dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

4630

intel_psr_init_dpcd(intel_dp, connector);

drivers/gpu/drm/i915/display/intel_dp.c

4632

intel_edp_set_sink_rates(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4633

intel_dp_set_max_sink_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4636

intel_dp_detect_dsc_caps(intel_dp, connector);

drivers/gpu/drm/i915/display/intel_dp.c

4642

intel_dp_has_sink_count(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4644

if (!intel_dp->attached_connector)

drivers/gpu/drm/i915/display/intel_dp.c

4647

return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,

drivers/gpu/drm/i915/display/intel_dp.c

4648

intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

4649

&intel_dp->desc);

drivers/gpu/drm/i915/display/intel_dp.c

4652

void intel_dp_update_sink_caps(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4654

intel_dp_set_sink_rates(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4655

intel_dp_set_max_sink_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4656

intel_dp_set_common_rates(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4660

intel_dp_get_dpcd(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4664

if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)

drivers/gpu/drm/i915/display/intel_dp.c

4671

if (!intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

4672

drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,

drivers/gpu/drm/i915/display/intel_dp.c

4673

drm_dp_is_branch(intel_dp->dpcd));

drivers/gpu/drm/i915/display/intel_dp.c

4675

intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);

drivers/gpu/drm/i915/display/intel_dp.c

4677

intel_dp->colorimetry_support =

drivers/gpu/drm/i915/display/intel_dp.c

4678

intel_dp_get_colorimetry_status(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4680

intel_dp_update_sink_caps(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4683

if (intel_dp_has_sink_count(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

4684

ret = drm_dp_read_sink_count(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp.c

4693

intel_dp->sink_count = ret;

drivers/gpu/drm/i915/display/intel_dp.c

4702

if (!intel_dp->sink_count)

drivers/gpu/drm/i915/display/intel_dp.c

4706

return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

4707

intel_dp->downstream_ports) == 0;

drivers/gpu/drm/i915/display/intel_dp.c

4721

intel_dp_mst_mode_choose(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

4724

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4729

if (!intel_dp_mst_source_support(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

4733

!(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B))

drivers/gpu/drm/i915/display/intel_dp.c

4740

intel_dp_mst_detect(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4742

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4743

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

4747

sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

4749

mst_detect = intel_dp_mst_mode_choose(intel_dp, sink_mst_mode);

drivers/gpu/drm/i915/display/intel_dp.c

4754

str_yes_no(intel_dp_mst_source_support(intel_dp)),

drivers/gpu/drm/i915/display/intel_dp.c

4763

intel_dp_mst_configure(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4765

if (!intel_dp_mst_source_support(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

4768

intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST;

drivers/gpu/drm/i915/display/intel_dp.c

4770

if (intel_dp->is_mst)

drivers/gpu/drm/i915/display/intel_dp.c

4771

intel_dp_mst_prepare_probe(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4773

drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, intel_dp->is_mst);

drivers/gpu/drm/i915/display/intel_dp.c

4776

intel_dp->mst_detect = DRM_DP_SST;

drivers/gpu/drm/i915/display/intel_dp.c

4780

intel_dp_mst_disconnect(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

4782

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4784

if (!intel_dp->is_mst)

drivers/gpu/drm/i915/display/intel_dp.c

4789

intel_dp->is_mst, intel_dp->mst.mgr.mst_state);

drivers/gpu/drm/i915/display/intel_dp.c

4790

intel_dp->is_mst = false;

drivers/gpu/drm/i915/display/intel_dp.c

4791

drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, intel_dp->is_mst);

drivers/gpu/drm/i915/display/intel_dp.c

4795

intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)

drivers/gpu/drm/i915/display/intel_dp.c

4797

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

4806

if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 3) != 3)

drivers/gpu/drm/i915/display/intel_dp.c

4810

return drm_dp_dpcd_readb(&intel_dp->aux, DP_LINK_SERVICE_IRQ_VECTOR_ESI0,

drivers/gpu/drm/i915/display/intel_dp.c

4814

return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;

drivers/gpu/drm/i915/display/intel_dp.c

4817

static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])

drivers/gpu/drm/i915/display/intel_dp.c

4822

if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,

drivers/gpu/drm/i915/display/intel_dp.c

494

int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

499

if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

501

drm_dp_tunnel_available_bw(intel_dp->tunnel));

drivers/gpu/drm/i915/display/intel_dp.c

506

bool intel_dp_has_joiner(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

508

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

509

struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

513

if (intel_dp->mso_link_count)

drivers/gpu/drm/i915/display/intel_dp.c

521

static int dg2_max_source_rate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

523

return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;

drivers/gpu/drm/i915/display/intel_dp.c

526

static int icl_max_source_rate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

528

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

5283

static bool intel_dp_link_ok(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

5286

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5287

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

5288

bool uhbr = intel_dp->link_rate >= 1000000;

drivers/gpu/drm/i915/display/intel_dp.c

5293

intel_dp->lane_count);

drivers/gpu/drm/i915/display/intel_dp.c

5295

ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);

drivers/gpu/drm/i915/display/intel_dp.c

530

if (intel_encoder_is_combo(encoder) && !intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

5300

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp.c

5310

intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)

drivers/gpu/drm/i915/display/intel_dp.c

5314

drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst.mgr, esi, ack, &handled);

drivers/gpu/drm/i915/display/intel_dp.c

5317

intel_hdcp_handle_cp_irq(intel_dp->attached_connector);

drivers/gpu/drm/i915/display/intel_dp.c

5322

static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5324

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5325

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

5329

if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,

drivers/gpu/drm/i915/display/intel_dp.c

5337

return intel_dp_link_ok(intel_dp, link_status);

drivers/gpu/drm/i915/display/intel_dp.c

5355

intel_dp_check_mst_status(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5357

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5358

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

536

static int ehl_max_source_rate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5367

if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {

drivers/gpu/drm/i915/display/intel_dp.c

5377

if (intel_dp_mst_active_streams(intel_dp) > 0 && link_ok &&

drivers/gpu/drm/i915/display/intel_dp.c

5379

if (!intel_dp_mst_link_status(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

538

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

5384

intel_dp_mst_hpd_irq(intel_dp, esi, ack);

drivers/gpu/drm/i915/display/intel_dp.c

5388

&intel_dp->aux))

drivers/gpu/drm/i915/display/intel_dp.c

5396

if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))

drivers/gpu/drm/i915/display/intel_dp.c

5400

drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp.c

5403

if (!link_ok || intel_dp->link.force_retrain)

drivers/gpu/drm/i915/display/intel_dp.c

5410

intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5415

is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp.c

5416

if (intel_dp->frl.is_trained && !is_active) {

drivers/gpu/drm/i915/display/intel_dp.c

5417

if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)

drivers/gpu/drm/i915/display/intel_dp.c

5421

if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)

drivers/gpu/drm/i915/display/intel_dp.c

5424

drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);

drivers/gpu/drm/i915/display/intel_dp.c

5426

intel_dp->frl.is_trained = false;

drivers/gpu/drm/i915/display/intel_dp.c

5429

intel_dp_check_frl_training(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5434

intel_dp_needs_link_retrain(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5438

if (!intel_dp->link.active)

drivers/gpu/drm/i915/display/intel_dp.c

544

static int mtl_max_source_rate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5449

if (intel_psr_enabled(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

5452

if (intel_dp->link.force_retrain)

drivers/gpu/drm/i915/display/intel_dp.c

5455

if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp.c

546

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5467

if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,

drivers/gpu/drm/i915/display/intel_dp.c

5468

intel_dp->lane_count))

drivers/gpu/drm/i915/display/intel_dp.c

547

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

5471

if (intel_dp->link.retrain_disabled)

drivers/gpu/drm/i915/display/intel_dp.c

5474

if (intel_dp->link.seq_train_failures)

drivers/gpu/drm/i915/display/intel_dp.c

5478

return !intel_dp_link_ok(intel_dp, link_status) &&

drivers/gpu/drm/i915/display/intel_dp.c

5479

!intel_psr_link_ok(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5482

bool intel_dp_has_connector(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

5485

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5493

encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

5499

encoder = &intel_dp->mst.stream_encoders[pipe]->base;

drivers/gpu/drm/i915/display/intel_dp.c

5522

int intel_dp_get_active_pipes(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

5526

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5540

if (!intel_dp_has_connector(intel_dp, conn_state))

drivers/gpu/drm/i915/display/intel_dp.c

5573

static bool intel_dp_is_connected(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5575

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

5578

intel_dp->is_mst;

drivers/gpu/drm/i915/display/intel_dp.c

5585

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

5589

if (!intel_dp_is_connected(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

559

static int vbt_max_link_rate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5597

if (!intel_dp_needs_link_retrain(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

5600

ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);

drivers/gpu/drm/i915/display/intel_dp.c

5607

if (!intel_dp_needs_link_retrain(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

561

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

5613

str_yes_no(intel_dp->link.force_retrain));

drivers/gpu/drm/i915/display/intel_dp.c

5619

intel_dp->link.force_retrain = false;

drivers/gpu/drm/i915/display/intel_dp.c

5639

void intel_dp_check_link_state(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5641

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5644

if (!intel_dp_is_connected(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

5647

if (!intel_dp_needs_link_retrain(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

5653

static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5655

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5658

if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)

drivers/gpu/drm/i915/display/intel_dp.c

566

if (intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

5661

if (drm_dp_dpcd_readb(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp.c

5665

drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);

drivers/gpu/drm/i915/display/intel_dp.c

5668

intel_dp_test_request(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

567

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

5671

intel_hdcp_handle_cp_irq(intel_dp->attached_connector);

drivers/gpu/drm/i915/display/intel_dp.c

5677

static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5679

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5683

if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)

drivers/gpu/drm/i915/display/intel_dp.c

5686

if (drm_dp_dpcd_readb(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp.c

5692

&intel_dp->aux))

drivers/gpu/drm/i915/display/intel_dp.c

5695

if (drm_dp_dpcd_writeb(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp.c

5700

intel_dp_handle_hdmi_link_status_change(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5719

intel_dp_short_pulse(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5721

u8 old_sink_count = intel_dp->sink_count;

drivers/gpu/drm/i915/display/intel_dp.c

5725

intel_dp_test_reset(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5733

ret = intel_dp_get_dpcd(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5735

if ((old_sink_count != intel_dp->sink_count) || !ret) {

drivers/gpu/drm/i915/display/intel_dp.c

5740

intel_dp_check_device_service_irq(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5741

reprobe_needed = intel_dp_check_link_service_irq(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5744

drm_dp_cec_irq(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp.c

5746

intel_dp_check_link_state(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5748

intel_psr_short_pulse(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5750

if (intel_alpm_get_error(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

5751

intel_alpm_disable(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5752

intel_dp->alpm.sink_alpm_error = true;

drivers/gpu/drm/i915/display/intel_dp.c

5755

if (intel_dp_test_short_pulse(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

5763

intel_dp_detect_dpcd(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5765

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5766

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5767

u8 *dpcd = intel_dp->dpcd;

drivers/gpu/drm/i915/display/intel_dp.c

5770

if (drm_WARN_ON(display->drm, intel_dp_is_edp(intel_dp)))

drivers/gpu/drm/i915/display/intel_dp.c

5775

if (!intel_dp_get_dpcd(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

5778

intel_dp->mst_detect = intel_dp_mst_detect(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5785

if (intel_dp_has_sink_count(intel_dp) &&

drivers/gpu/drm/i915/display/intel_dp.c

5786

intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {

drivers/gpu/drm/i915/display/intel_dp.c

5787

return intel_dp->sink_count ?

drivers/gpu/drm/i915/display/intel_dp.c

5791

if (intel_dp->mst_detect == DRM_DP_MST)

drivers/gpu/drm/i915/display/intel_dp.c

5795

if (drm_probe_ddc(&intel_dp->aux.ddc))

drivers/gpu/drm/i915/display/intel_dp.c

5799

if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {

drivers/gpu/drm/i915/display/intel_dp.c

580

intel_dp_set_source_rates(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5800

type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;

drivers/gpu/drm/i915/display/intel_dp.c

5805

type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &

drivers/gpu/drm/i915/display/intel_dp.c

5818

edp_detect(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5881

intel_dp_get_edid(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5883

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

5895

return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);

drivers/gpu/drm/i915/display/intel_dp.c

5899

intel_dp_update_dfp(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

5902

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5903

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

5905

intel_dp->dfp.max_bpc =

drivers/gpu/drm/i915/display/intel_dp.c

5906

drm_dp_downstream_max_bpc(intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

5907

intel_dp->downstream_ports, drm_edid);

drivers/gpu/drm/i915/display/intel_dp.c

5909

intel_dp->dfp.max_dotclock =

drivers/gpu/drm/i915/display/intel_dp.c

5910

drm_dp_downstream_max_dotclock(intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

5911

intel_dp->downstream_ports);

drivers/gpu/drm/i915/display/intel_dp.c

5913

intel_dp->dfp.min_tmds_clock =

drivers/gpu/drm/i915/display/intel_dp.c

5914

drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

5915

intel_dp->downstream_ports,

drivers/gpu/drm/i915/display/intel_dp.c

5917

intel_dp->dfp.max_tmds_clock =

drivers/gpu/drm/i915/display/intel_dp.c

5918

drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

5919

intel_dp->downstream_ports,

drivers/gpu/drm/i915/display/intel_dp.c

5922

intel_dp->dfp.pcon_max_frl_bw =

drivers/gpu/drm/i915/display/intel_dp.c

5923

drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

5924

intel_dp->downstream_ports);

drivers/gpu/drm/i915/display/intel_dp.c

5929

intel_dp->dfp.max_bpc,

drivers/gpu/drm/i915/display/intel_dp.c

5930

intel_dp->dfp.max_dotclock,

drivers/gpu/drm/i915/display/intel_dp.c

5931

intel_dp->dfp.min_tmds_clock,

drivers/gpu/drm/i915/display/intel_dp.c

5932

intel_dp->dfp.max_tmds_clock,

drivers/gpu/drm/i915/display/intel_dp.c

5933

intel_dp->dfp.pcon_max_frl_bw);

drivers/gpu/drm/i915/display/intel_dp.c

5935

intel_dp_get_pcon_dsc_cap(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5939

intel_dp_can_ycbcr420(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5941

if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) &&

drivers/gpu/drm/i915/display/intel_dp.c

5942

(!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))

drivers/gpu/drm/i915/display/intel_dp.c

5945

if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&

drivers/gpu/drm/i915/display/intel_dp.c

5946

dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))

drivers/gpu/drm/i915/display/intel_dp.c

5949

if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&

drivers/gpu/drm/i915/display/intel_dp.c

5950

dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))

drivers/gpu/drm/i915/display/intel_dp.c

5957

intel_dp_update_420(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5959

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5960

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

5962

intel_dp->dfp.ycbcr420_passthrough =

drivers/gpu/drm/i915/display/intel_dp.c

5963

drm_dp_downstream_420_passthrough(intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

5964

intel_dp->downstream_ports);

drivers/gpu/drm/i915/display/intel_dp.c

5966

intel_dp->dfp.ycbcr_444_to_420 =

drivers/gpu/drm/i915/display/intel_dp.c

5967

intel_lspcon_active(dp_to_dig_port(intel_dp)) ||

drivers/gpu/drm/i915/display/intel_dp.c

5968

drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

5969

intel_dp->downstream_ports);

drivers/gpu/drm/i915/display/intel_dp.c

5970

intel_dp->dfp.rgb_to_ycbcr =

drivers/gpu/drm/i915/display/intel_dp.c

5971

drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

5972

intel_dp->downstream_ports,

drivers/gpu/drm/i915/display/intel_dp.c

5975

connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5980

str_yes_no(intel_dp->dfp.rgb_to_ycbcr),

drivers/gpu/drm/i915/display/intel_dp.c

5982

str_yes_no(intel_dp->dfp.ycbcr_444_to_420));

drivers/gpu/drm/i915/display/intel_dp.c

5986

intel_dp_set_edid(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

5988

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5989

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

5993

intel_dp_unset_edid(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

5994

drm_edid = intel_dp_get_edid(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6005

intel_dp_update_dfp(intel_dp, drm_edid);

drivers/gpu/drm/i915/display/intel_dp.c

6006

intel_dp_update_420(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6008

drm_dp_cec_attach(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp.c

6013

intel_dp_unset_edid(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

6015

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

6017

drm_dp_cec_unset_edid(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp.c

6021

intel_dp->dfp.max_bpc = 0;

drivers/gpu/drm/i915/display/intel_dp.c

6022

intel_dp->dfp.max_dotclock = 0;

drivers/gpu/drm/i915/display/intel_dp.c

6023

intel_dp->dfp.min_tmds_clock = 0;

drivers/gpu/drm/i915/display/intel_dp.c

6024

intel_dp->dfp.max_tmds_clock = 0;

drivers/gpu/drm/i915/display/intel_dp.c

6026

intel_dp->dfp.pcon_max_frl_bw = 0;

drivers/gpu/drm/i915/display/intel_dp.c

6028

intel_dp->dfp.ycbcr_444_to_420 = false;

drivers/gpu/drm/i915/display/intel_dp.c

6036

intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

6038

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6040

intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&

drivers/gpu/drm/i915/display/intel_dp.c

6041

drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

6044

static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool force_on_external)

drivers/gpu/drm/i915/display/intel_dp.c

6046

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

6048

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6054

if (intel_dp->is_mst)

drivers/gpu/drm/i915/display/intel_dp.c

6060

void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external)

drivers/gpu/drm/i915/display/intel_dp.c

6062

drm_dp_dpcd_set_probe(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp.c

6063

intel_dp_needs_dpcd_probe(intel_dp, force_on_external));

drivers/gpu/drm/i915/display/intel_dp.c

607

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6073

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

6074

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6092

intel_pps_vdd_on(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6095

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6096

status = edp_detect(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6098

status = intel_dp_detect_dpcd(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6103

!intel_dp_mst_verify_dpcd_state(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6115

intel_dp_test_reset(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6125

intel_dp->psr.sink_panel_replay_support = false;

drivers/gpu/drm/i915/display/intel_dp.c

613

intel_dp->source_rates || intel_dp->num_source_rates);

drivers/gpu/drm/i915/display/intel_dp.c

6131

intel_dp_mst_disconnect(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6133

intel_dp_tunnel_disconnect(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6138

intel_dp_init_source_oui(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6140

ret = intel_dp_tunnel_detect(intel_dp, ctx);

drivers/gpu/drm/i915/display/intel_dp.c

6150

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6151

intel_psr_init_dpcd(intel_dp, connector);

drivers/gpu/drm/i915/display/intel_dp.c

6153

intel_dp_detect_dsc_caps(intel_dp, connector);

drivers/gpu/drm/i915/display/intel_dp.c

6155

intel_dp_detect_sdp_caps(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6157

if (intel_dp->reset_link_params) {

drivers/gpu/drm/i915/display/intel_dp.c

6158

intel_dp_reset_link_params(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6159

intel_dp->reset_link_params = false;

drivers/gpu/drm/i915/display/intel_dp.c

6162

intel_dp_mst_configure(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6164

intel_dp_print_rates(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6166

if (intel_dp->is_mst) {

drivers/gpu/drm/i915/display/intel_dp.c

6184

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6185

intel_dp_check_link_state(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6192

intel_dp->aux.i2c_nack_count = 0;

drivers/gpu/drm/i915/display/intel_dp.c

6193

intel_dp->aux.i2c_defer_count = 0;

drivers/gpu/drm/i915/display/intel_dp.c

6195

intel_dp_set_edid(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6196

if (intel_dp_is_edp(intel_dp) || connector->detect_edid)

drivers/gpu/drm/i915/display/intel_dp.c

6199

intel_dp_check_device_service_irq(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6202

if (status != connector_status_connected && !intel_dp->is_mst)

drivers/gpu/drm/i915/display/intel_dp.c

6203

intel_dp_unset_edid(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6205

intel_dp_dpcd_set_probe(intel_dp, false);

drivers/gpu/drm/i915/display/intel_dp.c

6207

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6210

intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

6211

intel_dp->downstream_ports);

drivers/gpu/drm/i915/display/intel_dp.c

6213

intel_pps_vdd_off(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6223

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

623

max_rate = mtl_max_source_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6231

intel_dp_unset_edid(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6236

intel_dp_set_edid(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6238

intel_dp_dpcd_set_probe(intel_dp, false);

drivers/gpu/drm/i915/display/intel_dp.c

6245

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

6252

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6262

intel_dp->dpcd,

drivers/gpu/drm/i915/display/intel_dp.c

6263

intel_dp->downstream_ports);

drivers/gpu/drm/i915/display/intel_dp.c

6278

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

6279

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

628

max_rate = dg2_max_source_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6287

intel_dp->aux.name, connector->base.kdev->kobj.name);

drivers/gpu/drm/i915/display/intel_dp.c

6289

intel_dp->aux.dev = connector->base.kdev;

drivers/gpu/drm/i915/display/intel_dp.c

6290

ret = drm_dp_aux_register(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp.c

6292

drm_dp_cec_register_connector(&intel_dp->aux, &connector->base);

drivers/gpu/drm/i915/display/intel_dp.c

6313

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp.c

6315

drm_dp_cec_unregister_connector(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp.c

6316

drm_dp_aux_unregister(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp.c

633

max_rate = ehl_max_source_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6338

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_dp.c

6344

intel_dp_tunnel_destroy(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6346

intel_pps_vdd_off_sync(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

635

max_rate = icl_max_source_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6352

intel_pps_wait_power_cycle(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6354

intel_dp_aux_fini(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6359

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

6361

intel_pps_vdd_off_sync(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6363

intel_dp_tunnel_suspend(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6368

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

6370

intel_pps_wait_power_cycle(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6490

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp.c

6497

if (intel_dp_mst_source_support(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

6498

ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp.c

6507

intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

651

vbt_max_rate = vbt_max_link_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6577

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_dp.c

6583

!intel_pps_have_panel_power_or_vdd(intel_dp))) {

drivers/gpu/drm/i915/display/intel_dp.c

660

intel_dp->source_rates = source_rates;

drivers/gpu/drm/i915/display/intel_dp.c

661

intel_dp->num_source_rates = size;

drivers/gpu/drm/i915/display/intel_dp.c

6612

intel_dp_dpcd_set_probe(intel_dp, true);

drivers/gpu/drm/i915/display/intel_dp.c

6614

intel_dp_read_dprx_caps(intel_dp, dpcd);

drivers/gpu/drm/i915/display/intel_dp.c

6616

intel_dp->reset_link_params = true;

drivers/gpu/drm/i915/display/intel_dp.c

6617

intel_dp_invalidate_source_oui(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6622

if (intel_dp->is_mst) {

drivers/gpu/drm/i915/display/intel_dp.c

6623

if (!intel_dp_check_mst_status(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6625

} else if (!intel_dp_short_pulse(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

6680

intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *_connector)

drivers/gpu/drm/i915/display/intel_dp.c

6683

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6684

enum port port = dp_to_dig_port(intel_dp)->base.port;

drivers/gpu/drm/i915/display/intel_dp.c

6686

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6699

if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {

drivers/gpu/drm/i915/display/intel_dp.c

6706

if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))

drivers/gpu/drm/i915/display/intel_dp.c

6714

intel_edp_add_properties(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

6716

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6717

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

6729

static void intel_edp_backlight_setup(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

6732

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6736

pipe = vlv_pps_backlight_initial_pipe(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6741

static bool intel_edp_init_connector(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

6744

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6746

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp.c

6750

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

6771

if (!intel_pps_init(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

6792

intel_alpm_init(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6795

has_dpcd = intel_edp_init_dpcd(intel_dp, connector);

drivers/gpu/drm/i915/display/intel_dp.c

6834

if (DISPLAY_VER(display) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&

drivers/gpu/drm/i915/display/intel_dp.c

6835

(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==

drivers/gpu/drm/i915/display/intel_dp.c

6871

intel_edp_mso_init(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6892

intel_edp_backlight_setup(intel_dp, connector);

drivers/gpu/drm/i915/display/intel_dp.c

6894

intel_edp_add_properties(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6896

intel_pps_init_late(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6901

intel_pps_vdd_off_sync(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6912

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_dp.c

6924

intel_dp->reset_link_params = true;

drivers/gpu/drm/i915/display/intel_dp.c

6927

intel_dp->DP = intel_de_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/intel_dp.c

6928

intel_dp->attached_connector = connector;

drivers/gpu/drm/i915/display/intel_dp.c

6949

intel_dp_set_default_sink_rates(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6950

intel_dp_set_default_max_sink_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6953

vlv_pps_pipe_init(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6955

intel_dp_aux_init(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6956

connector->dp.dsc_decompression_aux = &intel_dp->aux;

drivers/gpu/drm/i915/display/intel_dp.c

6964

type, &intel_dp->aux.ddc);

drivers/gpu/drm/i915/display/intel_dp.c

6982

if (!intel_edp_init_connector(intel_dp, connector)) {

drivers/gpu/drm/i915/display/intel_dp.c

6983

intel_dp_aux_fini(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6987

intel_dp_set_source_rates(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6988

intel_dp_set_common_rates(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

6989

intel_dp_reset_link_params(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

699

static int intel_dp_link_config_rate(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

6994

intel_dp_add_properties(intel_dp, &connector->base);

drivers/gpu/drm/i915/display/intel_dp.c

6996

if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_dp.c

7003

intel_dp->frl.is_trained = false;

drivers/gpu/drm/i915/display/intel_dp.c

7004

intel_dp->frl.trained_rate_gbps = 0;

drivers/gpu/drm/i915/display/intel_dp.c

7006

intel_psr_init(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

702

return intel_dp_common_rate(intel_dp, lc->link_rate_idx);

drivers/gpu/drm/i915/display/intel_dp.c

7025

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_dp.c

7030

intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

7032

if (!intel_dp_mst_source_support(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

7035

if (intel_dp->is_mst)

drivers/gpu/drm/i915/display/intel_dp.c

7036

drm_dp_mst_topology_mgr_suspend(&intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp.c

7048

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_dp.c

7054

intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

7056

if (!intel_dp_mst_source_support(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.c

7059

ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst.mgr, true);

drivers/gpu/drm/i915/display/intel_dp.c

7061

intel_dp->is_mst = false;

drivers/gpu/drm/i915/display/intel_dp.c

7062

drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, false);

drivers/gpu/drm/i915/display/intel_dp.c

7087

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp.c

7090

intel_psr_compute_config_late(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp.c

710

static int intel_dp_link_config_bw(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.c

713

return drm_dp_max_dprx_data_rate(intel_dp_link_config_rate(intel_dp, lc),

drivers/gpu/drm/i915/display/intel_dp.c

719

struct intel_dp *intel_dp = (struct intel_dp *)p; /* remove const */

drivers/gpu/drm/i915/display/intel_dp.c

722

int bw_a = intel_dp_link_config_bw(intel_dp, lc_a);

drivers/gpu/drm/i915/display/intel_dp.c

723

int bw_b = intel_dp_link_config_bw(intel_dp, lc_b);

drivers/gpu/drm/i915/display/intel_dp.c

728

return intel_dp_link_config_rate(intel_dp, lc_a) -

drivers/gpu/drm/i915/display/intel_dp.c

729

intel_dp_link_config_rate(intel_dp, lc_b);

drivers/gpu/drm/i915/display/intel_dp.c

732

static void intel_dp_link_config_init(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

734

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

740

if (drm_WARN_ON(display->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp))))

drivers/gpu/drm/i915/display/intel_dp.c

743

num_common_lane_configs = ilog2(intel_dp_max_common_lane_count(intel_dp)) + 1;

drivers/gpu/drm/i915/display/intel_dp.c

745

if (drm_WARN_ON(display->drm, intel_dp->num_common_rates * num_common_lane_configs >

drivers/gpu/drm/i915/display/intel_dp.c

746

ARRAY_SIZE(intel_dp->link.configs)))

drivers/gpu/drm/i915/display/intel_dp.c

749

intel_dp->link.num_configs = intel_dp->num_common_rates * num_common_lane_configs;

drivers/gpu/drm/i915/display/intel_dp.c

751

lc = &intel_dp->link.configs[0];

drivers/gpu/drm/i915/display/intel_dp.c

752

for (i = 0; i < intel_dp->num_common_rates; i++) {

drivers/gpu/drm/i915/display/intel_dp.c

761

sort_r(intel_dp->link.configs, intel_dp->link.num_configs,

drivers/gpu/drm/i915/display/intel_dp.c

762

sizeof(intel_dp->link.configs[0]),

drivers/gpu/drm/i915/display/intel_dp.c

764

intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

767

void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count)

drivers/gpu/drm/i915/display/intel_dp.c

769

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

772

if (drm_WARN_ON(display->drm, idx < 0 || idx >= intel_dp->link.num_configs))

drivers/gpu/drm/i915/display/intel_dp.c

775

lc = &intel_dp->link.configs[idx];

drivers/gpu/drm/i915/display/intel_dp.c

777

*link_rate = intel_dp_link_config_rate(intel_dp, lc);

drivers/gpu/drm/i915/display/intel_dp.c

781

int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count)

drivers/gpu/drm/i915/display/intel_dp.c

783

int link_rate_idx = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates,

drivers/gpu/drm/i915/display/intel_dp.c

788

for (i = 0; i < intel_dp->link.num_configs; i++) {

drivers/gpu/drm/i915/display/intel_dp.c

789

const struct intel_dp_link_config *lc = &intel_dp->link.configs[i];

drivers/gpu/drm/i915/display/intel_dp.c

799

static void intel_dp_set_common_rates(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp.c

801

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

804

!intel_dp->num_source_rates || !intel_dp->num_sink_rates);

drivers/gpu/drm/i915/display/intel_dp.c

806

intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,

drivers/gpu/drm/i915/display/intel_dp.c

807

intel_dp->num_source_rates,

drivers/gpu/drm/i915/display/intel_dp.c

808

intel_dp->sink_rates,

drivers/gpu/drm/i915/display/intel_dp.c

809

intel_dp->num_sink_rates,

drivers/gpu/drm/i915/display/intel_dp.c

810

intel_dp->common_rates);

drivers/gpu/drm/i915/display/intel_dp.c

813

if (drm_WARN_ON(display->drm, intel_dp->num_common_rates == 0)) {

drivers/gpu/drm/i915/display/intel_dp.c

814

intel_dp->common_rates[0] = 162000;

drivers/gpu/drm/i915/display/intel_dp.c

815

intel_dp->num_common_rates = 1;

drivers/gpu/drm/i915/display/intel_dp.c

818

intel_dp_link_config_init(intel_dp);

drivers/gpu/drm/i915/display/intel_dp.c

821

bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,

drivers/gpu/drm/i915/display/intel_dp.c

830

link_rate > intel_dp->link.max_rate)

drivers/gpu/drm/i915/display/intel_dp.c

834

lane_count > intel_dp_max_lane_count(intel_dp))

drivers/gpu/drm/i915/display/intel_dp.h

102

int intel_dp_max_link_rate(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

103

int intel_dp_max_lane_count(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

105

int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);

drivers/gpu/drm/i915/display/intel_dp.h

106

int intel_dp_max_common_rate(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

107

int intel_dp_max_common_lane_count(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

108

int intel_dp_common_rate(struct intel_dp *intel_dp, int index);

drivers/gpu/drm/i915/display/intel_dp.h

110

int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count);

drivers/gpu/drm/i915/display/intel_dp.h

111

void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count);

drivers/gpu/drm/i915/display/intel_dp.h

112

void intel_dp_update_sink_caps(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

113

void intel_dp_reset_link_params(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

115

void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,

drivers/gpu/drm/i915/display/intel_dp.h

127

int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

131

bool intel_dp_has_joiner(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

152

bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16);

drivers/gpu/drm/i915/display/intel_dp.h

156

int intel_dp_num_joined_pipes(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

165

bool intel_dp_supports_fec(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

171

bool intel_dp_supports_fec(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

175

bool intel_dp_supports_dsc(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

189

void intel_dp_check_frl_training(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

190

void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

193

void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

194

void intel_dp_wait_source_oui(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

198

bool intel_dp_compute_config_limits(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

210

bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,

drivers/gpu/drm/i915/display/intel_dp.h

212

bool intel_dp_has_connector(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

221

void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external);

drivers/gpu/drm/i915/display/intel_dp.h

24

struct intel_dp;

drivers/gpu/drm/i915/display/intel_dp.h

53

void intel_dp_set_link_params(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

55

int intel_dp_get_active_pipes(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

60

void intel_dp_check_link_state(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

61

void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode);

drivers/gpu/drm/i915/display/intel_dp.h

62

void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

78

int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp.h

86

bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp.h

87

bool intel_dp_is_edp(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

114

static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp_aux.c

116

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

117

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

128

return ilk_get_aux_clock_divider(intel_dp, index);

drivers/gpu/drm/i915/display/intel_dp_aux.c

131

static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp_aux.c

149

int intel_dp_aux_fw_sync_len(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_aux.c

162

if (intel_has_dpcd_quirk(intel_dp, QUIRK_FW_SYNC_LEN))

drivers/gpu/drm/i915/display/intel_dp_aux.c

178

static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_aux.c

182

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

202

static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_aux.c

206

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

207

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

222

DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(intel_dp_aux_fw_sync_len(intel_dp)) |

drivers/gpu/drm/i915/display/intel_dp_aux.c

239

intel_dp_aux_xfer(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_aux.c

244

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

245

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

257

ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

259

ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);

drivers/gpu/drm/i915/display/intel_dp_aux.c

267

if (!intel_dp_is_edp(intel_dp) &&

drivers/gpu/drm/i915/display/intel_dp_aux.c

287

if (intel_dp_is_edp(intel_dp) ||

drivers/gpu/drm/i915/display/intel_dp_aux.c

289

pps_wakeref = intel_pps_lock(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

297

vdd = intel_pps_vdd_on_unlocked(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

304

cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);

drivers/gpu/drm/i915/display/intel_dp_aux.c

306

intel_pps_check_power_unlocked(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

326

if (status != intel_dp->aux_busy_last_status) {

drivers/gpu/drm/i915/display/intel_dp_aux.c

329

intel_dp->aux.name, status);

drivers/gpu/drm/i915/display/intel_dp_aux.c

330

intel_dp->aux_busy_last_status = status;

drivers/gpu/drm/i915/display/intel_dp_aux.c

343

while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {

drivers/gpu/drm/i915/display/intel_dp_aux.c

344

u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,

drivers/gpu/drm/i915/display/intel_dp_aux.c

361

status = intel_dp_aux_wait_done(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

389

intel_dp->aux.name, status);

drivers/gpu/drm/i915/display/intel_dp_aux.c

401

intel_dp->aux.name, status);

drivers/gpu/drm/i915/display/intel_dp_aux.c

412

intel_dp->aux.name, status);

drivers/gpu/drm/i915/display/intel_dp_aux.c

428

intel_dp->aux.name, recv_bytes);

drivers/gpu/drm/i915/display/intel_dp_aux.c

442

cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);

drivers/gpu/drm/i915/display/intel_dp_aux.c

445

intel_pps_vdd_off_unlocked(intel_dp, false);

drivers/gpu/drm/i915/display/intel_dp_aux.c

448

intel_pps_unlock(intel_dp, pps_wakeref);

drivers/gpu/drm/i915/display/intel_dp_aux.c

487

struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);

drivers/gpu/drm/i915/display/intel_dp_aux.c

488

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

511

ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,

drivers/gpu/drm/i915/display/intel_dp_aux.c

534

ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,

drivers/gpu/drm/i915/display/intel_dp_aux.c

557

static i915_reg_t vlv_aux_ctl_reg(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_aux.c

559

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

573

static i915_reg_t vlv_aux_data_reg(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp_aux.c

575

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

58

intel_dp_aux_wait_done(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_aux.c

589

static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_aux.c

591

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

60

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

605

static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp_aux.c

607

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

61

i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

621

static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_aux.c

623

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

639

static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp_aux.c

641

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

657

static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_aux.c

659

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

676

static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp_aux.c

678

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

695

static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_aux.c

697

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

717

static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp_aux.c

719

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

73

intel_dp->aux.name, timeout_ms, status);

drivers/gpu/drm/i915/display/intel_dp_aux.c

739

static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_aux.c

741

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

742

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

759

static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp_aux.c

761

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

762

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

779

void intel_dp_aux_fini(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_aux.c

781

if (cpu_latency_qos_request_active(&intel_dp->pm_qos))

drivers/gpu/drm/i915/display/intel_dp_aux.c

782

cpu_latency_qos_remove_request(&intel_dp->pm_qos);

drivers/gpu/drm/i915/display/intel_dp_aux.c

784

kfree(intel_dp->aux.name);

drivers/gpu/drm/i915/display/intel_dp_aux.c

787

void intel_dp_aux_init(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_aux.c

789

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

79

static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp_aux.c

790

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

796

intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

797

intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

799

intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

800

intel_dp->aux_ch_data_reg = tgl_aux_data_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

802

intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

803

intel_dp->aux_ch_data_reg = skl_aux_data_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

805

intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

806

intel_dp->aux_ch_data_reg = ilk_aux_data_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

808

intel_dp->aux_ch_ctl_reg = vlv_aux_ctl_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

809

intel_dp->aux_ch_data_reg = vlv_aux_data_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

81

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

811

intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

812

intel_dp->aux_ch_data_reg = g4x_aux_data_reg;

drivers/gpu/drm/i915/display/intel_dp_aux.c

816

intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;

drivers/gpu/drm/i915/display/intel_dp_aux.c

818

intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;

drivers/gpu/drm/i915/display/intel_dp_aux.c

820

intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;

drivers/gpu/drm/i915/display/intel_dp_aux.c

822

intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;

drivers/gpu/drm/i915/display/intel_dp_aux.c

825

intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;

drivers/gpu/drm/i915/display/intel_dp_aux.c

827

intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;

drivers/gpu/drm/i915/display/intel_dp_aux.c

829

intel_dp->aux.drm_dev = display->drm;

drivers/gpu/drm/i915/display/intel_dp_aux.c

830

drm_dp_aux_init(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp_aux.c

833

intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %s/%s",

drivers/gpu/drm/i915/display/intel_dp_aux.c

837

intel_dp->aux.transfer = intel_dp_aux_transfer;

drivers/gpu/drm/i915/display/intel_dp_aux.c

838

cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);

drivers/gpu/drm/i915/display/intel_dp_aux.c

840

intel_dp_dpcd_set_probe(intel_dp, true);

drivers/gpu/drm/i915/display/intel_dp_aux.c

93

static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)

drivers/gpu/drm/i915/display/intel_dp_aux.c

95

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.c

96

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.h

13

struct intel_dp;

drivers/gpu/drm/i915/display/intel_dp_aux.h

16

void intel_dp_aux_fini(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.h

17

void intel_dp_aux_init(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux.h

23

int intel_dp_aux_fw_sync_len(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

115

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

116

struct drm_dp_aux *aux = &intel_dp->aux;

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

121

intel_dp_wait_source_oui(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

178

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

182

if (drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &tmp) != 1) {

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

200

if (drm_dp_dpcd_read(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

216

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

222

if (drm_dp_dpcd_write(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

249

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

261

ret = drm_dp_dpcd_write(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

309

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

314

intel_dp_wait_source_oui(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

316

ret = drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &old_ctrl);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

341

drm_dp_dpcd_writeb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, ctrl) != 1)

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

376

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

385

ret = drm_dp_dpcd_write(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

442

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

449

ret = drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_PANEL_TARGET_LUMINANCE_VALUE, buf,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

452

drm_err(intel_dp->aux.drm_dev,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

470

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

478

drm_edp_backlight_set_level(&intel_dp->aux, &panel->backlight.edp.vesa.info, level);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

487

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

501

drm_edp_backlight_enable(&intel_dp->aux, &panel->backlight.edp.vesa.info, level);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

509

struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

511

drm_edp_backlight_disable(&intel_dp->aux, &panel->backlight.edp.vesa.info);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

523

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

529

ret = drm_edp_backlight_init(&intel_dp->aux, &panel->backlight.edp.vesa.info,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

532

intel_dp->edp_dpcd, &current_level, &current_mode,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

604

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

607

if ((intel_dp->edp_dpcd[3] & DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE) &&

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

608

(intel_dp->edp_dpcd[3] & DP_EDP_SMOOTH_BRIGHTNESS_CAPABLE)) {

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

616

if (drm_edp_backlight_supported(intel_dp->edp_dpcd)) {

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

644

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

682

if (intel_dp->edp_dpcd[0] >= DP_EDP_15)

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

699

intel_dp->edp_dpcd[0] <= DP_EDP_14b) {

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

403

struct intel_dp *dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

44

struct intel_dp *dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

521

struct intel_dp *dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

895

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

903

else if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1008

if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

101

ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1012

intel_dp_dump_link_status(intel_dp, dp_phy, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1013

lt_err(intel_dp, dp_phy, "Failed clock recovery %d times, giving up!\n",

drivers/gpu/drm/i915/display/intel_dp_link_training.c

102

intel_dp->lttpr_common_caps);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1025

intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1035

delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1036

intel_dp->dpcd, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1039

training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1045

if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1047

lt_err(intel_dp, dp_phy, "Failed to start channel equalization\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1054

if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1056

lt_err(intel_dp, dp_phy, "Failed to get link status\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

106

lt_dbg(intel_dp, DP_PHY_DPRX, "LTTPR common capabilities: %*ph\n",

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1063

intel_dp_dump_link_status(intel_dp, dp_phy, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1064

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

107

(int)sizeof(intel_dp->lttpr_common_caps),

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1072

lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP Training successful\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1077

intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1079

if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

108

intel_dp->lttpr_common_caps);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1080

lt_err(intel_dp, dp_phy, "Failed to update link training\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1087

intel_dp_dump_link_status(intel_dp, dp_phy, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1088

lt_dbg(intel_dp, dp_phy, "Channel equalization failed 5 times\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1094

static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1097

int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1100

return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1104

intel_dp_128b132b_intra_hop(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

111

if (intel_dp->lttpr_common_caps[0] < 0x14)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1110

ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_STATUS, &sink_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1112

lt_dbg(intel_dp, DP_PHY_DPRX, "Failed to read sink status\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1135

void intel_dp_stop_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1138

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1139

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1142

intel_dp->link.active = true;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1144

intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1148

ret = poll_timeout_us(ret = intel_dp_128b132b_intra_hop(intel_dp, crtc_state),

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1152

lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1158

intel_dp->link.seq_train_failures < MAX_SEQ_TRAIN_FAILURES) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1159

int delay_ms = intel_dp->link.seq_train_failures ? 0 : 2000;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1166

intel_dp_link_train_phy(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

117

intel_dp_reset_lttpr_common_caps(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1172

if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1175

if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1181

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1189

static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1195

intel_panel_preferred_fixed_mode(intel_dp->attached_connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1201

max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1208

static bool reduce_link_params_in_bw_order(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1216

i = intel_dp_link_config_index(intel_dp, crtc_state->port_clock, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1218

intel_dp_link_config_get(intel_dp, i, &link_rate, &lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

122

intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1220

if ((intel_dp->link.force_rate &&

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1221

intel_dp->link.force_rate != link_rate) ||

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1222

(intel_dp->link.force_lane_count &&

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1223

intel_dp->link.force_lane_count != lane_count))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1238

static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1243

if (intel_dp->link.force_rate)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1246

rate_index = intel_dp_rate_index(intel_dp->common_rates,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1247

intel_dp->num_common_rates,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1253

new_rate = intel_dp_common_rate(intel_dp, rate_index - 1);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1262

static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1264

if (intel_dp->link.force_lane_count)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

127

intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE -

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1273

static bool reduce_link_params_in_rate_lane_order(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1281

link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1283

lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1284

link_rate = intel_dp_max_common_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1296

static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1301

return reduce_link_params_in_bw_order(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1304

return reduce_link_params_in_rate_lane_order(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1308

static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1314

if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1315

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1317

intel_dp->use_max_params = true;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1321

if (!reduce_link_params(intel_dp, crtc_state, &new_link_rate, &new_lane_count))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1324

if (intel_dp_is_edp(intel_dp) &&

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1325

!intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate, new_lane_count)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1326

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

133

bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1331

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1336

intel_dp->link.max_rate = new_link_rate;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1337

intel_dp->link.max_lane_count = new_lane_count;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1343

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1346

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1348

if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1349

lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

135

return intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE -

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1353

if (intel_dp->hobl_active) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1354

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1356

intel_dp->hobl_failed = true;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1357

} else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1369

intel_dp_link_train_all_phys(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1379

ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1380

intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1387

ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1389

intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1390

intel_dp->set_idle_link_train(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1399

intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1414

if (!intel_dp_reset_link_train(intel_dp, crtc_state, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1416

lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS1\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1420

delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1423

if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1424

lt_err(intel_dp, DP_PHY_DPRX, "Failed to read TX FFE presets\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1429

intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1430

if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1431

lt_err(intel_dp, DP_PHY_DPRX, "Failed to set initial TX FFE settings\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1436

if (!intel_dp_set_link_train(intel_dp, crtc_state, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1438

lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1448

if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1449

lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1454

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1455

lt_err(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1461

lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq done\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1466

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1467

lt_err(intel_dp, DP_PHY_DPRX, "Lane channel eq timeout\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1478

delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

148

static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1480

intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1483

if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1484

lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1490

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1491

lt_err(intel_dp, DP_PHY_DPRX, "Max loop count reached\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1499

if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1500

lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1505

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1506

lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1511

lt_dbg(intel_dp, DP_PHY_DPRX, "Interlane align done\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1516

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1517

lt_err(intel_dp, DP_PHY_DPRX, "Interlane align timeout\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

153

if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1531

intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1538

if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1540

lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2 CDS\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1555

if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1556

lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

156

lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1563

lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align done\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1568

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1569

lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1574

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1575

lt_err(intel_dp, DP_PHY_DPRX, "CDS timeout\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1587

intel_dp_128b132b_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1594

ret = poll_timeout_us(ret = intel_dp_128b132b_intra_hop(intel_dp, crtc_state),

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1598

lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1602

if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) &&

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1603

intel_dp_128b132b_lane_cds(intel_dp, crtc_state, lttpr_count))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1606

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1621

intel_dp_program_link_training_pattern(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1624

intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1641

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1645

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1657

lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1663

intel_dp_prepare_link_train(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1666

passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1668

passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1670

if (intel_dp->link.force_train_failure) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1671

intel_dp->link.force_train_failure--;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1672

lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training failure\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1674

intel_dp->link.seq_train_failures = 0;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1678

intel_dp->link.seq_train_failures++;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1693

lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1697

if (intel_dp->link.seq_train_failures < MAX_SEQ_TRAIN_FAILURES)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1700

if (intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1703

intel_dp->link.retrain_disabled = true;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1706

lt_err(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after failure\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1708

lt_dbg(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after forced failure\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

171

if (intel_dp->link.active) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1711

void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

172

if (lttpr_count < 0 || intel_dp_lttpr_transparent_mode_enabled(intel_dp))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1724

drm_dp_dpcd_writeb(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1728

lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1735

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1745

if (intel_dp->link.active)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1746

current_rate = intel_dp->link_rate;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1747

force_rate = intel_dp->link.force_rate;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1755

for (i = 0; i < intel_dp->num_source_rates; i++)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1757

intel_dp->source_rates[i] == force_rate ? "[" : "",

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1758

intel_dp->source_rates[i],

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1759

intel_dp->source_rates[i] == current_rate ? "*" : "",

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1760

intel_dp->source_rates[i] == force_rate ? "]" : "");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1767

static int parse_link_rate(struct intel_dp *intel_dp, const char __user *ubuf, size_t len)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

178

ret = drm_dp_lttpr_init(&intel_dp->aux, lttpr_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1787

if (intel_dp_rate_index(intel_dp->source_rates,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1788

intel_dp->num_source_rates,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

180

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1806

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1810

rate = parse_link_rate(intel_dp, ubuf, len);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1818

intel_dp_reset_link_params(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1819

intel_dp->link.force_rate = rate;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

183

intel_dp_set_lttpr_transparent_mode(intel_dp, true);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1833

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1843

if (intel_dp->link.active)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1844

current_lane_count = intel_dp->lane_count;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1845

force_lane_count = intel_dp->link.force_lane_count;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

188

intel_dp_set_lttpr_transparent_mode(intel_dp, false);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1908

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1920

intel_dp_reset_link_params(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1921

intel_dp->link.force_lane_count = lane_count;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

193

intel_dp_reset_lttpr_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1935

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1942

*val = intel_dp->link.max_rate;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1954

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1961

*val = intel_dp->link.max_lane_count;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1973

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

198

static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1980

*val = intel_dp->link.force_train_failure;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1991

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2001

intel_dp->link.force_train_failure = val;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2015

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2022

*val = intel_dp->link.force_retrain;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

203

lttpr_count = intel_dp_init_lttpr_phys(intel_dp, dpcd);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2033

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2040

intel_dp->link.force_retrain = val;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2044

intel_hpd_trigger_irq(dp_to_dig_port(intel_dp));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2056

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

206

intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

2063

seq_printf(m, "%s\n", str_yes_no(intel_dp->link.retrain_disabled));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

207

drm_dp_dump_lttpr_desc(&intel_dp->aux, DP_PHY_LTTPR(i));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

213

int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE])

drivers/gpu/drm/i915/display/intel_dp_link_training.c

215

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

217

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

225

if (drm_dp_dpcd_probe(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

229

if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

253

int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

255

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

262

if (!intel_dp_is_edp(intel_dp) &&

drivers/gpu/drm/i915/display/intel_dp_link_training.c

265

int err = intel_dp_read_dprx_caps(intel_dp, dpcd);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

270

lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

277

if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

278

intel_dp_reset_lttpr_common_caps(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

300

static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

303

const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

311

static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

314

const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

323

intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

326

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

327

int lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

335

static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

339

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

346

if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

347

voltage_max = intel_dp->voltage_max(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

349

voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

358

static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

361

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

368

if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

369

preemph_max = intel_dp->preemph_max(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

371

preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

380

static bool has_per_lane_signal_levels(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

383

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

385

return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) ||

drivers/gpu/drm/i915/display/intel_dp_link_training.c

390

static u8 intel_dp_get_lane_adjust_tx_ffe_preset(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

398

if (has_per_lane_signal_levels(intel_dp, dp_phy)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

410

static u8 intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

421

if (has_per_lane_signal_levels(intel_dp, dp_phy)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

433

preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

439

voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

446

static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

453

return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

456

return intel_dp_get_lane_adjust_vswing_preemph(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

484

intel_dp_get_adjust_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

493

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

499

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

509

u8 new = intel_dp_get_lane_adjust_train(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

511

if (intel_dp->train_set[lane] == new)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

514

intel_dp->train_set[lane] = new;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

521

static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

530

intel_dp_set_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

535

int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

536

u8 buf[sizeof(intel_dp->train_set) + 1];

drivers/gpu/drm/i915/display/intel_dp_link_training.c

539

intel_dp_program_link_training_pattern(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

544

memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

547

return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

566

intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

574

lt_dbg(intel_dp, dp_phy, "Using DP training pattern TPS%c\n",

drivers/gpu/drm/i915/display/intel_dp_link_training.c

577

intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

605

void intel_dp_set_signal_levels(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

609

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

612

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

616

TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

618

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

623

TRAIN_SET_VSWING_ARGS(intel_dp->train_set),

drivers/gpu/drm/i915/display/intel_dp_link_training.c

624

TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

627

if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))

drivers/gpu/drm/i915/display/intel_dp_link_training.c

63

static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

632

intel_dp_reset_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

637

memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

638

intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

639

return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

643

intel_dp_update_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

65

memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps));

drivers/gpu/drm/i915/display/intel_dp_link_training.c

652

intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

654

ret = drm_dp_dpcd_write(&intel_dp->aux, reg,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

655

intel_dp->train_set, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

68

static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

693

static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

699

u8 train_set_lane = intel_dp->train_set[lane];

drivers/gpu/drm/i915/display/intel_dp_link_training.c

70

intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT -

drivers/gpu/drm/i915/display/intel_dp_link_training.c

713

void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

720

drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

723

static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

739

intel_dp_link_training_set_mode(intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

74

static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

743

void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

754

drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

766

drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

767

drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET, rate_select);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

77

return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1];

drivers/gpu/drm/i915/display/intel_dp_link_training.c

776

static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

780

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

795

drm_dp_tps4_supported(intel_dp->dpcd);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

80

static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

800

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

803

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

813

drm_dp_tps3_supported(intel_dp->dpcd);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

818

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

821

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

828

static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

832

intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, crtc_state->lane_count,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

84

u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

841

intel_dp_prepare_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

846

if (intel_dp->prepare_link_retrain)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

847

intel_dp->prepare_link_retrain(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

849

intel_dp_compute_rate(intel_dp, crtc_state->port_clock,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

86

if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

866

lt_dbg(intel_dp, DP_PHY_DPRX, "Reloading eDP link rates\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

868

drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

87

lt_dbg(intel_dp, dp_phy, "failed to read the PHY caps\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

873

lt_dbg(intel_dp, DP_PHY_DPRX, "Using LINK_BW_SET value %02x\n",

drivers/gpu/drm/i915/display/intel_dp_link_training.c

876

lt_dbg(intel_dp, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

883

intel_dp_update_downspread_ctrl(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

884

intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

91

lt_dbg(intel_dp, dp_phy, "PHY capabilities: %*ph\n",

drivers/gpu/drm/i915/display/intel_dp_link_training.c

917

intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

92

(int)sizeof(intel_dp->lttpr_phy_caps[0]),

drivers/gpu/drm/i915/display/intel_dp_link_training.c

920

lt_dbg(intel_dp, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

931

intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

941

delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

942

intel_dp->dpcd, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

946

if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

949

lt_err(intel_dp, dp_phy, "Failed to enable link training\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

96

static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

961

if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

970

if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

972

lt_err(intel_dp, dp_phy, "Failed to get link status\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

977

lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

982

intel_dp_dump_link_status(intel_dp, dp_phy, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

983

lt_dbg(intel_dp, dp_phy, "Same voltage tried 5 times\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

988

intel_dp_dump_link_status(intel_dp, dp_phy, link_status);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

989

lt_dbg(intel_dp, dp_phy, "Max Voltage Swing reached\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.c

994

intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

996

if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {

drivers/gpu/drm/i915/display/intel_dp_link_training.c

997

lt_err(intel_dp, dp_phy, "Failed to update link training\n");

drivers/gpu/drm/i915/display/intel_dp_link_training.h

14

struct intel_dp;

drivers/gpu/drm/i915/display/intel_dp_link_training.h

16

int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]);

drivers/gpu/drm/i915/display/intel_dp_link_training.h

17

int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.h

18

bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_link_training.h

20

void intel_dp_link_training_set_mode(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

22

void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

26

bool intel_dp_get_adjust_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

30

void intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

34

void intel_dp_set_signal_levels(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

38

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

40

void intel_dp_stop_link_train(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

44

intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,

drivers/gpu/drm/i915/display/intel_dp_link_training.h

53

void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1005

struct intel_dp *intel_dp = to_primary_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1009

drm_atomic_get_old_mst_topology_state(&state->base, &intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1011

drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1020

last_mst_stream = intel_dp_mst_dec_active_streams(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1034

drm_dp_remove_payload_part1(&intel_dp->mst.mgr, new_mst_state, new_payload);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1043

drm_dp_check_act_status(&intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1045

drm_dp_remove_payload_part2(&intel_dp->mst.mgr, new_mst_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

105

static struct intel_dp *to_primary_dp(struct intel_encoder *encoder)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1068

drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1100

struct intel_dp *intel_dp = to_primary_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1102

if (intel_dp_mst_active_streams(intel_dp) == 0 &&

drivers/gpu/drm/i915/display/intel_dp_mst.c

1113

struct intel_dp *intel_dp = to_primary_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1115

if (intel_dp_mst_active_streams(intel_dp) == 0)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1127

static bool intel_mst_probed_link_params_valid(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

113

int intel_dp_mst_active_streams(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1130

return intel_dp->link.mst_probed_rate == link_rate &&

drivers/gpu/drm/i915/display/intel_dp_mst.c

1131

intel_dp->link.mst_probed_lane_count == lane_count;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1134

static void intel_mst_set_probed_link_params(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1137

intel_dp->link.mst_probed_rate = link_rate;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1138

intel_dp->link.mst_probed_lane_count = lane_count;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1141

static void intel_mst_reprobe_topology(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1144

if (intel_mst_probed_link_params_valid(intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1148

drm_dp_mst_topology_queue_probe(&intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

115

return intel_dp->mst.active_streams;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1150

intel_mst_set_probed_link_params(intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1162

struct intel_dp *intel_dp = to_primary_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1166

drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1176

first_mst_stream = intel_dp_mst_inc_active_streams(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

118

static bool intel_dp_mst_dec_active_streams(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1181

intel_dp_set_power(intel_dp, DP_SET_POWER_D0);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1183

drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port, true);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1191

intel_mst_reprobe_topology(intel_dp, pipe_config);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1194

ret = drm_dp_add_payload_part1(&intel_dp->mst.mgr, mst_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

120

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

123

intel_dp->mst.active_streams, intel_dp->mst.active_streams - 1);

drivers/gpu/drm/i915/display/intel_dp_mst.c

125

if (drm_WARN_ON(display->drm, intel_dp->mst.active_streams == 0))

drivers/gpu/drm/i915/display/intel_dp_mst.c

1256

struct intel_dp *intel_dp = to_primary_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1259

drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1261

bool first_mst_stream = intel_dp_mst_active_streams(intel_dp) == 1;

drivers/gpu/drm/i915/display/intel_dp_mst.c

128

return --intel_dp->mst.active_streams == 0;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1290

drm_dp_check_act_status(&intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1295

ret = drm_dp_add_payload_part2(&intel_dp->mst.mgr,

drivers/gpu/drm/i915/display/intel_dp_mst.c

131

static bool intel_dp_mst_inc_active_streams(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_mst.c

133

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1348

struct intel_dp *intel_dp = connector->mst.dp;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1358

drm_edid = drm_dp_mst_edid_read(&connector->base, &intel_dp->mst.mgr, connector->mst.port);

drivers/gpu/drm/i915/display/intel_dp_mst.c

136

intel_dp->mst.active_streams, intel_dp->mst.active_streams + 1);

drivers/gpu/drm/i915/display/intel_dp_mst.c

138

return intel_dp->mst.active_streams++ == 0;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1419

struct intel_dp *intel_dp = connector->mst.dp;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1420

struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst.mgr;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1451

max_link_clock = intel_dp_max_link_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1452

max_lanes = intel_dp_max_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1454

max_rate = intel_dp_max_link_data_rate(intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1473

num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1526

struct intel_dp *intel_dp = connector->mst.dp;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1529

return &intel_dp->mst.stream_encoders[crtc->pipe]->base.base;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1538

struct intel_dp *intel_dp = connector->mst.dp;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1551

return drm_dp_mst_detect_port(&connector->base, ctx, &intel_dp->mst.mgr,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1587

static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1591

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1607

intel_dp->attached_connector->base.max_bpc_property;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1615

intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1688

struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1689

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1690

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1701

connector->mst.dp = intel_dp;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1711

intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, connector);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1719

&intel_dp->mst.stream_encoders[pipe]->base.base;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1726

ret = mst_topology_add_connector_properties(intel_dp, &connector->base, pathprop);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1749

struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1751

intel_hpd_trigger_irq(dp_to_dig_port(intel_dp));

drivers/gpu/drm/i915/display/intel_dp_mst.c

1818

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1822

intel_dp->mst.stream_encoders[pipe] = mst_stream_encoder_create(dig_port, pipe);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1830

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1834

if (!HAS_DP_MST(display) || intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp_mst.c

1843

intel_dp->mst.mgr.cbs = &mst_topology_cbs;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1847

ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst.mgr, display->drm,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1848

&intel_dp->aux, 16,

drivers/gpu/drm/i915/display/intel_dp_mst.c

1851

intel_dp->mst.mgr.cbs = NULL;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1858

bool intel_dp_mst_source_support(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_mst.c

1860

return intel_dp->mst.mgr.cbs;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1866

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_dp_mst.c

1868

if (!intel_dp_mst_source_support(intel_dp))

drivers/gpu/drm/i915/display/intel_dp_mst.c

1871

drm_dp_mst_topology_mgr_destroy(&intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

1874

intel_dp->mst.mgr.cbs = NULL;

drivers/gpu/drm/i915/display/intel_dp_mst.c

2045

void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_mst.c

2047

int link_rate = intel_dp_max_link_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

2048

int lane_count = intel_dp_max_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

2052

if (intel_dp->link.active)

drivers/gpu/drm/i915/display/intel_dp_mst.c

2055

if (intel_mst_probed_link_params_valid(intel_dp, link_rate, lane_count))

drivers/gpu/drm/i915/display/intel_dp_mst.c

2058

intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select);

drivers/gpu/drm/i915/display/intel_dp_mst.c

2060

intel_dp_link_training_set_mode(intel_dp, link_rate, false);

drivers/gpu/drm/i915/display/intel_dp_mst.c

2061

intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count,

drivers/gpu/drm/i915/display/intel_dp_mst.c

2062

drm_dp_enhanced_frame_cap(intel_dp->dpcd));

drivers/gpu/drm/i915/display/intel_dp_mst.c

2064

intel_mst_set_probed_link_params(intel_dp, link_rate, lane_count);

drivers/gpu/drm/i915/display/intel_dp_mst.c

2079

bool intel_dp_mst_verify_dpcd_state(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_mst.c

2081

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

2082

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp_mst.c

2083

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

2088

if (!intel_dp->is_mst)

drivers/gpu/drm/i915/display/intel_dp_mst.c

2091

ret = drm_dp_dpcd_readb(intel_dp->mst.mgr.aux, DP_MSTM_CTRL, &val);

drivers/gpu/drm/i915/display/intel_dp_mst.c

247

int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

252

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

276

mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst.mgr);

drivers/gpu/drm/i915/display/intel_dp_mst.c

300

!intel_dp_supports_fec(intel_dp, connector, crtc_state))

drivers/gpu/drm/i915/display/intel_dp_mst.c

330

if (dsc && !intel_dp_dsc_valid_compressed_bpp(intel_dp, bpp_x16)) {

drivers/gpu/drm/i915/display/intel_dp_mst.c

396

slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst.mgr,

drivers/gpu/drm/i915/display/intel_dp_mst.c

441

static int mst_stream_compute_link_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

453

return intel_dp_mtp_tu_compute_config(intel_dp, crtc_state, conn_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

459

static int mst_stream_dsc_compute_link_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

464

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.c

476

return intel_dp_mtp_tu_compute_config(intel_dp, crtc_state, conn_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

517

adjust_limits_for_dsc_hblank_expansion_quirk(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

531

if (intel_dp_supports_dsc(intel_dp, connector, crtc_state)) {

drivers/gpu/drm/i915/display/intel_dp_mst.c

577

mst_stream_compute_config_limits(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

586

if (!intel_dp_compute_config_limits(intel_dp, conn_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

591

return adjust_limits_for_dsc_hblank_expansion_quirk(intel_dp,

drivers/gpu/drm/i915/display/intel_dp_mst.c

605

struct intel_dp *intel_dp = to_primary_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

616

!intel_dp_supports_fec(intel_dp, connector, pipe_config))

drivers/gpu/drm/i915/display/intel_dp_mst.c

622

num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,

drivers/gpu/drm/i915/display/intel_dp_mst.c

634

dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||

drivers/gpu/drm/i915/display/intel_dp_mst.c

635

!mst_stream_compute_config_limits(intel_dp, conn_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

639

ret = mst_stream_compute_link_config(intel_dp, pipe_config,

drivers/gpu/drm/i915/display/intel_dp_mst.c

649

if (dsc_needed && !intel_dp_supports_dsc(intel_dp, connector, pipe_config)) {

drivers/gpu/drm/i915/display/intel_dp_mst.c

658

str_yes_no(intel_dp->force_dsc_en));

drivers/gpu/drm/i915/display/intel_dp_mst.c

661

if (!mst_stream_compute_config_limits(intel_dp, conn_state,

drivers/gpu/drm/i915/display/intel_dp_mst.c

670

drm_WARN(display->drm, intel_dp->force_dsc_bpc,

drivers/gpu/drm/i915/display/intel_dp_mst.c

678

ret = mst_stream_dsc_compute_link_config(intel_dp, pipe_config,

drivers/gpu/drm/i915/display/intel_dp_mst.c

683

ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,

drivers/gpu/drm/i915/display/intel_dp_mst.c

708

intel_psr_compute_config(intel_dp, pipe_config, conn_state);

drivers/gpu/drm/i915/display/intel_dp_mst.c

710

return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,

drivers/gpu/drm/i915/display/intel_dp_mst.c

720

struct intel_dp *mst_port)

drivers/gpu/drm/i915/display/intel_dp_mst.c

879

struct intel_dp *intel_dp = to_primary_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

883

ffs(intel_dp_mst_transcoder_mask(state, intel_dp)) - 1;

drivers/gpu/drm/i915/display/intel_dp_mst.c

985

struct intel_dp *intel_dp = to_primary_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_mst.c

989

if (intel_dp_mst_active_streams(intel_dp) == 1)

drivers/gpu/drm/i915/display/intel_dp_mst.c

990

intel_dp->link.active = false;

drivers/gpu/drm/i915/display/intel_dp_mst.h

16

struct intel_dp;

drivers/gpu/drm/i915/display/intel_dp_mst.h

21

int intel_dp_mst_active_streams(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.h

24

bool intel_dp_mst_source_support(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.h

31

void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.h

32

bool intel_dp_mst_verify_dpcd_state(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_mst.h

34

int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_test.c

103

if (!intel_dp_link_params_valid(intel_dp, test_link_rate,

drivers/gpu/drm/i915/display/intel_dp_test.c

107

intel_dp->compliance.test_lane_count = test_lane_count;

drivers/gpu/drm/i915/display/intel_dp_test.c

108

intel_dp->compliance.test_link_rate = test_link_rate;

drivers/gpu/drm/i915/display/intel_dp_test.c

113

static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_test.c

115

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

122

status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,

drivers/gpu/drm/i915/display/intel_dp_test.c

131

status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,

drivers/gpu/drm/i915/display/intel_dp_test.c

138

status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,

drivers/gpu/drm/i915/display/intel_dp_test.c

145

status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,

drivers/gpu/drm/i915/display/intel_dp_test.c

157

intel_dp->compliance.test_data.bpc = 6;

drivers/gpu/drm/i915/display/intel_dp_test.c

160

intel_dp->compliance.test_data.bpc = 8;

drivers/gpu/drm/i915/display/intel_dp_test.c

166

intel_dp->compliance.test_data.video_pattern = test_pattern;

drivers/gpu/drm/i915/display/intel_dp_test.c

167

intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);

drivers/gpu/drm/i915/display/intel_dp_test.c

168

intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);

drivers/gpu/drm/i915/display/intel_dp_test.c

170

intel_dp->compliance.test_active = true;

drivers/gpu/drm/i915/display/intel_dp_test.c

175

static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_test.c

177

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

179

struct intel_connector *intel_connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp_test.c

183

intel_dp->aux.i2c_defer_count > 6) {

drivers/gpu/drm/i915/display/intel_dp_test.c

191

if (intel_dp->aux.i2c_nack_count > 0 ||

drivers/gpu/drm/i915/display/intel_dp_test.c

192

intel_dp->aux.i2c_defer_count > 0)

drivers/gpu/drm/i915/display/intel_dp_test.c

195

intel_dp->aux.i2c_nack_count,

drivers/gpu/drm/i915/display/intel_dp_test.c

196

intel_dp->aux.i2c_defer_count);

drivers/gpu/drm/i915/display/intel_dp_test.c

197

intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;

drivers/gpu/drm/i915/display/intel_dp_test.c

205

if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,

drivers/gpu/drm/i915/display/intel_dp_test.c

21

void intel_dp_test_reset(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_test.c

211

intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;

drivers/gpu/drm/i915/display/intel_dp_test.c

215

intel_dp->compliance.test_active = true;

drivers/gpu/drm/i915/display/intel_dp_test.c

220

static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_test.c

223

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

225

&intel_dp->compliance.test_data.phytest;

drivers/gpu/drm/i915/display/intel_dp_test.c

227

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_test.c

27

memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));

drivers/gpu/drm/i915/display/intel_dp_test.c

306

static void intel_dp_process_phy_request(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_test.c

309

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

31

void intel_dp_test_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_test.c

311

&intel_dp->compliance.test_data.phytest;

drivers/gpu/drm/i915/display/intel_dp_test.c

314

if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_test.c

321

intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,

drivers/gpu/drm/i915/display/intel_dp_test.c

324

intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);

drivers/gpu/drm/i915/display/intel_dp_test.c

326

intel_dp_phy_pattern_update(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_test.c

328

drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,

drivers/gpu/drm/i915/display/intel_dp_test.c

329

intel_dp->train_set, crtc_state->lane_count);

drivers/gpu/drm/i915/display/intel_dp_test.c

331

drm_dp_set_phy_test_pattern(&intel_dp->aux, data,

drivers/gpu/drm/i915/display/intel_dp_test.c

332

intel_dp->dpcd[DP_DPCD_REV]);

drivers/gpu/drm/i915/display/intel_dp_test.c

335

static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_test.c

337

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

339

&intel_dp->compliance.test_data.phytest;

drivers/gpu/drm/i915/display/intel_dp_test.c

341

if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {

drivers/gpu/drm/i915/display/intel_dp_test.c

348

intel_dp->compliance.test_active = true;

drivers/gpu/drm/i915/display/intel_dp_test.c

35

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

353

void intel_dp_test_request(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_test.c

355

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

360

status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);

drivers/gpu/drm/i915/display/intel_dp_test.c

370

response = intel_dp_autotest_link_training(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

374

response = intel_dp_autotest_video_pattern(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

378

response = intel_dp_autotest_edid(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

38

if (intel_dp->compliance.test_data.bpc != 0) {

drivers/gpu/drm/i915/display/intel_dp_test.c

382

response = intel_dp_autotest_phy_pattern(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

39

int bpp = 3 * intel_dp->compliance.test_data.bpc;

drivers/gpu/drm/i915/display/intel_dp_test.c

391

intel_dp->compliance.test_type = request;

drivers/gpu/drm/i915/display/intel_dp_test.c

394

status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);

drivers/gpu/drm/i915/display/intel_dp_test.c

402

static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_test.c

406

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

420

if (!intel_dp_has_connector(intel_dp, conn_state))

drivers/gpu/drm/i915/display/intel_dp_test.c

454

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_test.c

464

ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);

drivers/gpu/drm/i915/display/intel_dp_test.c

484

intel_dp_process_phy_request(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_dp_test.c

49

if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {

drivers/gpu/drm/i915/display/intel_dp_test.c

491

bool intel_dp_test_phy(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_test.c

493

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

498

if (!intel_dp->compliance.test_active ||

drivers/gpu/drm/i915/display/intel_dp_test.c

499

intel_dp->compliance.test_type != DP_TEST_LINK_PHY_TEST_PATTERN)

drivers/gpu/drm/i915/display/intel_dp_test.c

523

bool intel_dp_test_short_pulse(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_test.c

525

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

528

switch (intel_dp->compliance.test_type) {

drivers/gpu/drm/i915/display/intel_dp_test.c

55

if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,

drivers/gpu/drm/i915/display/intel_dp_test.c

56

intel_dp->compliance.test_lane_count)) {

drivers/gpu/drm/i915/display/intel_dp_test.c

560

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_dp_test.c

57

index = intel_dp_rate_index(intel_dp->common_rates,

drivers/gpu/drm/i915/display/intel_dp_test.c

58

intel_dp->num_common_rates,

drivers/gpu/drm/i915/display/intel_dp_test.c

585

intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_test.c

59

intel_dp->compliance.test_link_rate);

drivers/gpu/drm/i915/display/intel_dp_test.c

594

intel_dp->compliance.test_active = true;

drivers/gpu/drm/i915/display/intel_dp_test.c

596

intel_dp->compliance.test_active = false;

drivers/gpu/drm/i915/display/intel_dp_test.c

61

limits->min_rate = intel_dp->compliance.test_link_rate;

drivers/gpu/drm/i915/display/intel_dp_test.c

613

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_dp_test.c

62

limits->max_rate = intel_dp->compliance.test_link_rate;

drivers/gpu/drm/i915/display/intel_dp_test.c

628

intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_test.c

629

if (intel_dp->compliance.test_active)

drivers/gpu/drm/i915/display/intel_dp_test.c

64

limits->min_lane_count = intel_dp->compliance.test_lane_count;

drivers/gpu/drm/i915/display/intel_dp_test.c

65

limits->max_lane_count = intel_dp->compliance.test_lane_count;

drivers/gpu/drm/i915/display/intel_dp_test.c

663

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_dp_test.c

678

intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_test.c

679

if (intel_dp->compliance.test_type ==

drivers/gpu/drm/i915/display/intel_dp_test.c

682

intel_dp->compliance.test_data.edid);

drivers/gpu/drm/i915/display/intel_dp_test.c

683

else if (intel_dp->compliance.test_type ==

drivers/gpu/drm/i915/display/intel_dp_test.c

686

intel_dp->compliance.test_data.hdisplay);

drivers/gpu/drm/i915/display/intel_dp_test.c

688

intel_dp->compliance.test_data.vdisplay);

drivers/gpu/drm/i915/display/intel_dp_test.c

690

intel_dp->compliance.test_data.bpc);

drivers/gpu/drm/i915/display/intel_dp_test.c

691

} else if (intel_dp->compliance.test_type ==

drivers/gpu/drm/i915/display/intel_dp_test.c

694

intel_dp->compliance.test_data.phytest.phy_pattern);

drivers/gpu/drm/i915/display/intel_dp_test.c

696

intel_dp->compliance.test_data.phytest.num_lanes);

drivers/gpu/drm/i915/display/intel_dp_test.c

698

intel_dp->compliance.test_data.phytest.link_rate);

drivers/gpu/drm/i915/display/intel_dp_test.c

700

intel_dp->train_set[0]);

drivers/gpu/drm/i915/display/intel_dp_test.c

717

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_dp_test.c

732

intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dp_test.c

733

seq_printf(m, "%02lx\n", intel_dp->compliance.test_type);

drivers/gpu/drm/i915/display/intel_dp_test.c

75

static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_test.c

77

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.c

85

status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,

drivers/gpu/drm/i915/display/intel_dp_test.c

94

status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,

drivers/gpu/drm/i915/display/intel_dp_test.h

11

struct intel_dp;

drivers/gpu/drm/i915/display/intel_dp_test.h

14

void intel_dp_test_reset(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.h

15

void intel_dp_test_request(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.h

16

void intel_dp_test_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_test.h

19

bool intel_dp_test_phy(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_test.h

20

bool intel_dp_test_short_pulse(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

108

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

122

static int allocate_initial_tunnel_bw_for_pipes(struct intel_dp *intel_dp, u8 pipe_mask)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

124

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

125

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

139

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

146

err = drm_dp_tunnel_alloc_bw(intel_dp->tunnel, tunnel_bw);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

150

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

157

return update_tunnel_state(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

160

static int allocate_initial_tunnel_bw(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

166

err = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

170

return allocate_initial_tunnel_bw_for_pipes(intel_dp, pipe_mask);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

173

static int detect_new_tunnel(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

175

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

176

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

181

&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

185

intel_dp->tunnel = tunnel;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

187

ret = drm_dp_tunnel_enable_bw_alloc(intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

194

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

202

ret = allocate_initial_tunnel_bw(intel_dp, ctx);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

204

intel_dp_tunnel_destroy(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

228

int intel_dp_tunnel_detect(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

232

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

235

if (intel_dp->tunnel) {

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

236

ret = update_tunnel_state(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

241

intel_dp_tunnel_destroy(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

244

return detect_new_tunnel(intel_dp, ctx);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

256

bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

258

return drm_dp_tunnel_bw_alloc_is_enabled(intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

267

void intel_dp_tunnel_suspend(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

269

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

270

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

271

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

273

if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

278

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

282

drm_dp_tunnel_disable_bw_alloc(intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

284

intel_dp->tunnel_suspended = true;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

295

void intel_dp_tunnel_resume(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

299

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

30

void intel_dp_tunnel_disconnect(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

300

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

301

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

306

if (!intel_dp->tunnel_suspended)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

309

intel_dp->tunnel_suspended = false;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

313

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

32

drm_dp_tunnel_destroy(intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

325

err = intel_dp_read_dprx_caps(intel_dp, dpcd);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

328

drm_dp_tunnel_set_io_error(intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

33

intel_dp->tunnel = NULL;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

333

err = drm_dp_tunnel_enable_bw_alloc(intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

345

err = allocate_initial_tunnel_bw_for_pipes(intel_dp, pipe_mask);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

354

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

395

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

399

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

413

if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

423

old_crtc_state->dp_tunnel_ref.tunnel == intel_dp->tunnel)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

428

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

432

intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

434

return add_inherited_tunnel(state, intel_dp->tunnel, old_crtc);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

44

void intel_dp_tunnel_destroy(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

46

if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

47

drm_dp_tunnel_disable_bw_alloc(intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

49

intel_dp_tunnel_disconnect(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

505

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

510

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

519

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

542

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

552

err = check_group_state(state, intel_dp, connector,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

560

err = check_group_state(state, intel_dp, connector,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

566

return check_inherited_tunnel_state(state, intel_dp, old_conn_state);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

57

static int get_current_link_bw(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

584

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

589

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

594

if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

599

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

60

int rate = intel_dp_max_common_rate(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

606

ret = drm_dp_tunnel_atomic_set_stream_bw(&state->base, intel_dp->tunnel,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

61

int lane_count = intel_dp_max_common_lane_count(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

611

drm_dp_tunnel_ref_get(intel_dp->tunnel,

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

64

bw = intel_dp_max_link_data_rate(intel_dp, rate, lane_count);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

70

static int update_tunnel_state(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

72

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

73

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

80

old_bw = get_current_link_bw(intel_dp, &old_bw_below_dprx);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

82

ret = drm_dp_tunnel_update_state(intel_dp->tunnel);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

86

drm_dp_tunnel_name(intel_dp->tunnel),

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

94

!drm_dp_tunnel_bw_alloc_is_enabled(intel_dp->tunnel))

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

97

intel_dp_update_sink_caps(intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.c

99

new_bw = get_current_link_bw(intel_dp, &new_bw_below_dprx);

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

114

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

19

struct intel_dp;

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

26

int intel_dp_tunnel_detect(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx);

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

27

void intel_dp_tunnel_disconnect(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

28

void intel_dp_tunnel_destroy(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

29

void intel_dp_tunnel_resume(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

32

void intel_dp_tunnel_suspend(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

34

bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

40

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

51

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

62

intel_dp_tunnel_detect(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx)

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

67

static inline void intel_dp_tunnel_disconnect(struct intel_dp *intel_dp) {}

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

68

static inline void intel_dp_tunnel_destroy(struct intel_dp *intel_dp) {}

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

69

static inline void intel_dp_tunnel_resume(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

72

static inline void intel_dp_tunnel_suspend(struct intel_dp *intel_dp) {}

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

74

static inline bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_dp_tunnel.h

84

struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1132

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

1133

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

952

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

953

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

101

ident = &intel_dp->desc.ident;

drivers/gpu/drm/i915/display/intel_lspcon.c

135

struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);

drivers/gpu/drm/i915/display/intel_lspcon.c

136

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

140

ret = drm_dp_dpcd_read(&intel_dp->aux, get_hdr_status_reg(lspcon),

drivers/gpu/drm/i915/display/intel_lspcon.c

156

struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);

drivers/gpu/drm/i915/display/intel_lspcon.c

157

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

159

struct i2c_adapter *ddc = &intel_dp->aux.ddc;

drivers/gpu/drm/i915/display/intel_lspcon.c

161

if (drm_lspcon_get_mode(intel_dp->aux.drm_dev, ddc, &current_mode)) {

drivers/gpu/drm/i915/display/intel_lspcon.c

183

struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);

drivers/gpu/drm/i915/display/intel_lspcon.c

184

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

214

struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);

drivers/gpu/drm/i915/display/intel_lspcon.c

215

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

218

struct i2c_adapter *ddc = &intel_dp->aux.ddc;

drivers/gpu/drm/i915/display/intel_lspcon.c

220

err = drm_lspcon_get_mode(intel_dp->aux.drm_dev, ddc, &current_mode);

drivers/gpu/drm/i915/display/intel_lspcon.c

231

err = drm_lspcon_set_mode(intel_dp->aux.drm_dev, ddc, mode,

drivers/gpu/drm/i915/display/intel_lspcon.c

245

struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);

drivers/gpu/drm/i915/display/intel_lspcon.c

246

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

263

struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);

drivers/gpu/drm/i915/display/intel_lspcon.c

264

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

265

struct i2c_adapter *ddc = &intel_dp->aux.ddc;

drivers/gpu/drm/i915/display/intel_lspcon.c

278

adaptor_type = drm_dp_dual_mode_detect(intel_dp->aux.drm_dev, ddc);

drivers/gpu/drm/i915/display/intel_lspcon.c

309

struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);

drivers/gpu/drm/i915/display/intel_lspcon.c

310

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

311

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

499

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_lspcon.c

506

ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_lspcon.c

509

ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_lspcon.c

646

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_lspcon.c

653

infoframes_enabled = _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_lspcon.c

655

infoframes_enabled = _lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux);

drivers/gpu/drm/i915/display/intel_lspcon.c

66

static struct intel_dp *lspcon_to_intel_dp(struct intel_lspcon *lspcon)

drivers/gpu/drm/i915/display/intel_lspcon.c

682

struct intel_dp *intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_lspcon.c

684

struct drm_connector *connector = &intel_dp->attached_connector->base;

drivers/gpu/drm/i915/display/intel_lspcon.c

694

if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) {

drivers/gpu/drm/i915/display/intel_lspcon.c

91

struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);

drivers/gpu/drm/i915/display/intel_lspcon.c

92

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_lspcon.c

96

if (drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, drm_dp_is_branch(intel_dp->dpcd))) {

drivers/gpu/drm/i915/display/intel_lt_phy.c

1331

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1334

intel_psr_pause(intel_dp);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1343

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1345

intel_psr_resume(intel_dp);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1374

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1376

return (intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);

drivers/gpu/drm/i915/display/intel_pps.c

1004

wait_panel_on(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1005

intel_dp->pps.last_power_on = jiffies;

drivers/gpu/drm/i915/display/intel_pps.c

1018

void intel_pps_on(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1020

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

1023

with_intel_pps_lock(intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1024

intel_pps_on_unlocked(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1027

void intel_pps_off_unlocked(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1029

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1030

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1036

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

1041

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

1043

drm_WARN(display->drm, !intel_dp->pps.want_panel_vdd,

drivers/gpu/drm/i915/display/intel_pps.c

1046

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

1048

pp = ilk_get_pp_control(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1054

pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1056

intel_dp->pps.want_panel_vdd = false;

drivers/gpu/drm/i915/display/intel_pps.c

106

intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN,

drivers/gpu/drm/i915/display/intel_pps.c

1061

wait_panel_off(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1062

intel_dp->pps.panel_power_off_time = ktime_get_boottime();

drivers/gpu/drm/i915/display/intel_pps.c

1064

intel_dp_invalidate_source_oui(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1069

fetch_and_zero(&intel_dp->pps.vdd_wakeref));

drivers/gpu/drm/i915/display/intel_pps.c

1072

void intel_pps_off(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1074

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

1077

with_intel_pps_lock(intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1078

intel_pps_off_unlocked(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

108

pps_name(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

1082

void intel_pps_backlight_on(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1084

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1092

wait_backlight_on(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1094

with_intel_pps_lock(intel_dp) {

drivers/gpu/drm/i915/display/intel_pps.c

1095

i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1098

pp = ilk_get_pp_control(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1107

void intel_pps_backlight_off(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1109

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1111

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

1114

with_intel_pps_lock(intel_dp) {

drivers/gpu/drm/i915/display/intel_pps.c

1115

i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1118

pp = ilk_get_pp_control(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1125

intel_dp->pps.last_backlight_off = jiffies;

drivers/gpu/drm/i915/display/intel_pps.c

1126

edp_wait_backlight_off(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1136

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_pps.c

114

pps_name(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

1140

with_intel_pps_lock(intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1141

is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;

drivers/gpu/drm/i915/display/intel_pps.c

1149

intel_pps_backlight_on(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1151

intel_pps_backlight_off(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1154

static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1156

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1157

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1158

enum pipe pipe = intel_dp->pps.vlv_pps_pipe;

drivers/gpu/drm/i915/display/intel_pps.c

1161

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_pps.c

1166

intel_pps_vdd_off_sync_unlocked(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1179

pps_name(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

1184

intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;

drivers/gpu/drm/i915/display/intel_pps.c

1195

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_pps.c

1197

drm_WARN(display->drm, intel_dp->pps.vlv_active_pipe == pipe,

drivers/gpu/drm/i915/display/intel_pps.c

120

DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;

drivers/gpu/drm/i915/display/intel_pps.c

1202

if (intel_dp->pps.vlv_pps_pipe != pipe)

drivers/gpu/drm/i915/display/intel_pps.c

1211

vlv_detach_power_sequencer(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1215

static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1217

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1218

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_pps.c

1221

if (g4x_dp_port_enabled(display, intel_dp->output_reg,

drivers/gpu/drm/i915/display/intel_pps.c

1229

void vlv_pps_pipe_init(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1231

intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;

drivers/gpu/drm/i915/display/intel_pps.c

1232

intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1236

void vlv_pps_pipe_reset(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1238

with_intel_pps_lock(intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1239

intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1242

enum pipe vlv_pps_backlight_initial_pipe(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1251

pipe = vlv_active_pipe(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1254

pipe = intel_dp->pps.vlv_pps_pipe;

drivers/gpu/drm/i915/display/intel_pps.c

1267

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_pps.c

1272

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_pps.c

1274

if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE &&

drivers/gpu/drm/i915/display/intel_pps.c

1275

intel_dp->pps.vlv_pps_pipe != crtc->pipe) {

drivers/gpu/drm/i915/display/intel_pps.c

1281

vlv_detach_power_sequencer(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1290

intel_dp->pps.vlv_active_pipe = crtc->pipe;

drivers/gpu/drm/i915/display/intel_pps.c

1292

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

1296

intel_dp->pps.vlv_pps_pipe = crtc->pipe;

drivers/gpu/drm/i915/display/intel_pps.c

1300

pps_name(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

1304

pps_init_delays(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1305

pps_init_registers(intel_dp, true);

drivers/gpu/drm/i915/display/intel_pps.c

1312

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_pps.c

1314

with_intel_pps_lock(intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1315

intel_dp->pps.vlv_active_pipe = INVALID_PIPE;

drivers/gpu/drm/i915/display/intel_pps.c

1318

static void pps_vdd_init(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1320

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1321

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1325

if (!edp_have_panel_vdd(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

1337

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

1338

drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);

drivers/gpu/drm/i915/display/intel_pps.c

1339

intel_dp->pps.vdd_wakeref = intel_display_power_get(display,

drivers/gpu/drm/i915/display/intel_pps.c

1343

bool intel_pps_have_panel_power_or_vdd(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1347

with_intel_pps_lock(intel_dp) {

drivers/gpu/drm/i915/display/intel_pps.c

1348

have_power = edp_have_panel_power(intel_dp) ||

drivers/gpu/drm/i915/display/intel_pps.c

1349

edp_have_panel_vdd(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1355

static void pps_init_timestamps(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1363

intel_dp->pps.panel_power_off_time = 0;

drivers/gpu/drm/i915/display/intel_pps.c

1364

intel_dp->pps.last_power_on = jiffies;

drivers/gpu/drm/i915/display/intel_pps.c

1365

intel_dp->pps.last_backlight_off = jiffies;

drivers/gpu/drm/i915/display/intel_pps.c

1369

intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct intel_pps_delays *seq)

drivers/gpu/drm/i915/display/intel_pps.c

1371

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1375

intel_pps_get_registers(intel_dp, &regs);

drivers/gpu/drm/i915/display/intel_pps.c

1377

pp_ctl = ilk_get_pp_control(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1407

intel_pps_dump_state(struct intel_dp *intel_dp, const char *state_name,

drivers/gpu/drm/i915/display/intel_pps.c

1410

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1419

intel_pps_verify_state(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1421

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1423

struct intel_pps_delays *sw = &intel_dp->pps.pps_delays;

drivers/gpu/drm/i915/display/intel_pps.c

1425

intel_pps_readout_hw_state(intel_dp, &hw);

drivers/gpu/drm/i915/display/intel_pps.c

1433

intel_pps_dump_state(intel_dp, "sw", sw);

drivers/gpu/drm/i915/display/intel_pps.c

1434

intel_pps_dump_state(intel_dp, "hw", &hw);

drivers/gpu/drm/i915/display/intel_pps.c

1456

static void pps_init_delays_bios(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_pps.c

1459

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1463

if (!pps_delays_valid(&intel_dp->pps.bios_pps_delays))

drivers/gpu/drm/i915/display/intel_pps.c

1464

intel_pps_readout_hw_state(intel_dp, &intel_dp->pps.bios_pps_delays);

drivers/gpu/drm/i915/display/intel_pps.c

1466

*bios = intel_dp->pps.bios_pps_delays;

drivers/gpu/drm/i915/display/intel_pps.c

1468

intel_pps_dump_state(intel_dp, "bios", bios);

drivers/gpu/drm/i915/display/intel_pps.c

1471

static void pps_init_delays_vbt(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_pps.c

1474

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1475

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_pps.c

1495

intel_pps_dump_state(intel_dp, "vbt", vbt);

drivers/gpu/drm/i915/display/intel_pps.c

1498

static void pps_init_delays_spec(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_pps.c

1501

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1512

intel_pps_dump_state(intel_dp, "spec", spec);

drivers/gpu/drm/i915/display/intel_pps.c

1515

static void pps_init_delays(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1517

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1519

*final = &intel_dp->pps.pps_delays;

drivers/gpu/drm/i915/display/intel_pps.c

1527

pps_init_delays_bios(intel_dp, &cur);

drivers/gpu/drm/i915/display/intel_pps.c

1528

pps_init_delays_vbt(intel_dp, &vbt);

drivers/gpu/drm/i915/display/intel_pps.c

1529

pps_init_delays_spec(intel_dp, &spec);

drivers/gpu/drm/i915/display/intel_pps.c

154

intel_de_write(display, intel_dp->output_reg, DP);

drivers/gpu/drm/i915/display/intel_pps.c

1543

intel_dp->pps.panel_power_up_delay = pps_units_to_msecs(final->power_up);

drivers/gpu/drm/i915/display/intel_pps.c

1544

intel_dp->pps.backlight_on_delay = pps_units_to_msecs(final->backlight_on);

drivers/gpu/drm/i915/display/intel_pps.c

1545

intel_dp->pps.backlight_off_delay = pps_units_to_msecs(final->backlight_off);

drivers/gpu/drm/i915/display/intel_pps.c

1546

intel_dp->pps.panel_power_down_delay = pps_units_to_msecs(final->power_down);

drivers/gpu/drm/i915/display/intel_pps.c

1547

intel_dp->pps.panel_power_cycle_delay = pps_units_to_msecs(final->power_cycle);

drivers/gpu/drm/i915/display/intel_pps.c

155

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/intel_pps.c

1551

intel_dp->pps.panel_power_up_delay,

drivers/gpu/drm/i915/display/intel_pps.c

1552

intel_dp->pps.panel_power_down_delay,

drivers/gpu/drm/i915/display/intel_pps.c

1553

intel_dp->pps.panel_power_cycle_delay);

drivers/gpu/drm/i915/display/intel_pps.c

1556

intel_dp->pps.backlight_on_delay,

drivers/gpu/drm/i915/display/intel_pps.c

1557

intel_dp->pps.backlight_off_delay);

drivers/gpu/drm/i915/display/intel_pps.c

157

intel_de_write(display, intel_dp->output_reg, DP | DP_PORT_EN);

drivers/gpu/drm/i915/display/intel_pps.c

1577

static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd)

drivers/gpu/drm/i915/display/intel_pps.c

1579

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

158

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/intel_pps.c

1583

enum port port = dp_to_dig_port(intel_dp)->base.port;

drivers/gpu/drm/i915/display/intel_pps.c

1584

const struct intel_pps_delays *seq = &intel_dp->pps.pps_delays;

drivers/gpu/drm/i915/display/intel_pps.c

1588

intel_pps_get_registers(intel_dp, &regs);

drivers/gpu/drm/i915/display/intel_pps.c

160

intel_de_write(display, intel_dp->output_reg, DP & ~DP_PORT_EN);

drivers/gpu/drm/i915/display/intel_pps.c

1603

u32 pp = ilk_get_pp_control(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

161

intel_de_posting_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/intel_pps.c

1671

void intel_pps_encoder_reset(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1673

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1675

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

1678

with_intel_pps_lock(intel_dp) {

drivers/gpu/drm/i915/display/intel_pps.c

1684

vlv_initial_power_sequencer_setup(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1686

pps_init_delays(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1687

pps_init_registers(intel_dp, false);

drivers/gpu/drm/i915/display/intel_pps.c

1688

pps_vdd_init(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1690

if (edp_have_panel_vdd(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

1691

edp_panel_vdd_schedule_off(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1695

bool intel_pps_init(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1699

intel_dp->pps.initializing = true;

drivers/gpu/drm/i915/display/intel_pps.c

1700

INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);

drivers/gpu/drm/i915/display/intel_pps.c

1702

pps_init_timestamps(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1704

with_intel_pps_lock(intel_dp) {

drivers/gpu/drm/i915/display/intel_pps.c

1705

ret = pps_initial_setup(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1707

pps_init_delays(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1708

pps_init_registers(intel_dp, false);

drivers/gpu/drm/i915/display/intel_pps.c

1709

pps_vdd_init(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1715

static void pps_init_late(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1717

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1718

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_pps.c

1719

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_pps.c

1729

intel_dp->pps.pps_idx != connector->panel.vbt.backlight.controller,

drivers/gpu/drm/i915/display/intel_pps.c

1732

intel_dp->pps.pps_idx, connector->panel.vbt.backlight.controller);

drivers/gpu/drm/i915/display/intel_pps.c

1735

intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;

drivers/gpu/drm/i915/display/intel_pps.c

1738

void intel_pps_init_late(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

1740

with_intel_pps_lock(intel_dp) {

drivers/gpu/drm/i915/display/intel_pps.c

1742

pps_init_late(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1744

memset(&intel_dp->pps.pps_delays, 0, sizeof(intel_dp->pps.pps_delays));

drivers/gpu/drm/i915/display/intel_pps.c

1745

pps_init_delays(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1746

pps_init_registers(intel_dp, false);

drivers/gpu/drm/i915/display/intel_pps.c

1748

intel_dp->pps.initializing = false;

drivers/gpu/drm/i915/display/intel_pps.c

1750

if (edp_have_panel_vdd(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

1751

edp_panel_vdd_schedule_off(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

1786

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_pps.c

1792

intel_dp->pps.panel_power_up_delay);

drivers/gpu/drm/i915/display/intel_pps.c

1794

intel_dp->pps.panel_power_down_delay);

drivers/gpu/drm/i915/display/intel_pps.c

1796

intel_dp->pps.panel_power_cycle_delay);

drivers/gpu/drm/i915/display/intel_pps.c

1798

intel_dp->pps.backlight_on_delay);

drivers/gpu/drm/i915/display/intel_pps.c

1800

intel_dp->pps.backlight_off_delay);

drivers/gpu/drm/i915/display/intel_pps.c

181

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_pps.c

185

intel_dp->pps.vlv_active_pipe != INVALID_PIPE &&

drivers/gpu/drm/i915/display/intel_pps.c

186

intel_dp->pps.vlv_active_pipe !=

drivers/gpu/drm/i915/display/intel_pps.c

187

intel_dp->pps.vlv_pps_pipe);

drivers/gpu/drm/i915/display/intel_pps.c

189

if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE)

drivers/gpu/drm/i915/display/intel_pps.c

190

pipes &= ~(1 << intel_dp->pps.vlv_pps_pipe);

drivers/gpu/drm/i915/display/intel_pps.c

193

intel_dp->pps.vlv_pps_pipe != INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_pps.c

195

if (intel_dp->pps.vlv_active_pipe != INVALID_PIPE)

drivers/gpu/drm/i915/display/intel_pps.c

196

pipes &= ~(1 << intel_dp->pps.vlv_active_pipe);

drivers/gpu/drm/i915/display/intel_pps.c

207

vlv_power_sequencer_pipe(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

209

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

210

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

216

drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

218

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE &&

drivers/gpu/drm/i915/display/intel_pps.c

219

intel_dp->pps.vlv_active_pipe != intel_dp->pps.vlv_pps_pipe);

drivers/gpu/drm/i915/display/intel_pps.c

221

if (intel_dp->pps.vlv_pps_pipe != INVALID_PIPE)

drivers/gpu/drm/i915/display/intel_pps.c

222

return intel_dp->pps.vlv_pps_pipe;

drivers/gpu/drm/i915/display/intel_pps.c

234

intel_dp->pps.vlv_pps_pipe = pipe;

drivers/gpu/drm/i915/display/intel_pps.c

238

pps_name(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

242

pps_init_delays(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

243

pps_init_registers(intel_dp, true);

drivers/gpu/drm/i915/display/intel_pps.c

249

vlv_power_sequencer_kick(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

251

return intel_dp->pps.vlv_pps_pipe;

drivers/gpu/drm/i915/display/intel_pps.c

255

bxt_power_sequencer_idx(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

257

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

258

int pps_idx = intel_dp->pps.pps_idx;

drivers/gpu/drm/i915/display/intel_pps.c

263

drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

265

if (!intel_dp->pps.bxt_pps_reset)

drivers/gpu/drm/i915/display/intel_pps.c

268

intel_dp->pps.bxt_pps_reset = false;

drivers/gpu/drm/i915/display/intel_pps.c

274

pps_init_registers(intel_dp, false);

drivers/gpu/drm/i915/display/intel_pps.c

31

static void pps_init_delays(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

32

static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd);

drivers/gpu/drm/i915/display/intel_pps.c

320

vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

322

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

323

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

330

intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,

drivers/gpu/drm/i915/display/intel_pps.c

333

if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)

drivers/gpu/drm/i915/display/intel_pps.c

334

intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,

drivers/gpu/drm/i915/display/intel_pps.c

337

if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)

drivers/gpu/drm/i915/display/intel_pps.c

338

intel_dp->pps.vlv_pps_pipe = vlv_initial_pps_pipe(display, port,

drivers/gpu/drm/i915/display/intel_pps.c

34

static const char *pps_name(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

342

if (intel_dp->pps.vlv_pps_pipe == INVALID_PIPE) {

drivers/gpu/drm/i915/display/intel_pps.c

352

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

36

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

37

struct intel_pps *pps = &intel_dp->pps;

drivers/gpu/drm/i915/display/intel_pps.c

375

static bool intel_pps_is_valid(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

377

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

379

if (intel_dp->pps.pps_idx == 1 &&

drivers/gpu/drm/i915/display/intel_pps.c

401

pps_initial_setup(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

403

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

404

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

drivers/gpu/drm/i915/display/intel_pps.c

405

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_pps.c

410

vlv_initial_power_sequencer_setup(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

416

intel_dp->pps.pps_idx = connector->panel.vbt.backlight.controller;

drivers/gpu/drm/i915/display/intel_pps.c

418

intel_dp->pps.pps_idx = 0;

drivers/gpu/drm/i915/display/intel_pps.c

420

if (drm_WARN_ON(display->drm, intel_dp->pps.pps_idx >= intel_num_pps(display)))

drivers/gpu/drm/i915/display/intel_pps.c

421

intel_dp->pps.pps_idx = -1;

drivers/gpu/drm/i915/display/intel_pps.c

424

if (intel_dp->pps.pps_idx < 0)

drivers/gpu/drm/i915/display/intel_pps.c

425

intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_pp_on);

drivers/gpu/drm/i915/display/intel_pps.c

427

if (intel_dp->pps.pps_idx < 0)

drivers/gpu/drm/i915/display/intel_pps.c

428

intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_has_vdd_on);

drivers/gpu/drm/i915/display/intel_pps.c

430

if (intel_dp->pps.pps_idx < 0) {

drivers/gpu/drm/i915/display/intel_pps.c

431

intel_dp->pps.pps_idx = bxt_initial_pps_idx(display, pps_any);

drivers/gpu/drm/i915/display/intel_pps.c

436

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

441

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

444

return intel_pps_is_valid(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

465

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_pps.c

467

drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE);

drivers/gpu/drm/i915/display/intel_pps.c

470

intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;

drivers/gpu/drm/i915/display/intel_pps.c

484

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_pps.c

487

intel_dp->pps.bxt_pps_reset = true;

drivers/gpu/drm/i915/display/intel_pps.c

499

static void intel_pps_get_registers(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_pps.c

502

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

508

pps_idx = vlv_power_sequencer_pipe(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

510

pps_idx = bxt_power_sequencer_idx(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

512

pps_idx = intel_dp->pps.pps_idx;

drivers/gpu/drm/i915/display/intel_pps.c

528

_pp_ctrl_reg(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

532

intel_pps_get_registers(intel_dp, &regs);

drivers/gpu/drm/i915/display/intel_pps.c

538

_pp_stat_reg(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

542

intel_pps_get_registers(intel_dp, &regs);

drivers/gpu/drm/i915/display/intel_pps.c

547

static bool edp_have_panel_power(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

549

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

554

intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)

drivers/gpu/drm/i915/display/intel_pps.c

557

return (intel_de_read(display, _pp_stat_reg(intel_dp)) & PP_ON) != 0;

drivers/gpu/drm/i915/display/intel_pps.c

560

static bool edp_have_panel_vdd(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

562

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

567

intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)

drivers/gpu/drm/i915/display/intel_pps.c

570

return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;

drivers/gpu/drm/i915/display/intel_pps.c

573

void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

575

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

576

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

578

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

581

if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {

drivers/gpu/drm/i915/display/intel_pps.c

585

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

589

pps_name(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

590

intel_de_read(display, _pp_stat_reg(intel_dp)),

drivers/gpu/drm/i915/display/intel_pps.c

591

intel_de_read(display, _pp_ctrl_reg(intel_dp)));

drivers/gpu/drm/i915/display/intel_pps.c

604

static void intel_pps_verify_state(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

606

static void wait_panel_status(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_pps.c

609

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

610

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

617

intel_pps_verify_state(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

619

pp_stat_reg = _pp_stat_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

620

pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

625

pps_name(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

637

pps_name(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

646

static void wait_panel_on(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

648

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

649

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

654

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

655

wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);

drivers/gpu/drm/i915/display/intel_pps.c

658

static void wait_panel_off(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

660

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

661

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

666

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

667

wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);

drivers/gpu/drm/i915/display/intel_pps.c

670

static void wait_panel_power_cycle(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

672

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

673

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

680

panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time);

drivers/gpu/drm/i915/display/intel_pps.c

682

remaining = max(0, intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration);

drivers/gpu/drm/i915/display/intel_pps.c

687

pps_name(intel_dp), remaining);

drivers/gpu/drm/i915/display/intel_pps.c

694

wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);

drivers/gpu/drm/i915/display/intel_pps.c

697

void intel_pps_wait_power_cycle(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

699

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

70

struct ref_tracker *intel_pps_lock(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

702

with_intel_pps_lock(intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

703

wait_panel_power_cycle(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

706

static void wait_backlight_on(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

708

wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on,

drivers/gpu/drm/i915/display/intel_pps.c

709

intel_dp->pps.backlight_on_delay);

drivers/gpu/drm/i915/display/intel_pps.c

712

static void edp_wait_backlight_off(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

714

wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off,

drivers/gpu/drm/i915/display/intel_pps.c

715

intel_dp->pps.backlight_off_delay);

drivers/gpu/drm/i915/display/intel_pps.c

72

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

722

static u32 ilk_get_pp_control(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

724

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

729

control = intel_de_read(display, _pp_ctrl_reg(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

743

bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

745

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

746

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

749

bool need_to_disable = !intel_dp->pps.want_panel_vdd;

drivers/gpu/drm/i915/display/intel_pps.c

751

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

756

cancel_delayed_work(&intel_dp->pps.panel_vdd_work);

drivers/gpu/drm/i915/display/intel_pps.c

757

intel_dp->pps.want_panel_vdd = true;

drivers/gpu/drm/i915/display/intel_pps.c

759

if (edp_have_panel_vdd(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

762

drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);

drivers/gpu/drm/i915/display/intel_pps.c

763

intel_dp->pps.vdd_wakeref = intel_display_power_get(display,

drivers/gpu/drm/i915/display/intel_pps.c

766

pp_stat_reg = _pp_stat_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

767

pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

771

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

773

if (!edp_have_panel_power(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

774

wait_panel_power_cycle(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

776

pp = ilk_get_pp_control(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

784

pps_name(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

790

if (!edp_have_panel_power(intel_dp)) {

drivers/gpu/drm/i915/display/intel_pps.c

794

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

795

msleep(intel_dp->pps.panel_power_up_delay);

drivers/gpu/drm/i915/display/intel_pps.c

808

void intel_pps_vdd_on(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

810

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

813

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

817

with_intel_pps_lock(intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

818

vdd = intel_pps_vdd_on_unlocked(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

820

dp_to_dig_port(intel_dp)->base.base.base.id,

drivers/gpu/drm/i915/display/intel_pps.c

821

dp_to_dig_port(intel_dp)->base.base.name,

drivers/gpu/drm/i915/display/intel_pps.c

822

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

825

static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

827

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

828

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

834

drm_WARN_ON(display->drm, intel_dp->pps.want_panel_vdd);

drivers/gpu/drm/i915/display/intel_pps.c

836

if (!edp_have_panel_vdd(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

84

struct ref_tracker *intel_pps_unlock(struct intel_dp *intel_dp, struct ref_tracker *wakeref)

drivers/gpu/drm/i915/display/intel_pps.c

841

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

843

pp = ilk_get_pp_control(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

846

pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

847

pp_stat_reg = _pp_stat_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

856

pps_name(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

86

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

861

intel_dp->pps.panel_power_off_time = ktime_get_boottime();

drivers/gpu/drm/i915/display/intel_pps.c

862

intel_dp_invalidate_source_oui(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

867

fetch_and_zero(&intel_dp->pps.vdd_wakeref));

drivers/gpu/drm/i915/display/intel_pps.c

870

void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

872

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

875

cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work);

drivers/gpu/drm/i915/display/intel_pps.c

880

with_intel_pps_lock(intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

881

intel_pps_vdd_off_sync_unlocked(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

888

struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps);

drivers/gpu/drm/i915/display/intel_pps.c

890

with_intel_pps_lock(intel_dp) {

drivers/gpu/drm/i915/display/intel_pps.c

891

if (!intel_dp->pps.want_panel_vdd)

drivers/gpu/drm/i915/display/intel_pps.c

892

intel_pps_vdd_off_sync_unlocked(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

896

static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

898

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

905

if (intel_dp->pps.initializing)

drivers/gpu/drm/i915/display/intel_pps.c

913

delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5);

drivers/gpu/drm/i915/display/intel_pps.c

915

&intel_dp->pps.panel_vdd_work, delay);

drivers/gpu/drm/i915/display/intel_pps.c

923

void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)

drivers/gpu/drm/i915/display/intel_pps.c

925

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

927

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

932

INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd,

drivers/gpu/drm/i915/display/intel_pps.c

934

dp_to_dig_port(intel_dp)->base.base.base.id,

drivers/gpu/drm/i915/display/intel_pps.c

935

dp_to_dig_port(intel_dp)->base.base.name,

drivers/gpu/drm/i915/display/intel_pps.c

936

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

938

intel_dp->pps.want_panel_vdd = false;

drivers/gpu/drm/i915/display/intel_pps.c

941

intel_pps_vdd_off_sync_unlocked(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

943

edp_panel_vdd_schedule_off(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

946

void intel_pps_vdd_off(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

948

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

95

vlv_power_sequencer_kick(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

951

with_intel_pps_lock(intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

952

intel_pps_vdd_off_unlocked(intel_dp, false);

drivers/gpu/drm/i915/display/intel_pps.c

955

void intel_pps_on_unlocked(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_pps.c

957

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

963

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_pps.c

967

dp_to_dig_port(intel_dp)->base.base.base.id,

drivers/gpu/drm/i915/display/intel_pps.c

968

dp_to_dig_port(intel_dp)->base.base.name,

drivers/gpu/drm/i915/display/intel_pps.c

969

pps_name(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

97

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

971

if (drm_WARN(display->drm, edp_have_panel_power(intel_dp),

drivers/gpu/drm/i915/display/intel_pps.c

973

dp_to_dig_port(intel_dp)->base.base.base.id,

drivers/gpu/drm/i915/display/intel_pps.c

974

dp_to_dig_port(intel_dp)->base.base.name,

drivers/gpu/drm/i915/display/intel_pps.c

975

pps_name(intel_dp)))

drivers/gpu/drm/i915/display/intel_pps.c

978

wait_panel_power_cycle(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

98

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

980

pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

981

pp = ilk_get_pp_control(intel_dp);

drivers/gpu/drm/i915/display/intel_pps.c

99

enum pipe pipe = intel_dp->pps.vlv_pps_pipe;

drivers/gpu/drm/i915/display/intel_pps.h

15

struct intel_dp;

drivers/gpu/drm/i915/display/intel_pps.h

19

struct ref_tracker *intel_pps_lock(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

20

struct ref_tracker *intel_pps_unlock(struct intel_dp *intel_dp, struct ref_tracker *wakeref);

drivers/gpu/drm/i915/display/intel_pps.h

28

void intel_pps_backlight_on(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

29

void intel_pps_backlight_off(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

32

bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

33

void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync);

drivers/gpu/drm/i915/display/intel_pps.h

34

void intel_pps_on_unlocked(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

35

void intel_pps_off_unlocked(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

36

void intel_pps_check_power_unlocked(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

38

void intel_pps_vdd_on(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

39

void intel_pps_vdd_off(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

40

void intel_pps_on(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

41

void intel_pps_off(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

42

void intel_pps_vdd_off_sync(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

43

bool intel_pps_have_panel_power_or_vdd(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

44

void intel_pps_wait_power_cycle(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

46

bool intel_pps_init(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

47

void intel_pps_init_late(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

48

void intel_pps_encoder_reset(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

50

void vlv_pps_pipe_init(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

51

void vlv_pps_pipe_reset(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_pps.h

52

enum pipe vlv_pps_backlight_initial_pipe(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1004

static int psr2_block_count(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

1006

return psr2_block_count_lines(intel_dp->psr.io_wake_lines,

drivers/gpu/drm/i915/display/intel_psr.c

1007

intel_dp->psr.fast_wake_lines) / 4;

drivers/gpu/drm/i915/display/intel_psr.c

1010

static u8 frames_before_su_entry(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

1012

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_psr.c

1020

if (intel_dp->psr.entry_setup_frames >= frames_before_su_entry)

drivers/gpu/drm/i915/display/intel_psr.c

1021

frames_before_su_entry = intel_dp->psr.entry_setup_frames + 1;

drivers/gpu/drm/i915/display/intel_psr.c

1026

static void dg2_activate_panel_replay(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

1028

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1029

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

1030

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

1032

if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

1036

if (intel_dp->psr.req_psr2_sdp_prior_scanline)

drivers/gpu/drm/i915/display/intel_psr.c

1044

PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

1047

intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,

drivers/gpu/drm/i915/display/intel_psr.c

1051

static void hsw_activate_psr2(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

1053

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1054

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

1062

is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)

drivers/gpu/drm/i915/display/intel_psr.c

1065

idle_frames = psr_compute_idle_frames(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1074

val |= EDP_PSR2_FRAME_BEFORE_SU(frames_before_su_entry(intel_dp));

drivers/gpu/drm/i915/display/intel_psr.c

1076

val |= intel_psr2_get_tp_time(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1079

if (psr2_block_count(intel_dp) > 2)

drivers/gpu/drm/i915/display/intel_psr.c

1103

tmp = map[intel_dp->psr.io_wake_lines -

drivers/gpu/drm/i915/display/intel_psr.c

1107

tmp = map[intel_dp->psr.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];

drivers/gpu/drm/i915/display/intel_psr.c

1110

val |= LNL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines);

drivers/gpu/drm/i915/display/intel_psr.c

1112

val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines);

drivers/gpu/drm/i915/display/intel_psr.c

1113

val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines);

drivers/gpu/drm/i915/display/intel_psr.c

1115

val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines);

drivers/gpu/drm/i915/display/intel_psr.c

1116

val |= EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines);

drivers/gpu/drm/i915/display/intel_psr.c

1119

if (intel_dp->psr.req_psr2_sdp_prior_scanline)

drivers/gpu/drm/i915/display/intel_psr.c

1123

psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames);

drivers/gpu/drm/i915/display/intel_psr.c

1125

if (intel_dp->psr.psr2_sel_fetch_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

1136

if (intel_dp->psr.su_region_et_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

1170

static void psr2_program_idle_frames(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1173

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1174

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

1181

static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

1183

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1185

psr2_program_idle_frames(intel_dp, 0);

drivers/gpu/drm/i915/display/intel_psr.c

1189

static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

1191

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1194

psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp));

drivers/gpu/drm/i915/display/intel_psr.c

1199

struct intel_dp *intel_dp =

drivers/gpu/drm/i915/display/intel_psr.c

1200

container_of(work, typeof(*intel_dp), psr.dc3co_work.work);

drivers/gpu/drm/i915/display/intel_psr.c

1202

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

1204

if (delayed_work_pending(&intel_dp->psr.dc3co_work))

drivers/gpu/drm/i915/display/intel_psr.c

1207

tgl_psr2_disable_dc3co(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1209

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

1212

static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

1214

if (!intel_dp->psr.dc3co_exitline)

drivers/gpu/drm/i915/display/intel_psr.c

1217

cancel_delayed_work(&intel_dp->psr.dc3co_work);

drivers/gpu/drm/i915/display/intel_psr.c

1219

tgl_psr2_disable_dc3co(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1223

dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1226

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1227

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1238

tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1241

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1263

if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_psr.c

1283

static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1286

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1289

intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {

drivers/gpu/drm/i915/display/intel_psr.c

1301

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_psr.c

1302

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1353

static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1356

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1370

if (DISPLAY_VER(display) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b)

drivers/gpu/drm/i915/display/intel_psr.c

1377

static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1381

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1470

static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1476

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1505

static bool alpm_config_valid(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1511

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1513

if (!intel_alpm_compute_params(intel_dp, crtc_state)) {

drivers/gpu/drm/i915/display/intel_psr.c

1519

if (!wake_lines_fit_into_vblank(intel_dp, crtc_state, aux_less,

drivers/gpu/drm/i915/display/intel_psr.c

1529

static bool intel_psr2_config_valid(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1533

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1614

if (!alpm_config_valid(intel_dp, crtc_state, false, false, true))

drivers/gpu/drm/i915/display/intel_psr.c

1626

tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

1635

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_psr.c

1636

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1639

!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&

drivers/gpu/drm/i915/display/intel_psr.c

1646

if (!sel_update_global_enabled(intel_dp)) {

drivers/gpu/drm/i915/display/intel_psr.c

1652

if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state,

drivers/gpu/drm/i915/display/intel_psr.c

1656

if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) {

drivers/gpu/drm/i915/display/intel_psr.c

1700

static bool _psr_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1704

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1708

if (!CAN_PSR(intel_dp) || !display->params.enable_psr)

drivers/gpu/drm/i915/display/intel_psr.c

1717

entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, conn_state, adjusted_mode);

drivers/gpu/drm/i915/display/intel_psr.c

1748

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_psr.c

1749

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1752

if (!CAN_PANEL_REPLAY(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

1758

if (!panel_replay_global_enabled(intel_dp)) {

drivers/gpu/drm/i915/display/intel_psr.c

1780

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

1807

if (!alpm_config_valid(intel_dp, crtc_state, true, true, false))

drivers/gpu/drm/i915/display/intel_psr.c

1813

static bool intel_psr_needs_wa_18037818876(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1816

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1823

void intel_psr_set_non_psr_pipes(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1826

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1850

void intel_psr_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1854

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1858

if (!psr_global_enabled(intel_dp)) {

drivers/gpu/drm/i915/display/intel_psr.c

1863

if (intel_dp->psr.sink_not_reliable) {

drivers/gpu/drm/i915/display/intel_psr.c

1891

_psr_compute_config(intel_dp, crtc_state, conn_state);

drivers/gpu/drm/i915/display/intel_psr.c

1905

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_psr.c

1911

intel_dp = &dig_port->dp;

drivers/gpu/drm/i915/display/intel_psr.c

1912

if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp)))

drivers/gpu/drm/i915/display/intel_psr.c

1915

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

1916

if (!intel_dp->psr.enabled)

drivers/gpu/drm/i915/display/intel_psr.c

1919

if (intel_dp->psr.panel_replay_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

1929

pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled;

drivers/gpu/drm/i915/display/intel_psr.c

1932

if (!intel_dp->psr.sel_update_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

1942

pipe_config->enable_psr2_su_region_et = intel_dp->psr.su_region_et_enabled;

drivers/gpu/drm/i915/display/intel_psr.c

1950

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

1953

static void intel_psr_activate(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

1955

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1956

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

1965

drm_WARN_ON(display->drm, intel_dp->psr.active);

drivers/gpu/drm/i915/display/intel_psr.c

1967

drm_WARN_ON(display->drm, !intel_dp->psr.enabled);

drivers/gpu/drm/i915/display/intel_psr.c

1969

lockdep_assert_held(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

1972

if (intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

1973

dg2_activate_panel_replay(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1974

else if (intel_dp->psr.sel_update_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

1975

hsw_activate_psr2(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1977

hsw_activate_psr1(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1979

intel_dp->psr.active = true;

drivers/gpu/drm/i915/display/intel_psr.c

1980

intel_dp->psr.no_psr_reason = NULL;

drivers/gpu/drm/i915/display/intel_psr.c

1987

static void wm_optimization_wa(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

1990

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

1991

enum pipe pipe = intel_dp->psr.pipe;

drivers/gpu/drm/i915/display/intel_psr.c

2012

static void intel_psr_enable_source(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

2015

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2016

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

2024

hsw_psr_setup_aux(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2040

if (DISPLAY_VER(display) < 20 || intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

2043

if (intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_psr.c

207

#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \

drivers/gpu/drm/i915/display/intel_psr.c

2074

psr_irq_control(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

208

(intel_dp)->psr.source_support)

drivers/gpu/drm/i915/display/intel_psr.c

2080

if (intel_dp->psr.dc3co_exitline)

drivers/gpu/drm/i915/display/intel_psr.c

2084

intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE);

drivers/gpu/drm/i915/display/intel_psr.c

2088

intel_dp->psr.psr2_sel_fetch_enabled ?

drivers/gpu/drm/i915/display/intel_psr.c

2095

wm_optimization_wa(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2097

if (intel_dp->psr.sel_update_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

2108

if (!intel_dp->psr.panel_replay_enabled &&

drivers/gpu/drm/i915/display/intel_psr.c

2115

if (!intel_dp->psr.panel_replay_enabled &&

drivers/gpu/drm/i915/display/intel_psr.c

2129

!intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2130

intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true);

drivers/gpu/drm/i915/display/intel_psr.c

2132

intel_alpm_configure(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2135

static bool psr_interrupt_error_check(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

2137

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2138

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

2141

if (intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2153

val &= psr_irq_psr_error_bit_get(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2155

intel_dp->psr.sink_not_reliable = true;

drivers/gpu/drm/i915/display/intel_psr.c

2165

static void intel_psr_enable_locked(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

2168

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2169

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2172

drm_WARN_ON(display->drm, intel_dp->psr.enabled);

drivers/gpu/drm/i915/display/intel_psr.c

2174

intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update;

drivers/gpu/drm/i915/display/intel_psr.c

2175

intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;

drivers/gpu/drm/i915/display/intel_psr.c

2176

intel_dp->psr.busy_frontbuffer_bits = 0;

drivers/gpu/drm/i915/display/intel_psr.c

2177

intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;

drivers/gpu/drm/i915/display/intel_psr.c

2178

intel_dp->psr.transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

2181

intel_dp->psr.dc3co_exit_delay = val;

drivers/gpu/drm/i915/display/intel_psr.c

2182

intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;

drivers/gpu/drm/i915/display/intel_psr.c

2183

intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;

drivers/gpu/drm/i915/display/intel_psr.c

2184

intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et;

drivers/gpu/drm/i915/display/intel_psr.c

2185

intel_dp->psr.psr2_sel_fetch_cff_enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

2186

intel_dp->psr.req_psr2_sdp_prior_scanline =

drivers/gpu/drm/i915/display/intel_psr.c

2188

intel_dp->psr.active_non_psr_pipes = crtc_state->active_non_psr_pipes;

drivers/gpu/drm/i915/display/intel_psr.c

2189

intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used;

drivers/gpu/drm/i915/display/intel_psr.c

2190

intel_dp->psr.io_wake_lines = crtc_state->alpm_state.io_wake_lines;

drivers/gpu/drm/i915/display/intel_psr.c

2191

intel_dp->psr.fast_wake_lines = crtc_state->alpm_state.fast_wake_lines;

drivers/gpu/drm/i915/display/intel_psr.c

2192

intel_dp->psr.entry_setup_frames = crtc_state->entry_setup_frames;

drivers/gpu/drm/i915/display/intel_psr.c

2194

if (!psr_interrupt_error_check(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

2197

if (intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2201

intel_dp->psr.sel_update_enabled ? "2" : "1");

drivers/gpu/drm/i915/display/intel_psr.c

2216

intel_psr_enable_sink(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2218

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

2221

intel_psr_enable_source(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

2222

intel_dp->psr.enabled = true;

drivers/gpu/drm/i915/display/intel_psr.c

2223

intel_dp->psr.pause_counter = 0;

drivers/gpu/drm/i915/display/intel_psr.c

2232

intel_dp->psr.link_ok = true;

drivers/gpu/drm/i915/display/intel_psr.c

2234

intel_psr_activate(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2237

static void intel_psr_exit(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

2239

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2240

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

2243

if (!intel_dp->psr.active) {

drivers/gpu/drm/i915/display/intel_psr.c

2257

if (intel_dp->psr.panel_replay_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

2258

intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

2260

} else if (intel_dp->psr.sel_update_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

2261

tgl_disallow_dc3co_on_psr2_exit(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2271

intel_dp->psr.pkg_c_latency_used)

drivers/gpu/drm/i915/display/intel_psr.c

2273

intel_dp->psr.pipe,

drivers/gpu/drm/i915/display/intel_psr.c

2282

intel_dp->psr.active = false;

drivers/gpu/drm/i915/display/intel_psr.c

2285

static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

2287

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2288

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

2292

if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||

drivers/gpu/drm/i915/display/intel_psr.c

2293

intel_dp->psr.panel_replay_enabled)) {

drivers/gpu/drm/i915/display/intel_psr.c

2307

static void intel_psr_disable_locked(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

2309

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2310

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

2312

lockdep_assert_held(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

2314

if (!intel_dp->psr.enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2317

if (intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2321

intel_dp->psr.sel_update_enabled ? "2" : "1");

drivers/gpu/drm/i915/display/intel_psr.c

2323

intel_psr_exit(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2324

intel_psr_wait_exit_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2332

LATENCY_REPORTING_REMOVED(intel_dp->psr.pipe), 0);

drivers/gpu/drm/i915/display/intel_psr.c

2334

if (intel_dp->psr.sel_update_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

2336

if (!intel_dp->psr.panel_replay_enabled &&

drivers/gpu/drm/i915/display/intel_psr.c

2346

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

2347

intel_snps_phy_update_psr_power_state(&dp_to_dig_port(intel_dp)->base, false);

drivers/gpu/drm/i915/display/intel_psr.c

2349

if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

2350

intel_alpm_disable(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2353

if (!intel_dp->psr.panel_replay_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

2354

drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);

drivers/gpu/drm/i915/display/intel_psr.c

2356

if (intel_dp->psr.sel_update_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2357

drm_dp_dpcd_writeb(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_psr.c

2364

!intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2365

intel_dmc_block_pkgc(display, intel_dp->psr.pipe, false);

drivers/gpu/drm/i915/display/intel_psr.c

2367

intel_dp->psr.enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

2368

intel_dp->psr.panel_replay_enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

2369

intel_dp->psr.sel_update_enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

2370

intel_dp->psr.psr2_sel_fetch_enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

2371

intel_dp->psr.su_region_et_enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

2372

intel_dp->psr.psr2_sel_fetch_cff_enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

2373

intel_dp->psr.active_non_psr_pipes = 0;

drivers/gpu/drm/i915/display/intel_psr.c

2374

intel_dp->psr.pkg_c_latency_used = 0;

drivers/gpu/drm/i915/display/intel_psr.c

238

static bool psr_global_enabled(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

2384

void intel_psr_disable(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

2387

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2392

if (drm_WARN_ON(display->drm, !CAN_PSR(intel_dp) &&

drivers/gpu/drm/i915/display/intel_psr.c

2393

!CAN_PANEL_REPLAY(intel_dp)))

drivers/gpu/drm/i915/display/intel_psr.c

2396

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

2398

intel_psr_disable_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

240

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_psr.c

2400

intel_dp->psr.link_ok = false;

drivers/gpu/drm/i915/display/intel_psr.c

2402

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

2403

cancel_work_sync(&intel_dp->psr.work);

drivers/gpu/drm/i915/display/intel_psr.c

2404

cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);

drivers/gpu/drm/i915/display/intel_psr.c

2413

void intel_psr_pause(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

2415

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

2417

if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

242

switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {

drivers/gpu/drm/i915/display/intel_psr.c

2427

if (intel_dp->psr.pause_counter++ == 0) {

drivers/gpu/drm/i915/display/intel_psr.c

2428

intel_psr_exit(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2429

intel_psr_wait_exit_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

244

return intel_dp_is_edp(intel_dp) ?

drivers/gpu/drm/i915/display/intel_psr.c

2444

void intel_psr_resume(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

2446

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2447

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

2449

if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

2462

if (--intel_dp->psr.pause_counter == 0)

drivers/gpu/drm/i915/display/intel_psr.c

2463

intel_psr_activate(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2487

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_psr.c

2492

intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

2494

if (!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

2497

if (CAN_PANEL_REPLAY(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

2502

CAN_PSR(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

253

static bool sel_update_global_enabled(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

255

switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {

drivers/gpu/drm/i915/display/intel_psr.c

2571

static void intel_psr_force_update(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

2573

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2588

intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0);

drivers/gpu/drm/i915/display/intel_psr.c

2604

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

2607

lockdep_assert_held(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

2609

if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

264

static bool panel_replay_global_enabled(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

266

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

268

return !(intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE) &&

drivers/gpu/drm/i915/display/intel_psr.c

272

static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

274

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

277

EDP_PSR_ERROR(intel_dp->psr.transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

280

static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

282

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

2823

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

2825

if (!intel_dp_is_edp(intel_dp) &&

drivers/gpu/drm/i915/display/intel_psr.c

2826

intel_dp->psr.panel_replay_enabled &&

drivers/gpu/drm/i915/display/intel_psr.c

2827

intel_dp->psr.sel_update_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

285

EDP_PSR_POST_EXIT(intel_dp->psr.transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

288

static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

290

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

293

EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

296

static u32 psr_irq_mask_get(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

298

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

301

EDP_PSR_MASK(intel_dp->psr.transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

3095

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

3096

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

3121

intel_psr_disable_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3124

wm_optimization_wa(intel_dp, new_crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

3160

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

3161

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

3184

intel_psr_enable_locked(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

3187

wm_optimization_wa(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

3191

intel_psr_force_update(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3197

intel_dp->psr.busy_frontbuffer_bits = 0;

drivers/gpu/drm/i915/display/intel_psr.c

3273

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

3276

lockdep_assert_held(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3278

if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3281

if (intel_dp->psr.sel_update_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3306

static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3308

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3309

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

3314

if (!intel_dp->psr.enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3317

if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||

drivers/gpu/drm/i915/display/intel_psr.c

3318

intel_dp->psr.panel_replay_enabled)) {

drivers/gpu/drm/i915/display/intel_psr.c

3326

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3334

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3335

return err == 0 && intel_dp->psr.enabled && !intel_dp->psr.pause_counter;

drivers/gpu/drm/i915/display/intel_psr.c

3401

int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val)

drivers/gpu/drm/i915/display/intel_psr.c

3403

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3418

ret = mutex_lock_interruptible(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3422

old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;

drivers/gpu/drm/i915/display/intel_psr.c

3423

old_disable_bits = intel_dp->psr.debug &

drivers/gpu/drm/i915/display/intel_psr.c

3427

intel_dp->psr.debug = val;

drivers/gpu/drm/i915/display/intel_psr.c

3433

if (intel_dp->psr.enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3434

psr_irq_control(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3436

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3444

static void intel_psr_handle_irq(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3446

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

3448

intel_psr_disable_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3451

drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);

drivers/gpu/drm/i915/display/intel_psr.c

3456

struct intel_dp *intel_dp =

drivers/gpu/drm/i915/display/intel_psr.c

3457

container_of(work, typeof(*intel_dp), psr.work);

drivers/gpu/drm/i915/display/intel_psr.c

3459

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3461

if (!intel_dp->psr.enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3464

if (READ_ONCE(intel_dp->psr.irq_aux_error)) {

drivers/gpu/drm/i915/display/intel_psr.c

3465

intel_psr_handle_irq(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3469

if (intel_dp->psr.pause_counter)

drivers/gpu/drm/i915/display/intel_psr.c

3478

if (!__psr_wait_for_idle_locked(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

3486

if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active)

drivers/gpu/drm/i915/display/intel_psr.c

3489

intel_psr_activate(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3491

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3494

static void intel_psr_configure_full_frame_update(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3496

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3497

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

3499

if (!intel_dp->psr.psr2_sel_fetch_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3514

static void _psr_invalidate_handle(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3516

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3518

if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3519

if (!intel_dp->psr.psr2_sel_fetch_cff_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3520

intel_dp->psr.psr2_sel_fetch_cff_enabled = true;

drivers/gpu/drm/i915/display/intel_psr.c

3521

intel_psr_configure_full_frame_update(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3524

intel_psr_force_update(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3526

intel_psr_exit(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3553

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

3555

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3556

if (!intel_dp->psr.enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3557

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3562

INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);

drivers/gpu/drm/i915/display/intel_psr.c

3563

intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits;

drivers/gpu/drm/i915/display/intel_psr.c

3566

_psr_invalidate_handle(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3568

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3578

tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,

drivers/gpu/drm/i915/display/intel_psr.c

3581

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3583

if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.sel_update_enabled ||

drivers/gpu/drm/i915/display/intel_psr.c

3584

!intel_dp->psr.active)

drivers/gpu/drm/i915/display/intel_psr.c

3592

INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))

drivers/gpu/drm/i915/display/intel_psr.c

3595

tgl_psr2_enable_dc3co(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3596

mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work,

drivers/gpu/drm/i915/display/intel_psr.c

3597

intel_dp->psr.dc3co_exit_delay);

drivers/gpu/drm/i915/display/intel_psr.c

3600

static void _psr_flush_handle(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3602

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3604

if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3606

if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3608

if (intel_dp->psr.busy_frontbuffer_bits == 0)

drivers/gpu/drm/i915/display/intel_psr.c

3609

intel_dp->psr.psr2_sel_fetch_cff_enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

3621

intel_psr_configure_full_frame_update(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3623

intel_psr_force_update(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3624

} else if (!intel_dp->psr.psr2_sel_fetch_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3630

intel_psr_force_update(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3633

intel_psr_exit(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3636

if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)

drivers/gpu/drm/i915/display/intel_psr.c

3637

queue_work(display->wq.unordered, &intel_dp->psr.work);

drivers/gpu/drm/i915/display/intel_psr.c

3660

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

3662

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3663

if (!intel_dp->psr.enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3664

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3669

INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);

drivers/gpu/drm/i915/display/intel_psr.c

3670

intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits;

drivers/gpu/drm/i915/display/intel_psr.c

3677

if (intel_dp->psr.pause_counter)

drivers/gpu/drm/i915/display/intel_psr.c

3682

!intel_dp->psr.psr2_sel_fetch_enabled)) {

drivers/gpu/drm/i915/display/intel_psr.c

3683

tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin);

drivers/gpu/drm/i915/display/intel_psr.c

3691

_psr_flush_handle(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3693

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3705

void intel_psr_init(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3707

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3708

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_psr.c

3709

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3729

if ((HAS_DP20(display) && !intel_dp_is_edp(intel_dp)) ||

drivers/gpu/drm/i915/display/intel_psr.c

3731

intel_dp->psr.source_panel_replay_support = true;

drivers/gpu/drm/i915/display/intel_psr.c

3733

if (HAS_PSR(display) && intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

3734

intel_dp->psr.source_support = true;

drivers/gpu/drm/i915/display/intel_psr.c

3739

intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;

drivers/gpu/drm/i915/display/intel_psr.c

3741

INIT_WORK(&intel_dp->psr.work, intel_psr_work);

drivers/gpu/drm/i915/display/intel_psr.c

3742

INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);

drivers/gpu/drm/i915/display/intel_psr.c

3743

mutex_init(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3746

static int psr_get_status_and_error_status(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

3749

struct drm_dp_aux *aux = &intel_dp->aux;

drivers/gpu/drm/i915/display/intel_psr.c

3753

offset = intel_dp->psr.panel_replay_enabled ?

drivers/gpu/drm/i915/display/intel_psr.c

376

static void psr_irq_control(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3760

offset = intel_dp->psr.panel_replay_enabled ?

drivers/gpu/drm/i915/display/intel_psr.c

3772

static void psr_alpm_check(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3774

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

3779

if (intel_alpm_get_error(intel_dp)) {

drivers/gpu/drm/i915/display/intel_psr.c

378

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3780

intel_psr_disable_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3785

static void psr_capability_changed_check(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3787

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3788

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

379

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

3792

r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val);

drivers/gpu/drm/i915/display/intel_psr.c

3799

intel_psr_disable_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3805

drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val);

drivers/gpu/drm/i915/display/intel_psr.c

3816

void intel_psr_short_pulse(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3818

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3819

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

382

if (intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3825

if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

3835

if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) {

drivers/gpu/drm/i915/display/intel_psr.c

3843

intel_psr_disable_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

385

mask = psr_irq_psr_error_bit_get(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

386

if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)

drivers/gpu/drm/i915/display/intel_psr.c

3866

drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);

drivers/gpu/drm/i915/display/intel_psr.c

3869

psr_alpm_check(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

387

mask |= psr_irq_post_exit_bit_get(intel_dp) |

drivers/gpu/drm/i915/display/intel_psr.c

3870

psr_capability_changed_check(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3877

bool intel_psr_enabled(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

388

psr_irq_pre_entry_bit_get(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3881

if (!CAN_PSR(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

3884

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3885

ret = intel_dp->psr.enabled;

drivers/gpu/drm/i915/display/intel_psr.c

3886

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3903

bool intel_psr_link_ok(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3907

if ((!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) ||

drivers/gpu/drm/i915/display/intel_psr.c

3908

!intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

391

psr_irq_mask_get(intel_dp), ~mask);

drivers/gpu/drm/i915/display/intel_psr.c

3911

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3912

ret = intel_dp->psr.link_ok;

drivers/gpu/drm/i915/display/intel_psr.c

3913

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3936

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

3938

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3959

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

3961

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3967

static void intel_psr_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

3969

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3972

if (!intel_dp->psr.active || !intel_dp->psr.pkg_c_latency_used)

drivers/gpu/drm/i915/display/intel_psr.c

3975

dc5_dc6_blocked = is_dc5_dc6_blocked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

3977

if (intel_dp->psr.sel_update_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3978

psr2_program_idle_frames(intel_dp, dc5_dc6_blocked ? 0 :

drivers/gpu/drm/i915/display/intel_psr.c

3979

psr_compute_idle_frames(intel_dp));

drivers/gpu/drm/i915/display/intel_psr.c

3982

intel_dp->psr.pipe,

drivers/gpu/drm/i915/display/intel_psr.c

3993

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

3995

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3997

if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled &&

drivers/gpu/drm/i915/display/intel_psr.c

3998

!intel_dp->psr.pkg_c_latency_used)

drivers/gpu/drm/i915/display/intel_psr.c

3999

intel_psr_apply_underrun_on_idle_wa_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

4001

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4057

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

4060

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4062

if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

4065

active_non_psr_pipes = intel_dp->psr.active_non_psr_pipes;

drivers/gpu/drm/i915/display/intel_psr.c

4072

if (active_non_psr_pipes == intel_dp->psr.active_non_psr_pipes)

drivers/gpu/drm/i915/display/intel_psr.c

4075

if ((enable && intel_dp->psr.active_non_psr_pipes) ||

drivers/gpu/drm/i915/display/intel_psr.c

4076

(!enable && !intel_dp->psr.active_non_psr_pipes) ||

drivers/gpu/drm/i915/display/intel_psr.c

4077

!intel_dp->psr.pkg_c_latency_used) {

drivers/gpu/drm/i915/display/intel_psr.c

4078

intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes;

drivers/gpu/drm/i915/display/intel_psr.c

4082

intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes;

drivers/gpu/drm/i915/display/intel_psr.c

4084

intel_psr_apply_underrun_on_idle_wa_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

4086

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4104

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

4106

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4107

if (intel_dp->psr.panel_replay_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

4108

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4112

if (intel_dp->psr.enabled && intel_dp->psr.pkg_c_latency_used)

drivers/gpu/drm/i915/display/intel_psr.c

4113

intel_psr_apply_underrun_on_idle_wa_locked(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

4115

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4131

psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)

drivers/gpu/drm/i915/display/intel_psr.c

4133

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

4134

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

4138

if ((intel_dp_is_edp(intel_dp) || DISPLAY_VER(display) >= 30) &&

drivers/gpu/drm/i915/display/intel_psr.c

4139

(intel_dp->psr.sel_update_enabled || intel_dp->psr.panel_replay_enabled)) {

drivers/gpu/drm/i915/display/intel_psr.c

4200

static void intel_psr_print_mode(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

4203

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

4232

static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

4235

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

4236

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

4237

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

4250

intel_psr_print_mode(intel_dp, m);

drivers/gpu/drm/i915/display/intel_psr.c

4262

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

4278

if (psr->panel_replay_enabled && intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

4281

psr_source_status(intel_dp, m);

drivers/gpu/drm/i915/display/intel_psr.c

432

void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)

drivers/gpu/drm/i915/display/intel_psr.c

434

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

4343

struct intel_dp *intel_dp = NULL;

drivers/gpu/drm/i915/display/intel_psr.c

435

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

4351

intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

4355

if (!intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

4358

return intel_psr_status(m, intel_dp, intel_dp->attached_connector);

drivers/gpu/drm/i915/display/intel_psr.c

4373

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

4379

ret = intel_psr_debug_set(intel_dp, val);

drivers/gpu/drm/i915/display/intel_psr.c

438

if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) {

drivers/gpu/drm/i915/display/intel_psr.c

439

intel_dp->psr.last_entry_attempt = time_ns;

drivers/gpu/drm/i915/display/intel_psr.c

4395

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_psr.c

4398

*val = READ_ONCE(intel_dp->psr.debug);

drivers/gpu/drm/i915/display/intel_psr.c

4420

static const char *psr_mode_str(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

4422

if (intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

4424

else if (intel_dp->psr.enabled)

drivers/gpu/drm/i915/display/intel_psr.c

4433

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_psr.c

4448

if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) {

drivers/gpu/drm/i915/display/intel_psr.c

445

if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) {

drivers/gpu/drm/i915/display/intel_psr.c

4456

ret = psr_get_status_and_error_status(intel_dp, &status, &error_status);

drivers/gpu/drm/i915/display/intel_psr.c

446

intel_dp->psr.last_exit = time_ns;

drivers/gpu/drm/i915/display/intel_psr.c

4466

seq_printf(m, "Sink %s status: 0x%x [%s]\n", psr_mode_str(intel_dp), status, str);

drivers/gpu/drm/i915/display/intel_psr.c

4468

seq_printf(m, "Sink %s error status: 0x%x", psr_mode_str(intel_dp), error_status);

drivers/gpu/drm/i915/display/intel_psr.c

4477

seq_printf(m, "\t%s RFB storage error\n", psr_mode_str(intel_dp));

drivers/gpu/drm/i915/display/intel_psr.c

4479

seq_printf(m, "\t%s VSC SDP uncorrectable error\n", psr_mode_str(intel_dp));

drivers/gpu/drm/i915/display/intel_psr.c

4481

seq_printf(m, "\t%s Link CRC error\n", psr_mode_str(intel_dp));

drivers/gpu/drm/i915/display/intel_psr.c

4490

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_psr.c

4492

return intel_psr_status(m, intel_dp, connector);

drivers/gpu/drm/i915/display/intel_psr.c

4513

bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/intel_psr.c

4519

return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update ||

drivers/gpu/drm/i915/display/intel_psr.c

4523

bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

4526

return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay;

drivers/gpu/drm/i915/display/intel_psr.c

4529

void intel_psr_compute_config_late(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

4532

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

4536

if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_psr.c

4538

else if (intel_psr_needs_alpm(intel_dp, crtc_state))

drivers/gpu/drm/i915/display/intel_psr.c

4574

if (intel_psr_needs_wa_18037818876(intel_dp, crtc_state)) {

drivers/gpu/drm/i915/display/intel_psr.c

458

psr_event_print(display, val, intel_dp->psr.sel_update_enabled);

drivers/gpu/drm/i915/display/intel_psr.c

4580

intel_psr_set_non_psr_pipes(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

462

if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) {

drivers/gpu/drm/i915/display/intel_psr.c

466

intel_dp->psr.irq_aux_error = true;

drivers/gpu/drm/i915/display/intel_psr.c

477

0, psr_irq_psr_error_bit_get(intel_dp));

drivers/gpu/drm/i915/display/intel_psr.c

479

queue_work(display->wq.unordered, &intel_dp->psr.work);

drivers/gpu/drm/i915/display/intel_psr.c

483

static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

485

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

488

if (drm_dp_dpcd_readb(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_psr.c

497

static void _psr_compute_su_granularity(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

500

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

516

r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, sizeof(w));

drivers/gpu/drm/i915/display/intel_psr.c

527

r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1);

drivers/gpu/drm/i915/display/intel_psr.c

603

static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)

drivers/gpu/drm/i915/display/intel_psr.c

605

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

609

if (intel_dp->mst_detect == DRM_DP_MST)

drivers/gpu/drm/i915/display/intel_psr.c

612

ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT,

drivers/gpu/drm/i915/display/intel_psr.c

622

if (intel_dp_is_edp(intel_dp)) {

drivers/gpu/drm/i915/display/intel_psr.c

623

if (!intel_alpm_aux_less_wake_supported(intel_dp)) {

drivers/gpu/drm/i915/display/intel_psr.c

638

intel_dp->psr.sink_panel_replay_support = true;

drivers/gpu/drm/i915/display/intel_psr.c

656

static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)

drivers/gpu/drm/i915/display/intel_psr.c

658

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

661

ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, connector->dp.psr_caps.dpcd,

drivers/gpu/drm/i915/display/intel_psr.c

672

if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {

drivers/gpu/drm/i915/display/intel_psr.c

678

if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {

drivers/gpu/drm/i915/display/intel_psr.c

685

intel_dp->psr.sink_support = true;

drivers/gpu/drm/i915/display/intel_psr.c

687

connector->dp.psr_caps.sync_latency = intel_dp_get_sink_sync_latency(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

706

intel_alpm_aux_wake_supported(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

712

_psr_compute_su_granularity(intel_dp, connector);

drivers/gpu/drm/i915/display/intel_psr.c

715

void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)

drivers/gpu/drm/i915/display/intel_psr.c

717

_psr_init_dpcd(intel_dp, connector);

drivers/gpu/drm/i915/display/intel_psr.c

719

_panel_replay_init_dpcd(intel_dp, connector);

drivers/gpu/drm/i915/display/intel_psr.c

722

static void hsw_psr_setup_aux(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

724

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

725

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

743

aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);

drivers/gpu/drm/i915/display/intel_psr.c

746

aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg),

drivers/gpu/drm/i915/display/intel_psr.c

761

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_psr.c

762

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

764

if (DISPLAY_VER(display) < 20 || !intel_dp_is_edp(intel_dp) ||

drivers/gpu/drm/i915/display/intel_psr.c

765

intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE)

drivers/gpu/drm/i915/display/intel_psr.c

774

static void _panel_replay_enable_sink(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

794

drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val);

drivers/gpu/drm/i915/display/intel_psr.c

796

drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2,

drivers/gpu/drm/i915/display/intel_psr.c

800

static void _psr_enable_sink(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

803

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

809

if (intel_dp->psr.link_standby)

drivers/gpu/drm/i915/display/intel_psr.c

822

if (intel_dp->psr.entry_setup_frames > 0)

drivers/gpu/drm/i915/display/intel_psr.c

824

drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);

drivers/gpu/drm/i915/display/intel_psr.c

827

drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);

drivers/gpu/drm/i915/display/intel_psr.c

830

static void intel_psr_enable_sink(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.c

833

intel_alpm_enable_sink(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

836

_panel_replay_enable_sink(intel_dp, crtc_state) :

drivers/gpu/drm/i915/display/intel_psr.c

837

_psr_enable_sink(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_psr.c

839

if (intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

840

drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);

drivers/gpu/drm/i915/display/intel_psr.c

843

void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

850

if (CAN_PANEL_REPLAY(intel_dp) && panel_replay_global_enabled(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

851

drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,

drivers/gpu/drm/i915/display/intel_psr.c

855

static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

857

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

858

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_psr.c

899

drm_dp_tps3_supported(intel_dp->dpcd))

drivers/gpu/drm/i915/display/intel_psr.c

907

static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

909

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

910

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_psr.c

925

static bool is_dc5_dc6_blocked(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

927

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

929

struct intel_crtc *crtc = intel_crtc_for_pipe(display, intel_dp->psr.pipe);

drivers/gpu/drm/i915/display/intel_psr.c

934

intel_dp->psr.active_non_psr_pipes ||

drivers/gpu/drm/i915/display/intel_psr.c

938

static void hsw_activate_psr1(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

940

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

941

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

945

val |= EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));

drivers/gpu/drm/i915/display/intel_psr.c

953

if (intel_dp->psr.link_standby)

drivers/gpu/drm/i915/display/intel_psr.c

956

val |= intel_psr1_get_tp_time(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

962

val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames);

drivers/gpu/drm/i915/display/intel_psr.c

970

is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)

drivers/gpu/drm/i915/display/intel_psr.c

972

intel_dp->psr.pipe,

drivers/gpu/drm/i915/display/intel_psr.c

976

static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_psr.c

978

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_psr.c

979

struct intel_connector *connector = intel_dp->attached_connector;

drivers/gpu/drm/i915/display/intel_psr.h

19

struct intel_dp;

drivers/gpu/drm/i915/display/intel_psr.h

25

#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \

drivers/gpu/drm/i915/display/intel_psr.h

26

(intel_dp)->psr.source_panel_replay_support)

drivers/gpu/drm/i915/display/intel_psr.h

31

void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector);

drivers/gpu/drm/i915/display/intel_psr.h

32

void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_psr.h

37

void intel_psr_disable(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.h

39

int intel_psr_debug_set(struct intel_dp *intel_dp, u64 value);

drivers/gpu/drm/i915/display/intel_psr.h

46

void intel_psr_init(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_psr.h

47

void intel_psr_compute_config(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.h

52

void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);

drivers/gpu/drm/i915/display/intel_psr.h

53

void intel_psr_short_pulse(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_psr.h

57

bool intel_psr_enabled(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_psr.h

63

void intel_psr_pause(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_psr.h

64

void intel_psr_resume(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_psr.h

72

bool intel_psr_link_ok(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_psr.h

82

bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state);

drivers/gpu/drm/i915/display/intel_psr.h

83

bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_psr.h

85

void intel_psr_compute_config_late(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_quirks.c

102

void (*hook)(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/intel_quirks.c

19

static void intel_set_dpcd_quirk(struct intel_dp *intel_dp, enum intel_quirk_id quirk)

drivers/gpu/drm/i915/display/intel_quirks.c

21

intel_dp->quirks.mask |= BIT(quirk);

drivers/gpu/drm/i915/display/intel_quirks.c

278

void intel_init_dpcd_quirks(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_quirks.c

281

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_quirks.c

297

q->hook(intel_dp);

drivers/gpu/drm/i915/display/intel_quirks.c

306

bool intel_has_dpcd_quirk(struct intel_dp *intel_dp, enum intel_quirk_id quirk)

drivers/gpu/drm/i915/display/intel_quirks.c

308

return intel_dp->quirks.mask & BIT(quirk);

drivers/gpu/drm/i915/display/intel_quirks.c

75

static void quirk_fw_sync_len(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_quirks.c

77

struct intel_display *display = to_intel_display(intel_dp);

drivers/gpu/drm/i915/display/intel_quirks.c

79

intel_set_dpcd_quirk(intel_dp, QUIRK_FW_SYNC_LEN);

drivers/gpu/drm/i915/display/intel_quirks.h

12

struct intel_dp;

drivers/gpu/drm/i915/display/intel_quirks.h

27

void intel_init_dpcd_quirks(struct intel_dp *intel_dp,

drivers/gpu/drm/i915/display/intel_quirks.h

30

bool intel_has_dpcd_quirk(struct intel_dp *intel_dp, enum intel_quirk_id quirk);

drivers/gpu/drm/i915/display/intel_tc.c

1767

struct intel_dp *intel_dp = enc_to_intel_dp(&dig_port->base);

drivers/gpu/drm/i915/display/intel_tc.c

1776

ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);

drivers/gpu/drm/i915/display/intel_vrr.c

37

struct intel_dp *intel_dp;

drivers/gpu/drm/i915/display/intel_vrr.c

412

struct intel_dp *intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_vrr.c

413

bool is_edp = intel_dp_is_edp(intel_dp);

drivers/gpu/drm/i915/display/intel_vrr.c

56

intel_dp = intel_attached_dp(connector);

drivers/gpu/drm/i915/display/intel_vrr.c

58

if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd))