intel_de_wait_for_clear_ms
if (intel_de_wait_for_clear_ms(display, IPS_CTL, IPS_ENABLE, 100))
if (intel_de_wait_for_clear_ms(display, TRANSCONF(display, dsi_trans),
if (intel_de_wait_for_clear_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
if (intel_de_wait_for_clear_ms(display,
if (intel_de_wait_for_clear_ms(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
if (intel_de_wait_for_clear_ms(display,
if (intel_de_wait_for_clear_ms(display, crt->adpa_reg,
if (intel_de_wait_for_clear_ms(display, PORT_HOTPLUG_EN(display),
if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
if (intel_de_wait_for_clear_ms(display, buf_ctl2_reg,
if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
ret = intel_de_wait_for_clear_ms(display, dp_tp_status_reg(encoder, crtc_state),
if (intel_de_wait_for_clear_ms(display, intel_ddi_buf_status_reg(display, port),
if (intel_de_wait_for_clear_ms(display, TRANSCONF(display, cpu_transcoder),
if (intel_de_wait_for_clear_ms(display, LCPLL_CTL, LCPLL_PLL_LOCK, 1))
if (intel_de_wait_for_clear_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
if (intel_de_wait_for_clear_ms(display, XE2LPD_PICA_PW_CTL,
ret = intel_de_wait_for_clear_ms(display, regs->driver,
if (intel_de_wait_for_clear_ms(display, enable_reg, PLL_LOCK, 1))
if (intel_de_wait_for_clear_ms(display, enable_reg, PLL_POWER_STATE, 1))
if (intel_de_wait_for_clear_ms(display, FBC_STATUS,
intel_de_wait_for_clear_ms(display,
if (intel_de_wait_for_clear_ms(display,
ret = intel_de_wait_for_clear_ms(display,
if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
if (intel_de_wait_for_clear_ms(display, PP_STATUS(display, 0), PP_ON, 1000))
if (intel_de_wait_for_clear_ms(display, PP_STATUS(display, 0), PP_CYCLE_DELAY_ACTIVE, 5000))
if (intel_de_wait_for_clear_ms(display, reg, TRANS_STATE_ENABLE, 50))
if (intel_de_wait_for_clear_ms(display, LPT_TRANSCONF,
return !(intel_de_wait_for_clear_ms(display,
intel_de_wait_for_clear_ms(display,
if (intel_de_wait_for_clear_ms(display, psr_status,
return intel_de_wait_for_clear_ms(display,
return intel_de_wait_for_clear_ms(display,
err = intel_de_wait_for_clear_ms(display, reg, mask, 50);
if (intel_de_wait_for_clear_ms(display, enable_reg, PLL_LOCK, 5))
if (intel_de_wait_for_clear_ms(display, DG2_PHY_MISC(phy),
if (intel_de_wait_for_clear_ms(display, TCSS_DISP_MAILBOX_IN_CMD,
if (intel_de_wait_for_clear_ms(display, TCSS_DISP_MAILBOX_IN_CMD,
if (intel_de_wait_for_clear_ms(display,
if (intel_de_wait_for_clear_ms(display, MIPI_GEN_FIFO_STAT(display, port),
if (intel_de_wait_for_clear_ms(display, MIPI_GEN_FIFO_STAT(display, port),
if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display, port),
if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display, port),
if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display, port),
if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display, port),
intel_de_wait_for_clear_ms(display, port_ctrl,
if (intel_de_wait_for_clear_ms(display, BXT_DSI_PLL_ENABLE,