drivers/gpu/drm/i915/display/g4x_dp.c

1192

return intel_de_read(display, SDEISR) & bit;

drivers/gpu/drm/i915/display/g4x_dp.c

1215

return intel_de_read(display, PORT_HOTPLUG_STAT(display)) & bit;

drivers/gpu/drm/i915/display/g4x_dp.c

1223

return intel_de_read(display, DEISR) & bit;

drivers/gpu/drm/i915/display/g4x_dp.c

125

intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;

drivers/gpu/drm/i915/display/g4x_dp.c

1267

intel_dp->DP = intel_de_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

175

bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN;

drivers/gpu/drm/i915/display/g4x_dp.c

186

bool cur_state = intel_de_read(display, DP_A) & EDP_PLL_ENABLE;

drivers/gpu/drm/i915/display/g4x_dp.c

259

u32 val = intel_de_read(display, TRANS_DP_CTL(p));

drivers/gpu/drm/i915/display/g4x_dp.c

283

val = intel_de_read(display, dp_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

350

tmp = intel_de_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_dp.c

355

u32 trans_dp = intel_de_read(display,

drivers/gpu/drm/i915/display/g4x_dp.c

395

if ((intel_de_read(display, DP_A) & EDP_PLL_FREQ_MASK) == EDP_PLL_FREQ_162MHZ)

drivers/gpu/drm/i915/display/g4x_dp.c

421

(intel_de_read(display, intel_dp->output_reg) &

drivers/gpu/drm/i915/display/g4x_dp.c

686

u32 dp_reg = intel_de_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

160

tmp = intel_de_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

224

temp = intel_de_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

283

temp = intel_de_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

331

temp = intel_de_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/g4x_hdmi.c

387

temp = intel_de_read(display, intel_hdmi->hdmi_reg);

drivers/gpu/drm/i915/display/hsw_ips.c

281

crtc_state->ips_enabled = intel_de_read(display, IPS_CTL) & IPS_ENABLE;

drivers/gpu/drm/i915/display/hsw_ips.c

351

if (intel_de_read(display, IPS_CTL) & IPS_ENABLE)

drivers/gpu/drm/i915/display/i9xx_display_sr.c

22

display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i));

drivers/gpu/drm/i915/display/i9xx_display_sr.c

23

display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i));

drivers/gpu/drm/i915/display/i9xx_display_sr.c

26

display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i));

drivers/gpu/drm/i915/display/i9xx_display_sr.c

29

display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i));

drivers/gpu/drm/i915/display/i9xx_display_sr.c

32

display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i));

drivers/gpu/drm/i915/display/i9xx_display_sr.c

33

display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i));

drivers/gpu/drm/i915/display/i9xx_display_sr.c

36

display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i));

drivers/gpu/drm/i915/display/i9xx_display_sr.c

74

display->restore.saveDSPARB = intel_de_read(display, DSPARB(display));

drivers/gpu/drm/i915/display/i9xx_plane.c

1187

val = intel_de_read(display, DSPCNTR(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

1207

offset = intel_de_read(display,

drivers/gpu/drm/i915/display/i9xx_plane.c

1209

base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK;

drivers/gpu/drm/i915/display/i9xx_plane.c

1212

offset = intel_de_read(display,

drivers/gpu/drm/i915/display/i9xx_plane.c

1215

offset = intel_de_read(display,

drivers/gpu/drm/i915/display/i9xx_plane.c

1217

base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK;

drivers/gpu/drm/i915/display/i9xx_plane.c

1220

base = intel_de_read(display, DSPADDR(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

1226

val = intel_de_read(display, PIPESRC(display, pipe));

drivers/gpu/drm/i915/display/i9xx_plane.c

1230

val = intel_de_read(display, DSPSTRIDE(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

573

error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

574

error->surf = intel_de_read(display, DSPSURF(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

575

error->surflive = intel_de_read(display, DSPSURFLIVE(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

585

error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

586

error->surf = intel_de_read(display, DSPSURF(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

596

error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

597

error->surf = intel_de_read(display, DSPADDR(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_plane.c

740

val = intel_de_read(display, DSPCNTR(display, i9xx_plane));

drivers/gpu/drm/i915/display/i9xx_wm.c

167

was_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;

drivers/gpu/drm/i915/display/i9xx_wm.c

171

was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;

drivers/gpu/drm/i915/display/i9xx_wm.c

175

val = intel_de_read(display, DSPFW3(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

184

was_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;

drivers/gpu/drm/i915/display/i9xx_wm.c

195

was_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;

drivers/gpu/drm/i915/display/i9xx_wm.c

2381

fwater_lo = intel_de_read(display, FW_BLC) & ~0xfff;

drivers/gpu/drm/i915/display/i9xx_wm.c

295

dsparb = intel_de_read(display, DSPARB(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

296

dsparb2 = intel_de_read(display, DSPARB2);

drivers/gpu/drm/i915/display/i9xx_wm.c

301

dsparb = intel_de_read(display, DSPARB(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

302

dsparb2 = intel_de_read(display, DSPARB2);

drivers/gpu/drm/i915/display/i9xx_wm.c

307

dsparb2 = intel_de_read(display, DSPARB2);

drivers/gpu/drm/i915/display/i9xx_wm.c

308

dsparb3 = intel_de_read(display, DSPARB3);

drivers/gpu/drm/i915/display/i9xx_wm.c

326

u32 dsparb = intel_de_read(display, DSPARB(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

342

u32 dsparb = intel_de_read(display, DSPARB(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

3503

hw->wm_pipe[pipe] = intel_de_read(display, WM0_PIPE_ILK(pipe));

drivers/gpu/drm/i915/display/i9xx_wm.c

359

u32 dsparb = intel_de_read(display, DSPARB(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

3669

tmp = intel_de_read(display, DSPFW1(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

3675

tmp = intel_de_read(display, DSPFW2(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

3683

tmp = intel_de_read(display, DSPFW3(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

3697

tmp = intel_de_read(display, VLV_DDL(pipe));

drivers/gpu/drm/i915/display/i9xx_wm.c

3709

tmp = intel_de_read(display, DSPFW1(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

3715

tmp = intel_de_read(display, DSPFW2(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

3720

tmp = intel_de_read(display, DSPFW3(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

3724

tmp = intel_de_read(display, DSPFW7_CHV);

drivers/gpu/drm/i915/display/i9xx_wm.c

3728

tmp = intel_de_read(display, DSPFW8_CHV);

drivers/gpu/drm/i915/display/i9xx_wm.c

3732

tmp = intel_de_read(display, DSPFW9_CHV);

drivers/gpu/drm/i915/display/i9xx_wm.c

3736

tmp = intel_de_read(display, DSPHOWM);

drivers/gpu/drm/i915/display/i9xx_wm.c

3748

tmp = intel_de_read(display, DSPFW7);

drivers/gpu/drm/i915/display/i9xx_wm.c

3752

tmp = intel_de_read(display, DSPHOWM);

drivers/gpu/drm/i915/display/i9xx_wm.c

3773

wm->cxsr = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;

drivers/gpu/drm/i915/display/i9xx_wm.c

3917

wm->cxsr = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;

drivers/gpu/drm/i915/display/i9xx_wm.c

4083

hw->wm_lp[0] = intel_de_read(display, WM1_LP_ILK);

drivers/gpu/drm/i915/display/i9xx_wm.c

4084

hw->wm_lp[1] = intel_de_read(display, WM2_LP_ILK);

drivers/gpu/drm/i915/display/i9xx_wm.c

4085

hw->wm_lp[2] = intel_de_read(display, WM3_LP_ILK);

drivers/gpu/drm/i915/display/i9xx_wm.c

4087

hw->wm_lp_spr[0] = intel_de_read(display, WM1S_LP_ILK);

drivers/gpu/drm/i915/display/i9xx_wm.c

4089

hw->wm_lp_spr[1] = intel_de_read(display, WM2S_LP_IVB);

drivers/gpu/drm/i915/display/i9xx_wm.c

4090

hw->wm_lp_spr[2] = intel_de_read(display, WM3S_LP_IVB);

drivers/gpu/drm/i915/display/i9xx_wm.c

4094

hw->partitioning = (intel_de_read(display, WM_MISC) &

drivers/gpu/drm/i915/display/i9xx_wm.c

4098

hw->partitioning = (intel_de_read(display, DISP_ARB_CTL2) &

drivers/gpu/drm/i915/display/i9xx_wm.c

4103

!(intel_de_read(display, DISP_ARB_CTL) & DISP_FBC_WM_DIS);

drivers/gpu/drm/i915/display/i9xx_wm.c

680

reg = intel_de_read(display, DSPFW1(display));

drivers/gpu/drm/i915/display/i9xx_wm.c

707

reg = intel_de_read(display, DSPFW3(display));

drivers/gpu/drm/i915/display/icl_dsi.c

1119

tmp = intel_de_read(display, UTIL_PIN_CTL);

drivers/gpu/drm/i915/display/icl_dsi.c

1181

tmp = intel_de_read(display, DSI_CMD_RXCTL(dsi_trans));

drivers/gpu/drm/i915/display/icl_dsi.c

1355

tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans));

drivers/gpu/drm/i915/display/icl_dsi.c

1549

val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));

drivers/gpu/drm/i915/display/icl_dsi.c

1604

!(intel_de_read(display, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))

drivers/gpu/drm/i915/display/icl_dsi.c

1737

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/icl_dsi.c

1757

tmp = intel_de_read(display, TRANSCONF(display, dsi_trans));

drivers/gpu/drm/i915/display/icl_dsi.c

202

tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans));

drivers/gpu/drm/i915/display/icl_dsi.c

266

tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

drivers/gpu/drm/i915/display/icl_dsi.c

276

tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));

drivers/gpu/drm/i915/display/icl_dsi.c

314

dss_ctl1 = intel_de_read(display, dss_ctl1_reg);

drivers/gpu/drm/i915/display/icl_dsi.c

461

tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));

drivers/gpu/drm/i915/display/icl_dsi.c

472

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/icl_dsi.c

492

tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));

drivers/gpu/drm/i915/display/icl_dsi.c

509

tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

drivers/gpu/drm/i915/display/icl_dsi.c

520

tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

drivers/gpu/drm/i915/display/icl_dsi.c

629

tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);

drivers/gpu/drm/i915/display/icl_dsi.c

63

return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)

drivers/gpu/drm/i915/display/icl_dsi.c

645

tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);

drivers/gpu/drm/i915/display/icl_dsi.c

661

tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);

drivers/gpu/drm/i915/display/icl_dsi.c

682

val = intel_de_read(display, ICL_DPCLKA_CFGCR0);

drivers/gpu/drm/i915/display/icl_dsi.c

70

return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)

drivers/gpu/drm/i915/display/icl_dsi.c

713

tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));

drivers/gpu/drm/i915/display/icl_dsi.c

822

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_alpm.c

492

alpm_ctl = intel_de_read(display, ALPM_CTL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_audio.c

1338

aud_freq_init = intel_de_read(display, AUD_FREQ_CNTRL);

drivers/gpu/drm/i915/display/intel_audio.c

260

tmp = intel_de_read(display, G4X_AUD_CNTL_ST);

drivers/gpu/drm/i915/display/intel_audio.c

273

tmp = intel_de_read(display, G4X_AUD_CNTL_ST);

drivers/gpu/drm/i915/display/intel_audio.c

283

eld[i] = intel_de_read(display, G4X_HDMIW_HDMIEDID);

drivers/gpu/drm/i915/display/intel_audio.c

324

(intel_de_read(display, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0);

drivers/gpu/drm/i915/display/intel_audio.c

361

tmp = intel_de_read(display, HSW_AUD_CFG(cpu_transcoder));

drivers/gpu/drm/i915/display/intel_audio.c

384

tmp = intel_de_read(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));

drivers/gpu/drm/i915/display/intel_audio.c

525

val = intel_de_read(display, AUD_CONFIG_BE);

drivers/gpu/drm/i915/display/intel_backlight.c

1148

if ((intel_de_read(display, CBR1_VLV) & CBR_PWM_CLOCK_MUX_SELECT) == 0) {

drivers/gpu/drm/i915/display/intel_backlight.c

1241

alt = intel_de_read(display, SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY;

drivers/gpu/drm/i915/display/intel_backlight.c

1243

alt = intel_de_read(display, SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY;

drivers/gpu/drm/i915/display/intel_backlight.c

1246

pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);

drivers/gpu/drm/i915/display/intel_backlight.c

1249

pch_ctl2 = intel_de_read(display, BLC_PWM_PCH_CTL2);

drivers/gpu/drm/i915/display/intel_backlight.c

1252

cpu_ctl2 = intel_de_read(display, BLC_PWM_CPU_CTL2);

drivers/gpu/drm/i915/display/intel_backlight.c

1296

pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);

drivers/gpu/drm/i915/display/intel_backlight.c

1299

pch_ctl2 = intel_de_read(display, BLC_PWM_PCH_CTL2);

drivers/gpu/drm/i915/display/intel_backlight.c

1310

cpu_ctl2 = intel_de_read(display, BLC_PWM_CPU_CTL2);

drivers/gpu/drm/i915/display/intel_backlight.c

1327

ctl = intel_de_read(display, BLC_PWM_CTL);

drivers/gpu/drm/i915/display/intel_backlight.c

1369

ctl2 = intel_de_read(display, BLC_PWM_CTL2);

drivers/gpu/drm/i915/display/intel_backlight.c

1373

ctl = intel_de_read(display, BLC_PWM_CTL);

drivers/gpu/drm/i915/display/intel_backlight.c

1405

ctl2 = intel_de_read(display, VLV_BLC_PWM_CTL2(pipe));

drivers/gpu/drm/i915/display/intel_backlight.c

1408

ctl = intel_de_read(display, VLV_BLC_PWM_CTL(pipe));

drivers/gpu/drm/i915/display/intel_backlight.c

1437

pwm_ctl = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_backlight.c

1442

val = intel_de_read(display, UTIL_PIN_CTL);

drivers/gpu/drm/i915/display/intel_backlight.c

1449

intel_de_read(display, BXT_BLC_PWM_FREQ(panel->backlight.controller));

drivers/gpu/drm/i915/display/intel_backlight.c

1491

return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;

drivers/gpu/drm/i915/display/intel_backlight.c

1516

pwm_ctl = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_backlight.c

1521

intel_de_read(display, BXT_BLC_PWM_FREQ(panel->backlight.controller));

drivers/gpu/drm/i915/display/intel_backlight.c

154

return intel_de_read(display, BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK;

drivers/gpu/drm/i915/display/intel_backlight.c

161

return intel_de_read(display, BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;

drivers/gpu/drm/i915/display/intel_backlight.c

170

val = intel_de_read(display, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;

drivers/gpu/drm/i915/display/intel_backlight.c

192

return intel_de_read(display, VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK;

drivers/gpu/drm/i915/display/intel_backlight.c

200

return intel_de_read(display, BXT_BLC_PWM_DUTY(panel->backlight.controller));

drivers/gpu/drm/i915/display/intel_backlight.c

218

val = intel_de_read(display, BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK;

drivers/gpu/drm/i915/display/intel_backlight.c

228

tmp = intel_de_read(display, BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;

drivers/gpu/drm/i915/display/intel_backlight.c

258

tmp = intel_de_read(display, BLC_PWM_CTL) & ~mask;

drivers/gpu/drm/i915/display/intel_backlight.c

269

tmp = intel_de_read(display, VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK;

drivers/gpu/drm/i915/display/intel_backlight.c

358

tmp = intel_de_read(display, BLC_PWM_CPU_CTL2);

drivers/gpu/drm/i915/display/intel_backlight.c

483

pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);

drivers/gpu/drm/i915/display/intel_backlight.c

529

cpu_ctl2 = intel_de_read(display, BLC_PWM_CPU_CTL2);

drivers/gpu/drm/i915/display/intel_backlight.c

538

pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1);

drivers/gpu/drm/i915/display/intel_backlight.c

578

ctl = intel_de_read(display, BLC_PWM_CTL);

drivers/gpu/drm/i915/display/intel_backlight.c

620

ctl2 = intel_de_read(display, BLC_PWM_CTL2);

drivers/gpu/drm/i915/display/intel_backlight.c

657

ctl2 = intel_de_read(display, VLV_BLC_PWM_CTL2(pipe));

drivers/gpu/drm/i915/display/intel_backlight.c

691

val = intel_de_read(display, UTIL_PIN_CTL);

drivers/gpu/drm/i915/display/intel_backlight.c

707

pwm_ctl = intel_de_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller));

drivers/gpu/drm/i915/display/intel_backlight.c

740

pwm_ctl = intel_de_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller));

drivers/gpu/drm/i915/display/intel_casf.c

145

sharp = intel_de_read(display, SHARPNESS_CTL(crtc->pipe));

drivers/gpu/drm/i915/display/intel_casf.c

88

win_size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, 1));

drivers/gpu/drm/i915/display/intel_cdclk.c

1018

cdctl = intel_de_read(display, CDCLK_CTL);

drivers/gpu/drm/i915/display/intel_cdclk.c

1194

cdclk_ctl = intel_de_read(display, CDCLK_CTL);

drivers/gpu/drm/i915/display/intel_cdclk.c

1239

if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)

drivers/gpu/drm/i915/display/intel_cdclk.c

1256

cdctl = intel_de_read(display, CDCLK_CTL);

drivers/gpu/drm/i915/display/intel_cdclk.c

1710

u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;

drivers/gpu/drm/i915/display/intel_cdclk.c

1740

val = intel_de_read(display, BXT_DE_PLL_ENABLE);

drivers/gpu/drm/i915/display/intel_cdclk.c

1758

ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;

drivers/gpu/drm/i915/display/intel_cdclk.c

1784

divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;

drivers/gpu/drm/i915/display/intel_cdclk.c

1805

squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL);

drivers/gpu/drm/i915/display/intel_cdclk.c

1822

cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;

drivers/gpu/drm/i915/display/intel_cdclk.c

2347

cdctl = intel_de_read(display, CDCLK_CTL);

drivers/gpu/drm/i915/display/intel_cdclk.c

3713

u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;

drivers/gpu/drm/i915/display/intel_cdclk.c

3741

if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)

drivers/gpu/drm/i915/display/intel_cdclk.c

379

tmp = intel_de_read(display, display->platform.pineview ||

drivers/gpu/drm/i915/display/intel_cdclk.c

3805

if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {

drivers/gpu/drm/i915/display/intel_cdclk.c

3831

return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;

drivers/gpu/drm/i915/display/intel_cdclk.c

554

u32 lcpll = intel_de_read(display, LCPLL_CTL);

drivers/gpu/drm/i915/display/intel_cdclk.c

559

else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)

drivers/gpu/drm/i915/display/intel_cdclk.c

662

intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND);

drivers/gpu/drm/i915/display/intel_cdclk.c

834

u32 lcpll = intel_de_read(display, LCPLL_CTL);

drivers/gpu/drm/i915/display/intel_cdclk.c

839

else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)

drivers/gpu/drm/i915/display/intel_cdclk.c

883

(intel_de_read(display, LCPLL_CTL) &

drivers/gpu/drm/i915/display/intel_cdclk.c

973

val = intel_de_read(display, LCPLL1_CTL);

drivers/gpu/drm/i915/display/intel_cdclk.c

980

val = intel_de_read(display, DPLL_CTRL1);

drivers/gpu/drm/i915/display/intel_cmtg.c

106

val = intel_de_read(display, TRANS_CMTG_CTL_A);

drivers/gpu/drm/i915/display/intel_cmtg.c

110

val = intel_de_read(display, TRANS_CMTG_CTL_B);

drivers/gpu/drm/i915/display/intel_cmtg.c

96

val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, trans));

drivers/gpu/drm/i915/display/intel_color.c

1064

return intel_de_read(display, GAMMA_MODE(crtc->pipe));

drivers/gpu/drm/i915/display/intel_color.c

1071

return intel_de_read(display, PIPE_CSC_MODE(crtc->pipe));

drivers/gpu/drm/i915/display/intel_color.c

1082

tmp = intel_de_read(display, DSPCNTR(display, i9xx_plane));

drivers/gpu/drm/i915/display/intel_color.c

1110

u32 tmp = intel_de_read(display, SKL_BOTTOM_COLOR(crtc->pipe));

drivers/gpu/drm/i915/display/intel_color.c

3482

crtc_state->cgm_mode = intel_de_read(display, CGM_PIPE_MODE(crtc->pipe));

drivers/gpu/drm/i915/display/intel_color.c

4081

if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) & LUT_3D_READY) {

drivers/gpu/drm/i915/display/intel_color.c

4099

if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) & LUT_3D_READY) {

drivers/gpu/drm/i915/display/intel_combo_phy.c

156

return intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT;

drivers/gpu/drm/i915/display/intel_combo_phy.c

158

return !(intel_de_read(display, ICL_PHY_MISC(phy)) &

drivers/gpu/drm/i915/display/intel_combo_phy.c

160

(intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT);

drivers/gpu/drm/i915/display/intel_combo_phy.c

337

val = intel_de_read(display, ICL_PHY_MISC(phy));

drivers/gpu/drm/i915/display/intel_combo_phy.c

351

val = intel_de_read(display, ICL_PORT_TX_DW8_LN(0, phy));

drivers/gpu/drm/i915/display/intel_combo_phy.c

357

val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));

drivers/gpu/drm/i915/display/intel_combo_phy.c

62

val = intel_de_read(display, ICL_PORT_COMP_DW3(phy));

drivers/gpu/drm/i915/display/intel_combo_phy.c

98

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_crt.c

1021

adpa = intel_de_read(display, adpa_reg);

drivers/gpu/drm/i915/display/intel_crt.c

1035

if ((intel_de_read(display, adpa_reg) & ADPA_DAC_ENABLE) == 0)

drivers/gpu/drm/i915/display/intel_crt.c

1130

display->fdi.rx_config = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_crt.c

133

tmp = intel_de_read(display, crt->adpa_reg);

drivers/gpu/drm/i915/display/intel_crt.c

491

save_adpa = adpa = intel_de_read(display, crt->adpa_reg);

drivers/gpu/drm/i915/display/intel_crt.c

515

adpa = intel_de_read(display, crt->adpa_reg);

drivers/gpu/drm/i915/display/intel_crt.c

548

save_adpa = adpa = intel_de_read(display, crt->adpa_reg);

drivers/gpu/drm/i915/display/intel_crt.c

564

adpa = intel_de_read(display, crt->adpa_reg);

drivers/gpu/drm/i915/display/intel_crt.c

613

stat = intel_de_read(display, PORT_HOTPLUG_STAT(display));

drivers/gpu/drm/i915/display/intel_crt.c

710

save_bclrpat = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_crt.c

712

save_vtotal = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_crt.c

714

vblank = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_crt.c

727

u32 transconf = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_crt.c

755

u32 vsync = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_crt.c

775

while (intel_de_read(display, PIPEDSL(display, pipe)) >= vactive)

drivers/gpu/drm/i915/display/intel_crt.c

777

while ((dsl = intel_de_read(display, PIPEDSL(display, pipe))) <= vsample)

drivers/gpu/drm/i915/display/intel_crt.c

790

} while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl));

drivers/gpu/drm/i915/display/intel_crt.c

96

val = intel_de_read(display, adpa_reg);

drivers/gpu/drm/i915/display/intel_crt.c

970

adpa = intel_de_read(display, crt->adpa_reg);

drivers/gpu/drm/i915/display/intel_cursor.c

335

ret = intel_de_read(display, CURCNTR(display, PIPE_A)) & CURSOR_ENABLE;

drivers/gpu/drm/i915/display/intel_cursor.c

744

val = intel_de_read(display, CURCNTR(display, plane->pipe));

drivers/gpu/drm/i915/display/intel_cursor.c

764

error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe));

drivers/gpu/drm/i915/display/intel_cursor.c

765

error->surf = intel_de_read(display, CURBASE(display, crtc->pipe));

drivers/gpu/drm/i915/display/intel_cursor.c

766

error->surflive = intel_de_read(display, CURSURFLIVE(display, crtc->pipe));

drivers/gpu/drm/i915/display/intel_cursor.c

775

error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe));

drivers/gpu/drm/i915/display/intel_cursor.c

776

error->surf = intel_de_read(display, CURBASE(display, crtc->pipe));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

176

if (!(intel_de_read(display, XELPDP_PORT_MSGBUS_TIMER(display, port, lane)) &

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2204

lane_reversal = intel_de_read(display, XELPDP_PORT_BUF_CTL1(display, encoder->port)) &

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2221

max_tx_lane_count = DDI_PORT_WIDTH_GET(intel_de_read(display,

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2244

return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) &

drivers/gpu/drm/i915/display/intel_cx0_phy.c

316

} else if ((intel_de_read(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane)) &

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3349

val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3429

val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3585

return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) &

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3651

val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));

drivers/gpu/drm/i915/display/intel_ddi.c

1083

tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0);

drivers/gpu/drm/i915/display/intel_ddi.c

1192

val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

drivers/gpu/drm/i915/display/intel_ddi.c

1247

val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));

drivers/gpu/drm/i915/display/intel_ddi.c

1272

val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

drivers/gpu/drm/i915/display/intel_ddi.c

1280

val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));

drivers/gpu/drm/i915/display/intel_ddi.c

1589

return !(intel_de_read(display, reg) & clk_off);

drivers/gpu/drm/i915/display/intel_ddi.c

1598

id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;

drivers/gpu/drm/i915/display/intel_ddi.c

1741

val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy));

drivers/gpu/drm/i915/display/intel_ddi.c

1836

tmp = intel_de_read(display, DDI_CLK_SEL(port));

drivers/gpu/drm/i915/display/intel_ddi.c

1889

tmp = intel_de_read(display, DDI_CLK_SEL(port));

drivers/gpu/drm/i915/display/intel_ddi.c

1894

tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);

drivers/gpu/drm/i915/display/intel_ddi.c

1907

tmp = intel_de_read(display, DDI_CLK_SEL(port));

drivers/gpu/drm/i915/display/intel_ddi.c

1995

return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));

drivers/gpu/drm/i915/display/intel_ddi.c

2005

tmp = intel_de_read(display, DPLL_CTRL2);

drivers/gpu/drm/i915/display/intel_ddi.c

2046

return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;

drivers/gpu/drm/i915/display/intel_ddi.c

2056

tmp = intel_de_read(display, PORT_CLK_SEL(port));

drivers/gpu/drm/i915/display/intel_ddi.c

2194

ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port));

drivers/gpu/drm/i915/display/intel_ddi.c

2195

ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port));

drivers/gpu/drm/i915/display/intel_ddi.c

2507

dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

drivers/gpu/drm/i915/display/intel_ddi.c

3446

val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_ddi.c

3739

dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));

drivers/gpu/drm/i915/display/intel_ddi.c

3793

dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));

drivers/gpu/drm/i915/display/intel_ddi.c

3825

temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));

drivers/gpu/drm/i915/display/intel_ddi.c

3885

return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) &

drivers/gpu/drm/i915/display/intel_ddi.c

391

u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;

drivers/gpu/drm/i915/display/intel_ddi.c

3933

u32 ctl2 = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_ddi.c

3941

u32 ctl = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_ddi.c

4031

intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &

drivers/gpu/drm/i915/display/intel_ddi.c

4060

intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &

drivers/gpu/drm/i915/display/intel_ddi.c

4065

intel_de_read(display,

drivers/gpu/drm/i915/display/intel_ddi.c

4096

intel_de_read(display,

drivers/gpu/drm/i915/display/intel_ddi.c

4110

ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_ddi.c

4888

return intel_de_read(display, SDEISR) & bit;

drivers/gpu/drm/i915/display/intel_ddi.c

4896

return intel_de_read(display, DEISR) & bit;

drivers/gpu/drm/i915/display/intel_ddi.c

4904

return intel_de_read(display, GEN8_DE_PORT_ISR) & bit;

drivers/gpu/drm/i915/display/intel_ddi.c

4961

if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)

drivers/gpu/drm/i915/display/intel_ddi.c

5102

return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;

drivers/gpu/drm/i915/display/intel_ddi.c

5104

return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED;

drivers/gpu/drm/i915/display/intel_ddi.c

5106

return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED;

drivers/gpu/drm/i915/display/intel_ddi.c

5108

return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED;

drivers/gpu/drm/i915/display/intel_ddi.c

5411

ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port));

drivers/gpu/drm/i915/display/intel_ddi.c

692

ctl = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_ddi.c

773

ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) &

drivers/gpu/drm/i915/display/intel_ddi.c

821

tmp = intel_de_read(display, DDI_BUF_CTL(port));

drivers/gpu/drm/i915/display/intel_ddi.c

826

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_ddi.c

866

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_ddi.c

925

tmp = intel_de_read(display, BXT_PHY_CTL(port));

drivers/gpu/drm/i915/display/intel_display.c

2558

bool bios_lvds_use_ssc = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

2845

return intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

2848

return intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

2860

tmp = intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

2865

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

2871

tmp = intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

2875

tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

2881

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

2886

tmp = intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

2898

intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

2916

pipe_config->min_hblank = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

2943

tmp = intel_de_read(display, PIPESRC(display, crtc->pipe));

drivers/gpu/drm/i915/display/intel_display.c

3025

tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));

drivers/gpu/drm/i915/display/intel_display.c

3060

tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

3302

tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));

drivers/gpu/drm/i915/display/intel_display.c

3347

m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;

drivers/gpu/drm/i915/display/intel_display.c

3348

m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK;

drivers/gpu/drm/i915/display/intel_display.c

3349

m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK;

drivers/gpu/drm/i915/display/intel_display.c

3350

m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK;

drivers/gpu/drm/i915/display/intel_display.c

3351

m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;

drivers/gpu/drm/i915/display/intel_display.c

3404

tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

3490

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

3514

u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

drivers/gpu/drm/i915/display/intel_display.c

3542

u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

drivers/gpu/drm/i915/display/intel_display.c

3611

u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));

drivers/gpu/drm/i915/display/intel_display.c

3773

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

383

u32 val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

3879

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

3886

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

3922

tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port));

drivers/gpu/drm/i915/display/intel_display.c

3926

tmp = intel_de_read(display, MIPI_CTRL(display, port));

drivers/gpu/drm/i915/display/intel_display.c

3979

tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

4001

u32 tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

4017

tmp = intel_de_read(display, WM_LINETIME(crtc->pipe));

drivers/gpu/drm/i915/display/intel_display.c

4036

intel_de_read(display,

drivers/gpu/drm/i915/display/intel_display.c

473

val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

519

val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_display.c

686

tmp = intel_de_read(display, PIPE_CHICKEN(pipe));

drivers/gpu/drm/i915/display/intel_display.c

7803

if ((intel_de_read(display, DP_A) & DP_DETECTED) == 0)

drivers/gpu/drm/i915/display/intel_display.c

7806

if (display->platform.ironlake && (intel_de_read(display, FUSE_STRAP) & ILK_eDP_A_DISABLE))

drivers/gpu/drm/i915/display/intel_display.c

7821

intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)

drivers/gpu/drm/i915/display/intel_display.c

7825

if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)

drivers/gpu/drm/i915/display/intel_display.c

7874

if (intel_de_read(display, PCH_HDMIB) & SDVO_DETECTED) {

drivers/gpu/drm/i915/display/intel_display.c

7879

if (!found && (intel_de_read(display, PCH_DP_B) & DP_DETECTED))

drivers/gpu/drm/i915/display/intel_display.c

7883

if (intel_de_read(display, PCH_HDMIC) & SDVO_DETECTED)

drivers/gpu/drm/i915/display/intel_display.c

7886

if (!dpd_is_edp && intel_de_read(display, PCH_HDMID) & SDVO_DETECTED)

drivers/gpu/drm/i915/display/intel_display.c

7889

if (intel_de_read(display, PCH_DP_C) & DP_DETECTED)

drivers/gpu/drm/i915/display/intel_display.c

7892

if (intel_de_read(display, PCH_DP_D) & DP_DETECTED)

drivers/gpu/drm/i915/display/intel_display.c

7917

if (intel_de_read(display, VLV_DP_B) & DP_DETECTED || has_port)

drivers/gpu/drm/i915/display/intel_display.c

7919

if ((intel_de_read(display, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)

drivers/gpu/drm/i915/display/intel_display.c

7924

if (intel_de_read(display, VLV_DP_C) & DP_DETECTED || has_port)

drivers/gpu/drm/i915/display/intel_display.c

7926

if ((intel_de_read(display, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)

drivers/gpu/drm/i915/display/intel_display.c

7935

if (intel_de_read(display, CHV_DP_D) & DP_DETECTED || has_port)

drivers/gpu/drm/i915/display/intel_display.c

7937

if (intel_de_read(display, CHV_HDMID) & SDVO_DETECTED || has_port)

drivers/gpu/drm/i915/display/intel_display.c

7953

if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) {

drivers/gpu/drm/i915/display/intel_display.c

7968

if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) {

drivers/gpu/drm/i915/display/intel_display.c

7973

if (!found && (intel_de_read(display, GEN3_SDVOC) & SDVO_DETECTED)) {

drivers/gpu/drm/i915/display/intel_display.c

7984

if (display->platform.g4x && (intel_de_read(display, DP_D) & DP_DETECTED))

drivers/gpu/drm/i915/display/intel_display.c

8411

intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE);

drivers/gpu/drm/i915/display/intel_display.c

8413

intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE);

drivers/gpu/drm/i915/display/intel_display.c

8415

intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE);

drivers/gpu/drm/i915/display/intel_display.c

8417

intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK);

drivers/gpu/drm/i915/display/intel_display.c

8419

intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK);

drivers/gpu/drm/i915/display/intel_display_debugfs.c

100

sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

102

sr_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

104

sr_enabled = intel_de_read(display, DSPFW3(display)) & PINEVIEW_SELF_REFRESH_EN;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

106

sr_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

97

sr_enabled = intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE;

drivers/gpu/drm/i915/display/intel_display_device.c

1819

!(intel_de_read(display, GU_CNTL_PROTECTED) & DEPRESENT)) {

drivers/gpu/drm/i915/display/intel_display_device.c

1825

u32 fuse_strap = intel_de_read(display, FUSE_STRAP);

drivers/gpu/drm/i915/display/intel_display_device.c

1826

u32 sfuse_strap = intel_de_read(display, SFUSE_STRAP);

drivers/gpu/drm/i915/display/intel_display_device.c

1850

u32 dfsm = intel_de_read(display, SKL_DFSM);

drivers/gpu/drm/i915/display/intel_display_device.c

1899

u32 cap = intel_de_read(display, XE2LPD_DE_CAP);

drivers/gpu/drm/i915/display/intel_display_device.c

1915

intel_de_read(display, PICA_PHY_CONFIG_CONTROL) & EDP_ON_TYPEC;

drivers/gpu/drm/i915/display/intel_display_irq.c

1275

u32 val = intel_de_read(display, RM_TIMEOUT_REG_CAPTURE);

drivers/gpu/drm/i915/display/intel_display_irq.c

1327

val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_DSI_0));

drivers/gpu/drm/i915/display/intel_display_irq.c

1339

val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));

drivers/gpu/drm/i915/display/intel_display_irq.c

1348

val = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, dsi_trans));

drivers/gpu/drm/i915/display/intel_display_irq.c

1384

*pch_iir = intel_de_read(display, SDEIIR);

drivers/gpu/drm/i915/display/intel_display_irq.c

1397

*pica_iir = intel_de_read(display, PICAINTERRUPT_IIR);

drivers/gpu/drm/i915/display/intel_display_irq.c

1415

iir = intel_de_read(display, GEN8_DE_MISC_IIR);

drivers/gpu/drm/i915/display/intel_display_irq.c

1426

iir = intel_de_read(display, GEN11_DE_HPD_IIR);

drivers/gpu/drm/i915/display/intel_display_irq.c

1437

iir = intel_de_read(display, GEN8_DE_PORT_IIR);

drivers/gpu/drm/i915/display/intel_display_irq.c

1494

iir = intel_de_read(display, GEN8_DE_PIPE_IIR(pipe));

drivers/gpu/drm/i915/display/intel_display_irq.c

1577

iir = intel_de_read(display, GEN11_GU_MISC_IIR);

drivers/gpu/drm/i915/display/intel_display_irq.c

1601

disp_ctl = intel_de_read(display, GEN11_DISPLAY_INT_CTL);

drivers/gpu/drm/i915/display/intel_display_irq.c

1867

tmp = intel_de_read(display, DPINVGTT);

drivers/gpu/drm/i915/display/intel_display_irq.c

1906

*eir = intel_de_read(display, VLV_EIR);

drivers/gpu/drm/i915/display/intel_display_irq.c

1918

emr = intel_de_read(display, VLV_EMR);

drivers/gpu/drm/i915/display/intel_display_irq.c

208

old_val = intel_de_read(display, GEN8_DE_PORT_IMR);

drivers/gpu/drm/i915/display/intel_display_irq.c

2487

snapshot->derrmr = intel_de_read(display, DERRMR);

drivers/gpu/drm/i915/display/intel_display_irq.c

273

u32 sdeimr = intel_de_read(display, SDEIMR);

drivers/gpu/drm/i915/display/intel_display_irq.c

482

intel_de_read(display, PIPE_CRC_RES_HSW(pipe)),

drivers/gpu/drm/i915/display/intel_display_irq.c

490

intel_de_read(display, PIPE_CRC_RES_1_IVB(pipe)),

drivers/gpu/drm/i915/display/intel_display_irq.c

491

intel_de_read(display, PIPE_CRC_RES_2_IVB(pipe)),

drivers/gpu/drm/i915/display/intel_display_irq.c

492

intel_de_read(display, PIPE_CRC_RES_3_IVB(pipe)),

drivers/gpu/drm/i915/display/intel_display_irq.c

493

intel_de_read(display, PIPE_CRC_RES_4_IVB(pipe)),

drivers/gpu/drm/i915/display/intel_display_irq.c

494

intel_de_read(display, PIPE_CRC_RES_5_IVB(pipe)));

drivers/gpu/drm/i915/display/intel_display_irq.c

503

res1 = intel_de_read(display, PIPE_CRC_RES_RES1_I915(display, pipe));

drivers/gpu/drm/i915/display/intel_display_irq.c

508

res2 = intel_de_read(display, PIPE_CRC_RES_RES2_G4X(display, pipe));

drivers/gpu/drm/i915/display/intel_display_irq.c

513

intel_de_read(display, PIPE_CRC_RES_RED(display, pipe)),

drivers/gpu/drm/i915/display/intel_display_irq.c

514

intel_de_read(display, PIPE_CRC_RES_GREEN(display, pipe)),

drivers/gpu/drm/i915/display/intel_display_irq.c

515

intel_de_read(display, PIPE_CRC_RES_BLUE(display, pipe)),

drivers/gpu/drm/i915/display/intel_display_irq.c

52

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_display_irq.c

579

pipe_stats[pipe] = intel_de_read(display, reg) & status_mask;

drivers/gpu/drm/i915/display/intel_display_irq.c

706

intel_de_read(display, FDI_RX_IIR(pipe)));

drivers/gpu/drm/i915/display/intel_display_irq.c

758

u32 err_int = intel_de_read(display, GEN7_ERR_INT);

drivers/gpu/drm/i915/display/intel_display_irq.c

794

u32 serr_int = intel_de_read(display, SERR_INT);

drivers/gpu/drm/i915/display/intel_display_irq.c

837

intel_de_read(display, FDI_RX_IIR(pipe)));

drivers/gpu/drm/i915/display/intel_display_irq.c

875

gtt_fault = intel_de_read(display, ILK_GTT_FAULT);

drivers/gpu/drm/i915/display/intel_display_irq.c

930

u32 pch_iir = intel_de_read(display, SDEIIR);

drivers/gpu/drm/i915/display/intel_display_irq.c

985

u32 pch_iir = intel_de_read(display, SDEIIR);

drivers/gpu/drm/i915/display/intel_display_power.c

1080

state = intel_de_read(display, reg) & DBUF_POWER_STATE;

drivers/gpu/drm/i915/display/intel_display_power.c

1184

u32 val = intel_de_read(display, LCPLL_CTL);

drivers/gpu/drm/i915/display/intel_display_power.c

1211

INTEL_DISPLAY_STATE_WARN(display, intel_de_read(display, HSW_PWR_WELL_CTL2),

drivers/gpu/drm/i915/display/intel_display_power.c

1214

intel_de_read(display, SPLL_CTL) & SPLL_PLL_ENABLE,

drivers/gpu/drm/i915/display/intel_display_power.c

1217

intel_de_read(display, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE,

drivers/gpu/drm/i915/display/intel_display_power.c

1220

intel_de_read(display, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE,

drivers/gpu/drm/i915/display/intel_display_power.c

1223

intel_de_read(display, PP_STATUS(display, 0)) & PP_ON,

drivers/gpu/drm/i915/display/intel_display_power.c

1226

intel_de_read(display, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,

drivers/gpu/drm/i915/display/intel_display_power.c

1230

intel_de_read(display, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,

drivers/gpu/drm/i915/display/intel_display_power.c

1233

intel_de_read(display, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,

drivers/gpu/drm/i915/display/intel_display_power.c

1236

(intel_de_read(display, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM),

drivers/gpu/drm/i915/display/intel_display_power.c

1239

intel_de_read(display, PCH_GTC_CTL) & PCH_GTC_ENABLE,

drivers/gpu/drm/i915/display/intel_display_power.c

1255

return intel_de_read(display, D_COMP_HSW);

drivers/gpu/drm/i915/display/intel_display_power.c

1257

return intel_de_read(display, D_COMP_BDW);

drivers/gpu/drm/i915/display/intel_display_power.c

1287

val = intel_de_read(display, LCPLL_CTL);

drivers/gpu/drm/i915/display/intel_display_power.c

1298

val = intel_de_read(display, LCPLL_CTL);

drivers/gpu/drm/i915/display/intel_display_power.c

1334

val = intel_de_read(display, LCPLL_CTL);

drivers/gpu/drm/i915/display/intel_display_power.c

1357

val = intel_de_read(display, LCPLL_CTL);

drivers/gpu/drm/i915/display/intel_display_power.c

1805

u32 status = intel_de_read(display, DPLL(display, PIPE_A));

drivers/gpu/drm/i915/display/intel_display_power.c

1836

u32 status = intel_de_read(display, DPIO_PHY_STATUS);

drivers/gpu/drm/i915/display/intel_display_power.c

1873

intel_de_read(display, DPIO_CTL) & DPIO_CMNRST)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1103

if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1105

if ((intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE) == 0)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1119

return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE &&

drivers/gpu/drm/i915/display/intel_display_power_well.c

1120

intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE;

drivers/gpu/drm/i915/display/intel_display_power_well.c

1256

u32 val = intel_de_read(display, DPLL(display, pipe));

drivers/gpu/drm/i915/display/intel_display_power_well.c

1412

(intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0)

drivers/gpu/drm/i915/display/intel_display_power_well.c

1912

return intel_de_read(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch)) &

drivers/gpu/drm/i915/display/intel_display_power_well.c

1946

return intel_de_read(display, XE2LPD_PICA_PW_CTL) &

drivers/gpu/drm/i915/display/intel_display_power_well.c

329

ret = intel_de_read(display, regs->bios) & req_mask ? 1 : 0;

drivers/gpu/drm/i915/display/intel_display_power_well.c

330

ret |= intel_de_read(display, regs->driver) & req_mask ? 2 : 0;

drivers/gpu/drm/i915/display/intel_display_power_well.c

332

ret |= intel_de_read(display, regs->kvmr) & req_mask ? 4 : 0;

drivers/gpu/drm/i915/display/intel_display_power_well.c

333

ret |= intel_de_read(display, regs->debug) & req_mask ? 8 : 0;

drivers/gpu/drm/i915/display/intel_display_power_well.c

626

val = intel_de_read(display, regs->driver);

drivers/gpu/drm/i915/display/intel_display_power_well.c

636

val |= intel_de_read(display, regs->bios);

drivers/gpu/drm/i915/display/intel_display_power_well.c

644

(intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9),

drivers/gpu/drm/i915/display/intel_display_power_well.c

647

intel_de_read(display, DC_STATE_EN) &

drivers/gpu/drm/i915/display/intel_display_power_well.c

651

intel_de_read(display, HSW_PWR_WELL_CTL2) &

drivers/gpu/drm/i915/display/intel_display_power_well.c

671

intel_de_read(display, DC_STATE_EN) &

drivers/gpu/drm/i915/display/intel_display_power_well.c

699

v = intel_de_read(display, DC_STATE_EN);

drivers/gpu/drm/i915/display/intel_display_power_well.c

750

val = intel_de_read(display, DC_STATE_EN) & gen9_dc_mask(display);

drivers/gpu/drm/i915/display/intel_display_power_well.c

798

val = intel_de_read(display, DC_STATE_EN);

drivers/gpu/drm/i915/display/intel_display_power_well.c

856

(intel_de_read(display, DC_STATE_EN) &

drivers/gpu/drm/i915/display/intel_display_power_well.c

884

(intel_de_read(display, UTIL_PIN_CTL) &

drivers/gpu/drm/i915/display/intel_display_power_well.c

889

(intel_de_read(display, DC_STATE_EN) &

drivers/gpu/drm/i915/display/intel_display_power_well.c

943

u32 bios_req = intel_de_read(display, regs->bios);

drivers/gpu/drm/i915/display/intel_display_power_well.c

947

u32 drv_req = intel_de_read(display, regs->driver);

drivers/gpu/drm/i915/display/intel_display_power_well.c

997

return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&

drivers/gpu/drm/i915/display/intel_display_power_well.c

998

(intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);

drivers/gpu/drm/i915/display/intel_dkl_phy.c

54

val = intel_de_read(display, DKL_REG_MMIO(reg));

drivers/gpu/drm/i915/display/intel_dmc.c

1584

dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT);

drivers/gpu/drm/i915/display/intel_dmc.c

1658

intel_de_read(display, dc3co_reg));

drivers/gpu/drm/i915/display/intel_dmc.c

1666

seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));

drivers/gpu/drm/i915/display/intel_dmc.c

1673

intel_de_read(display, dc6_reg));

drivers/gpu/drm/i915/display/intel_dmc.c

1676

intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));

drivers/gpu/drm/i915/display/intel_dmc.c

1680

intel_de_read(display, DMC_SSP_BASE));

drivers/gpu/drm/i915/display/intel_dmc.c

1681

seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL));

drivers/gpu/drm/i915/display/intel_dmc.c

1702

tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe));

drivers/gpu/drm/i915/display/intel_dmc.c

1733

int_vector = intel_de_read(display, PIPEDMC_STATUS(pipe)) & PIPEDMC_INT_VECTOR_MASK;

drivers/gpu/drm/i915/display/intel_dmc.c

688

found = intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, 0));

drivers/gpu/drm/i915/display/intel_dmc.c

698

found = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_dp.c

5014

u32 val = intel_de_read(display, reg) & ~dip_enable;

drivers/gpu/drm/i915/display/intel_dp.c

6927

intel_dp->DP = intel_de_read(display, intel_dp->output_reg);

drivers/gpu/drm/i915/display/intel_dp_aux.c

324

const u32 status = intel_de_read(display, ch_ctl);

drivers/gpu/drm/i915/display/intel_dp_aux.c

437

intel_dp_aux_unpack(intel_de_read(display, ch_data[i >> 2]),

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

812

val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

834

val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpio_phy.c

288

old = intel_de_read(display, reg_single);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

336

val = intel_de_read(display, BXT_PORT_TX_DW3_LN(phy, ch, lane));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

362

if (!(intel_de_read(display, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))

drivers/gpu/drm/i915/display/intel_dpio_phy.c

365

if ((intel_de_read(display, BXT_PORT_CL1CM_DW0(phy)) &

drivers/gpu/drm/i915/display/intel_dpio_phy.c

373

if (!(intel_de_read(display, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {

drivers/gpu/drm/i915/display/intel_dpio_phy.c

385

u32 val = intel_de_read(display, BXT_PORT_REF_DW6(phy));

drivers/gpu/drm/i915/display/intel_dpio_phy.c

522

val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_dpio_phy.c

649

u32 val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll.c

2191

(intel_de_read(display, DPLL(display, PIPE_B)) &

drivers/gpu/drm/i915/display/intel_dpll.c

2321

cur_state = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;

drivers/gpu/drm/i915/display/intel_dpll.c

404

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll.c

410

hw_state->dpll = intel_de_read(display, DPLL(display, crtc->pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

413

hw_state->fp0 = intel_de_read(display, FP0(crtc->pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

414

hw_state->fp1 = intel_de_read(display, FP1(crtc->pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

483

u32 lvds = intel_de_read(display, LVDS);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1264

if (intel_de_read(display, FUSE_STRAP3) & HSW_REF_CLK_SELECT)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1461

val = intel_de_read(display, regs[id].ctl);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1465

val = intel_de_read(display, DPLL_CTRL1);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1470

hw_state->cfgcr1 = intel_de_read(display, regs[id].cfgcr1);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1471

hw_state->cfgcr2 = intel_de_read(display, regs[id].cfgcr2);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1500

val = intel_de_read(display, regs[id].ctl);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1504

val = intel_de_read(display, DPLL_CTRL1);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2109

temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2123

temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2130

temp = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2147

temp = intel_de_read(display, BXT_PORT_TX_DW5_LN(phy, ch, 0));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2156

temp = intel_de_read(display, BXT_PORT_PCS_DW12_LN01(phy, ch));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2206

val = intel_de_read(display, BXT_PORT_PLL_ENABLE(port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2210

hw_state->ebb0 = intel_de_read(display, BXT_PORT_PLL_EBB_0(phy, ch));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2213

hw_state->ebb4 = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2216

hw_state->pll0 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 0));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2219

hw_state->pll1 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 1));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2222

hw_state->pll2 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 2));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2225

hw_state->pll3 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 3));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2228

hw_state->pll6 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2233

hw_state->pll8 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 8));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2236

hw_state->pll9 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 9));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2239

hw_state->pll10 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2248

hw_state->pcsdw12 = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2250

if (intel_de_read(display, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2254

intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3612

val = intel_de_read(display, enable_reg);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3616

hw_state->mg_refclkin_ctl = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3621

intel_de_read(display, MG_CLKTOP2_CORECLKCTL1(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3626

intel_de_read(display, MG_CLKTOP2_HSCLKCTL(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3633

hw_state->mg_pll_div0 = intel_de_read(display, MG_PLL_DIV0(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3634

hw_state->mg_pll_div1 = intel_de_read(display, MG_PLL_DIV1(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3635

hw_state->mg_pll_lf = intel_de_read(display, MG_PLL_LF(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3636

hw_state->mg_pll_frac_lock = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3638

hw_state->mg_pll_ssc = intel_de_read(display, MG_PLL_SSC(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3640

hw_state->mg_pll_bias = intel_de_read(display, MG_PLL_BIAS(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3642

intel_de_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3677

val = intel_de_read(display, intel_tc_pll_enable_reg(display, pll));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3749

val = intel_de_read(display, enable_reg);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3754

hw_state->cfgcr0 = intel_de_read(display, ADLS_DPLL_CFGCR0(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3755

hw_state->cfgcr1 = intel_de_read(display, ADLS_DPLL_CFGCR1(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3757

hw_state->cfgcr0 = intel_de_read(display, DG1_DPLL_CFGCR0(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3758

hw_state->cfgcr1 = intel_de_read(display, DG1_DPLL_CFGCR1(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3760

hw_state->cfgcr0 = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3762

hw_state->cfgcr1 = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3765

hw_state->cfgcr0 = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3767

hw_state->cfgcr1 = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3770

hw_state->div0 = intel_de_read(display, TGL_DPLL0_DIV0(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3776

hw_state->cfgcr0 = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3778

hw_state->cfgcr1 = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3781

hw_state->cfgcr0 = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3783

hw_state->cfgcr1 = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4004

val = intel_de_read(display, TRANS_CMTG_CHICKEN);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

558

val = intel_de_read(display, PCH_DPLL(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

560

hw_state->fp0 = intel_de_read(display, PCH_FP0(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

561

hw_state->fp1 = intel_de_read(display, PCH_FP1(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

573

val = intel_de_read(display, PCH_DREF_CONTROL);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

779

val = intel_de_read(display, WRPLL_CTL(id));

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

800

val = intel_de_read(display, SPLL_CTL);

drivers/gpu/drm/i915/display/intel_dvo.c

139

tmp = intel_de_read(display, DVO(port));

drivers/gpu/drm/i915/display/intel_dvo.c

154

tmp = intel_de_read(display, DVO(port));

drivers/gpu/drm/i915/display/intel_dvo.c

170

tmp = intel_de_read(display, DVO(port));

drivers/gpu/drm/i915/display/intel_dvo.c

300

dvo_val = intel_de_read(display, DVO(port)) &

drivers/gpu/drm/i915/display/intel_fbc.c

2252

val = intel_de_read(display, FBC_DEBUG_STATUS(fbc->id));

drivers/gpu/drm/i915/display/intel_fbc.c

332

fbc_ctl = intel_de_read(display, FBC_CONTROL);

drivers/gpu/drm/i915/display/intel_fbc.c

370

return intel_de_read(fbc->display, FBC_CONTROL) & FBC_CTL_EN;

drivers/gpu/drm/i915/display/intel_fbc.c

375

return intel_de_read(fbc->display, FBC_STATUS) &

drivers/gpu/drm/i915/display/intel_fbc.c

490

dpfc_ctl = intel_de_read(display, DPFC_CONTROL);

drivers/gpu/drm/i915/display/intel_fbc.c

499

return intel_de_read(fbc->display, DPFC_CONTROL) & DPFC_CTL_EN;

drivers/gpu/drm/i915/display/intel_fbc.c

504

return intel_de_read(fbc->display, DPFC_STATUS) & DPFC_COMP_SEG_MASK;

drivers/gpu/drm/i915/display/intel_fbc.c

559

dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id));

drivers/gpu/drm/i915/display/intel_fbc.c

568

return intel_de_read(fbc->display, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN;

drivers/gpu/drm/i915/display/intel_fbc.c

573

return intel_de_read(fbc->display, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;

drivers/gpu/drm/i915/display/intel_fbc.c

710

return intel_de_read(fbc->display, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB;

drivers/gpu/drm/i915/display/intel_fdi.c

1005

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

1008

temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;

drivers/gpu/drm/i915/display/intel_fdi.c

1021

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

105

cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE;

drivers/gpu/drm/i915/display/intel_fdi.c

1061

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

1063

temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;

drivers/gpu/drm/i915/display/intel_fdi.c

1079

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

1089

temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11;

drivers/gpu/drm/i915/display/intel_fdi.c

274

fdi_pll_clk = intel_de_read(display, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;

drivers/gpu/drm/i915/display/intel_fdi.c

393

temp = intel_de_read(display, SOUTH_CHICKEN1);

drivers/gpu/drm/i915/display/intel_fdi.c

398

intel_de_read(display, FDI_RX_CTL(PIPE_B)) &

drivers/gpu/drm/i915/display/intel_fdi.c

401

intel_de_read(display, FDI_RX_CTL(PIPE_C)) &

drivers/gpu/drm/i915/display/intel_fdi.c

42

cur_state = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_fdi.c

447

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

45

cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE;

drivers/gpu/drm/i915/display/intel_fdi.c

458

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

491

intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);

drivers/gpu/drm/i915/display/intel_fdi.c

499

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

503

intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

508

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

516

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

532

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

554

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

592

intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);

drivers/gpu/drm/i915/display/intel_fdi.c

597

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

607

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

621

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

642

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

661

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

67

cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE;

drivers/gpu/drm/i915/display/intel_fdi.c

672

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

693

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

729

intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);

drivers/gpu/drm/i915/display/intel_fdi.c

734

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

743

intel_de_read(display, FDI_RX_IIR(pipe)));

drivers/gpu/drm/i915/display/intel_fdi.c

749

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

755

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

763

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

776

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

786

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

790

(intel_de_read(display, reg) & FDI_RX_BIT_LOCK)) {

drivers/gpu/drm/i915/display/intel_fdi.c

818

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_fdi.c

822

(intel_de_read(display, reg) & FDI_RX_SYMBOL_LOCK)) {

drivers/gpu/drm/i915/display/intel_fdi.c

930

temp = intel_de_read(display, DP_TP_STATUS(PORT_E));

drivers/gpu/drm/i915/display/intel_fdi.c

95

cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_PLL_ENABLE;

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

110

u32 val = intel_de_read(display, UNDERRUN_DBG2(pipe));

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

127

u32 val = intel_de_read(display, GEN12_DCPR_STATUS_1);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

198

if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

224

if (old && intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS)

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

246

u32 err_int = intel_de_read(display, GEN7_ERR_INT);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

276

intel_de_read(display, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

310

u32 serr_int = intel_de_read(display, SERR_INT);

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

341

if (old && intel_de_read(display, SERR_INT) &

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

88

u32 val = intel_de_read(display, UNDERRUN_DBG1(pipe));

drivers/gpu/drm/i915/display/intel_flipq.c

178

return intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id));

drivers/gpu/drm/i915/display/intel_flipq.c

221

intel_de_read(display, PIPEDMC_FQ_RAM(flipq->start_mmioaddr, i)));

drivers/gpu/drm/i915/display/intel_flipq.c

229

intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id)),

drivers/gpu/drm/i915/display/intel_flipq.c

230

intel_de_read(display, PIPEDMC_FPQ_HP(crtc->pipe, flipq_id)));

drivers/gpu/drm/i915/display/intel_flipq.c

240

intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe)));

drivers/gpu/drm/i915/display/intel_flipq.c

242

tmp = intel_de_read(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe));

drivers/gpu/drm/i915/display/intel_flipq.c

433

pts += intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe));

drivers/gpu/drm/i915/display/intel_hdcp.c

1145

intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)));

drivers/gpu/drm/i915/display/intel_hdcp.c

1882

if (!(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &

drivers/gpu/drm/i915/display/intel_hdcp.c

1923

intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &

drivers/gpu/drm/i915/display/intel_hdcp.c

1936

if (intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &

drivers/gpu/drm/i915/display/intel_hdcp.c

1961

!(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) &

drivers/gpu/drm/i915/display/intel_hdcp.c

2169

intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)));

drivers/gpu/drm/i915/display/intel_hdcp.c

310

return intel_de_read(display,

drivers/gpu/drm/i915/display/intel_hdcp.c

318

return intel_de_read(display,

drivers/gpu/drm/i915/display/intel_hdcp.c

380

val = intel_de_read(display, HDCP_KEY_STATUS);

drivers/gpu/drm/i915/display/intel_hdcp.c

389

if (!(intel_de_read(display, HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE))

drivers/gpu/drm/i915/display/intel_hdcp.c

714

if (!(intel_de_read(display, HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) {

drivers/gpu/drm/i915/display/intel_hdcp.c

865

an.reg[0] = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_hdcp.c

867

an.reg[1] = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_hdcp.c

906

ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)),

drivers/gpu/drm/i915/display/intel_hdcp.c

941

ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)),

drivers/gpu/drm/i915/display/intel_hdmi.c

103

intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) &

drivers/gpu/drm/i915/display/intel_hdmi.c

1039

crtc_state->infoframes.gcp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1074

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1132

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1181

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1237

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1262

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

1522

scanline = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_hdmi.c

1605

intel_de_read(display, HDCP_STATUS(display, cpu_transcoder,

drivers/gpu/drm/i915/display/intel_hdmi.c

233

u32 val = intel_de_read(display, VIDEO_DIP_CTL);

drivers/gpu/drm/i915/display/intel_hdmi.c

275

*data++ = intel_de_read(display, VIDEO_DIP_DATA);

drivers/gpu/drm/i915/display/intel_hdmi.c

282

u32 val = intel_de_read(display, VIDEO_DIP_CTL);

drivers/gpu/drm/i915/display/intel_hdmi.c

303

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

347

*data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));

drivers/gpu/drm/i915/display/intel_hdmi.c

356

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

378

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

425

*data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));

drivers/gpu/drm/i915/display/intel_hdmi.c

433

u32 val = intel_de_read(display, TVIDEO_DIP_CTL(pipe));

drivers/gpu/drm/i915/display/intel_hdmi.c

452

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

497

*data++ = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_hdmi.c

506

u32 val = intel_de_read(display, VLV_TVIDEO_DIP_CTL(pipe));

drivers/gpu/drm/i915/display/intel_hdmi.c

530

u32 val = intel_de_read(display, ctl_reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

573

*data++ = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_hdmi.c

581

u32 val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_hdmi.c

889

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_hdmi.c

94

intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

443

u32 tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

456

intel_de_read(display, PORT_HOTPLUG_STAT(display)));

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

497

dig_hotplug_reg = intel_de_read(display, PCH_PORT_HOTPLUG);

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

533

val = intel_de_read(display, XELPDP_PORT_HOTPLUG_CTL(pin));

drivers/gpu/drm/i915/display/intel_hti.c

21

display->hti.state = intel_de_read(display, HDPORT_STATE);

drivers/gpu/drm/i915/display/intel_lpe_audio.c

341

audio_enable = intel_de_read(display, VLV_AUD_PORT_EN_DBG(port));

drivers/gpu/drm/i915/display/intel_lspcon.c

661

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_lvds.c

131

tmp = intel_de_read(display, lvds_encoder->reg);

drivers/gpu/drm/i915/display/intel_lvds.c

149

tmp = intel_de_read(display, PFIT_CONTROL(display));

drivers/gpu/drm/i915/display/intel_lvds.c

162

pps->powerdown_on_reset = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_lvds.c

165

val = intel_de_read(display, PP_ON_DELAYS(display, 0));

drivers/gpu/drm/i915/display/intel_lvds.c

170

val = intel_de_read(display, PP_OFF_DELAYS(display, 0));

drivers/gpu/drm/i915/display/intel_lvds.c

174

val = intel_de_read(display, PP_DIVISOR(display, 0));

drivers/gpu/drm/i915/display/intel_lvds.c

216

val = intel_de_read(display, PP_CONTROL(display, 0));

drivers/gpu/drm/i915/display/intel_lvds.c

820

val = intel_de_read(display, lvds_encoder->reg);

drivers/gpu/drm/i915/display/intel_lvds.c

871

lvds = intel_de_read(display, lvds_reg);

drivers/gpu/drm/i915/display/intel_lvds.c

92

val = intel_de_read(display, lvds_reg);

drivers/gpu/drm/i915/display/intel_overlay.c

1305

attrs->gamma0 = intel_de_read(display, OGAMC0);

drivers/gpu/drm/i915/display/intel_overlay.c

1306

attrs->gamma1 = intel_de_read(display, OGAMC1);

drivers/gpu/drm/i915/display/intel_overlay.c

1307

attrs->gamma2 = intel_de_read(display, OGAMC2);

drivers/gpu/drm/i915/display/intel_overlay.c

1308

attrs->gamma3 = intel_de_read(display, OGAMC3);

drivers/gpu/drm/i915/display/intel_overlay.c

1309

attrs->gamma4 = intel_de_read(display, OGAMC4);

drivers/gpu/drm/i915/display/intel_overlay.c

1310

attrs->gamma5 = intel_de_read(display, OGAMC5);

drivers/gpu/drm/i915/display/intel_overlay.c

1491

error->dovsta = intel_de_read(display, DOVSTA);

drivers/gpu/drm/i915/display/intel_overlay.c

1492

error->isr = intel_de_read(display, GEN2_ISR);

drivers/gpu/drm/i915/display/intel_overlay.c

334

tmp = intel_de_read(display, DOVSTA);

drivers/gpu/drm/i915/display/intel_overlay.c

474

if (!(intel_de_read(display, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) {

drivers/gpu/drm/i915/display/intel_overlay.c

952

u32 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));

drivers/gpu/drm/i915/display/intel_overlay.c

959

if (intel_de_read(display, PFIT_CONTROL(display)) & PFIT_VERT_AUTO_SCALE)

drivers/gpu/drm/i915/display/intel_overlay.c

960

tmp = intel_de_read(display, PFIT_AUTO_RATIOS(display));

drivers/gpu/drm/i915/display/intel_overlay.c

962

tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));

drivers/gpu/drm/i915/display/intel_pch_display.c

111

val = intel_de_read(display, PCH_TRANSCONF(pipe));

drivers/gpu/drm/i915/display/intel_pch_display.c

121

u32 val = intel_de_read(display, hdmi_reg);

drivers/gpu/drm/i915/display/intel_pch_display.c

140

u32 val = intel_de_read(display, dp_reg);

drivers/gpu/drm/i915/display/intel_pch_display.c

230

intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder)));

drivers/gpu/drm/i915/display/intel_pch_display.c

232

intel_de_read(display, TRANS_HBLANK(display, cpu_transcoder)));

drivers/gpu/drm/i915/display/intel_pch_display.c

234

intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder)));

drivers/gpu/drm/i915/display/intel_pch_display.c

237

intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder)));

drivers/gpu/drm/i915/display/intel_pch_display.c

239

intel_de_read(display, TRANS_VBLANK(display, cpu_transcoder)));

drivers/gpu/drm/i915/display/intel_pch_display.c

241

intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder)));

drivers/gpu/drm/i915/display/intel_pch_display.c

243

intel_de_read(display, TRANS_VSYNCSHIFT(display, cpu_transcoder)));

drivers/gpu/drm/i915/display/intel_pch_display.c

263

val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_pch_display.c

276

val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_pch_display.c

277

pipeconf_val = intel_de_read(display, TRANSCONF(display, pipe));

drivers/gpu/drm/i915/display/intel_pch_display.c

382

temp = intel_de_read(display, PCH_DPLL_SEL);

drivers/gpu/drm/i915/display/intel_pch_display.c

419

u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe))

drivers/gpu/drm/i915/display/intel_pch_display.c

424

temp = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_pch_display.c

506

if ((intel_de_read(display, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)

drivers/gpu/drm/i915/display/intel_pch_display.c

511

tmp = intel_de_read(display, FDI_RX_CTL(pipe));

drivers/gpu/drm/i915/display/intel_pch_display.c

525

tmp = intel_de_read(display, PCH_DPLL_SEL);

drivers/gpu/drm/i915/display/intel_pch_display.c

557

val = intel_de_read(display, TRANS_CHICKEN2(PIPE_A));

drivers/gpu/drm/i915/display/intel_pch_display.c

566

pipeconf_val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_pch_display.c

625

if ((intel_de_read(display, LPT_TRANSCONF) & TRANS_ENABLE) == 0)

drivers/gpu/drm/i915/display/intel_pch_display.c

630

tmp = intel_de_read(display, FDI_RX_CTL(PIPE_A));

drivers/gpu/drm/i915/display/intel_pch_refclk.c

242

if ((intel_de_read(display, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)

drivers/gpu/drm/i915/display/intel_pch_refclk.c

405

u32 fuse_strap = intel_de_read(display, FUSE_STRAP);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

406

u32 ctl = intel_de_read(display, SPLL_CTL);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

424

u32 fuse_strap = intel_de_read(display, FUSE_STRAP);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

425

u32 ctl = intel_de_read(display, WRPLL_CTL(id));

drivers/gpu/drm/i915/display/intel_pch_refclk.c

541

temp = intel_de_read(display, PCH_DPLL(pll->info->id));

drivers/gpu/drm/i915/display/intel_pch_refclk.c

562

val = intel_de_read(display, PCH_DREF_CONTROL);

drivers/gpu/drm/i915/display/intel_pfit.c

626

ctl = intel_de_read(display, PF_CTL(crtc->pipe));

drivers/gpu/drm/i915/display/intel_pfit.c

637

pos = intel_de_read(display, PF_WIN_POS(crtc->pipe));

drivers/gpu/drm/i915/display/intel_pfit.c

638

size = intel_de_read(display, PF_WIN_SZ(crtc->pipe));

drivers/gpu/drm/i915/display/intel_pfit.c

667

intel_de_read(display, PFIT_CONTROL(display)) & PFIT_ENABLE);

drivers/gpu/drm/i915/display/intel_pfit.c

692

intel_de_read(display, PFIT_CONTROL(display)));

drivers/gpu/drm/i915/display/intel_pfit.c

715

tmp = intel_de_read(display, PFIT_CONTROL(display));

drivers/gpu/drm/i915/display/intel_pfit.c

730

intel_de_read(display, PFIT_PGM_RATIOS(display));

drivers/gpu/drm/i915/display/intel_pipe_crc.c

174

u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display));

drivers/gpu/drm/i915/display/intel_pipe_crc.c

236

u32 tmp = intel_de_read(display, PORT_DFT2_G4X(display));

drivers/gpu/drm/i915/display/intel_pmdemand.c

418

reg1 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0));

drivers/gpu/drm/i915/display/intel_pmdemand.c

420

reg2 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1));

drivers/gpu/drm/i915/display/intel_pmdemand.c

455

return !(intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &

drivers/gpu/drm/i915/display/intel_pmdemand.c

587

reg1 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0));

drivers/gpu/drm/i915/display/intel_pmdemand.c

590

reg2 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1));

drivers/gpu/drm/i915/display/intel_pps.c

106

intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN,

drivers/gpu/drm/i915/display/intel_pps.c

120

DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;

drivers/gpu/drm/i915/display/intel_pps.c

130

pll_enabled = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;

drivers/gpu/drm/i915/display/intel_pps.c

1383

pp_on = intel_de_read(display, regs.pp_on);

drivers/gpu/drm/i915/display/intel_pps.c

1384

pp_off = intel_de_read(display, regs.pp_off);

drivers/gpu/drm/i915/display/intel_pps.c

1395

pp_div = intel_de_read(display, regs.pp_div);

drivers/gpu/drm/i915/display/intel_pps.c

1664

intel_de_read(display, regs.pp_on),

drivers/gpu/drm/i915/display/intel_pps.c

1665

intel_de_read(display, regs.pp_off),

drivers/gpu/drm/i915/display/intel_pps.c

1667

intel_de_read(display, regs.pp_div) :

drivers/gpu/drm/i915/display/intel_pps.c

1668

(intel_de_read(display, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));

drivers/gpu/drm/i915/display/intel_pps.c

1830

port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) &

drivers/gpu/drm/i915/display/intel_pps.c

1858

port_sel = intel_de_read(display, PP_ON_DELAYS(display, 0)) &

drivers/gpu/drm/i915/display/intel_pps.c

1866

val = intel_de_read(display, pp_reg);

drivers/gpu/drm/i915/display/intel_pps.c

283

return intel_de_read(display, PP_STATUS(display, pps_idx)) & PP_ON;

drivers/gpu/drm/i915/display/intel_pps.c

288

return intel_de_read(display, PP_CONTROL(display, pps_idx)) & EDP_FORCE_VDD;

drivers/gpu/drm/i915/display/intel_pps.c

303

u32 port_sel = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_pps.c

382

return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;

drivers/gpu/drm/i915/display/intel_pps.c

557

return (intel_de_read(display, _pp_stat_reg(intel_dp)) & PP_ON) != 0;

drivers/gpu/drm/i915/display/intel_pps.c

570

return intel_de_read(display, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;

drivers/gpu/drm/i915/display/intel_pps.c

590

intel_de_read(display, _pp_stat_reg(intel_dp)),

drivers/gpu/drm/i915/display/intel_pps.c

591

intel_de_read(display, _pp_ctrl_reg(intel_dp)));

drivers/gpu/drm/i915/display/intel_pps.c

627

intel_de_read(display, pp_stat_reg),

drivers/gpu/drm/i915/display/intel_pps.c

628

intel_de_read(display, pp_ctrl_reg));

drivers/gpu/drm/i915/display/intel_pps.c

630

ret = poll_timeout_us(val = intel_de_read(display, pp_stat_reg),

drivers/gpu/drm/i915/display/intel_pps.c

638

intel_de_read(display, pp_stat_reg),

drivers/gpu/drm/i915/display/intel_pps.c

639

intel_de_read(display, pp_ctrl_reg));

drivers/gpu/drm/i915/display/intel_pps.c

729

control = intel_de_read(display, _pp_ctrl_reg(intel_dp));

drivers/gpu/drm/i915/display/intel_pps.c

785

intel_de_read(display, pp_stat_reg),

drivers/gpu/drm/i915/display/intel_pps.c

786

intel_de_read(display, pp_ctrl_reg));

drivers/gpu/drm/i915/display/intel_pps.c

857

intel_de_read(display, pp_stat_reg),

drivers/gpu/drm/i915/display/intel_pps.c

858

intel_de_read(display, pp_ctrl_reg));

drivers/gpu/drm/i915/display/intel_psr.c

1128

tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_psr.c

1936

val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_psr.c

1945

val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_psr.c

1960

intel_de_read(display, EDP_PSR2_CTL(display, cpu_transcoder)) & EDP_PSR2_ENABLE);

drivers/gpu/drm/i915/display/intel_psr.c

1963

intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)) & EDP_PSR_ENABLE);

drivers/gpu/drm/i915/display/intel_psr.c

2152

val = intel_de_read(display, psr_iir_reg(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_psr.c

2245

val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_psr.c

2250

val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_psr.c

4153

val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_psr.c

4169

val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_psr.c

4260

val = intel_de_read(display, TRANS_DP2_CTL(cpu_transcoder));

drivers/gpu/drm/i915/display/intel_psr.c

4263

psr2_ctl = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_psr.c

4269

val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_psr.c

4273

val = intel_de_read(display, psr_ctl_reg(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_psr.c

4288

val = intel_de_read(display, psr_perf_cnt_reg(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_psr.c

4312

val = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_sdvo.c

1626

sdvox = intel_de_read(display, intel_sdvo->sdvo_reg);

drivers/gpu/drm/i915/display/intel_sdvo.c

1672

val = intel_de_read(display, sdvo_reg);

drivers/gpu/drm/i915/display/intel_sdvo.c

1714

sdvox = intel_de_read(display, intel_sdvo->sdvo_reg);

drivers/gpu/drm/i915/display/intel_sdvo.c

1849

temp = intel_de_read(display, intel_sdvo->sdvo_reg);

drivers/gpu/drm/i915/display/intel_sdvo.c

1910

temp = intel_de_read(display, intel_sdvo->sdvo_reg);

drivers/gpu/drm/i915/display/intel_sdvo.c

235

cval = intel_de_read(display, GEN3_SDVOC);

drivers/gpu/drm/i915/display/intel_sdvo.c

237

bval = intel_de_read(display, GEN3_SDVOB);

drivers/gpu/drm/i915/display/intel_snps_phy.c

1955

pll_state->mpllb_cp = intel_de_read(display, SNPS_PHY_MPLLB_CP(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1956

pll_state->mpllb_div = intel_de_read(display, SNPS_PHY_MPLLB_DIV(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1957

pll_state->mpllb_div2 = intel_de_read(display, SNPS_PHY_MPLLB_DIV2(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1958

pll_state->mpllb_sscen = intel_de_read(display, SNPS_PHY_MPLLB_SSCEN(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1959

pll_state->mpllb_sscstep = intel_de_read(display, SNPS_PHY_MPLLB_SSCSTEP(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1960

pll_state->mpllb_fracn1 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN1(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1961

pll_state->mpllb_fracn2 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN2(phy));

drivers/gpu/drm/i915/display/intel_snps_phy.c

1969

pll_state->ref_control = intel_de_read(display, SNPS_PHY_REF_CONTROL(phy)) &

drivers/gpu/drm/i915/display/intel_sprite.c

1225

error->ctl = intel_de_read(display, DVSCNTR(crtc->pipe));

drivers/gpu/drm/i915/display/intel_sprite.c

1226

error->surf = intel_de_read(display, DVSSURF(crtc->pipe));

drivers/gpu/drm/i915/display/intel_sprite.c

1227

error->surflive = intel_de_read(display, DVSSURFLIVE(crtc->pipe));

drivers/gpu/drm/i915/display/intel_sprite.c

1244

ret = intel_de_read(display, DVSCNTR(plane->pipe)) & DVS_ENABLE;

drivers/gpu/drm/i915/display/intel_sprite.c

453

error->ctl = intel_de_read(display, SPCNTR(crtc->pipe, plane->id));

drivers/gpu/drm/i915/display/intel_sprite.c

454

error->surf = intel_de_read(display, SPSURF(crtc->pipe, plane->id));

drivers/gpu/drm/i915/display/intel_sprite.c

455

error->surflive = intel_de_read(display, SPSURFLIVE(crtc->pipe, plane->id));

drivers/gpu/drm/i915/display/intel_sprite.c

473

ret = intel_de_read(display, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;

drivers/gpu/drm/i915/display/intel_sprite.c

885

error->ctl = intel_de_read(display, SPRCTL(crtc->pipe));

drivers/gpu/drm/i915/display/intel_sprite.c

886

error->surf = intel_de_read(display, SPRSURF(crtc->pipe));

drivers/gpu/drm/i915/display/intel_sprite.c

887

error->surflive = intel_de_read(display, SPRSURFLIVE(crtc->pipe));

drivers/gpu/drm/i915/display/intel_sprite.c

904

ret = intel_de_read(display, SPRCTL(plane->pipe)) & SPRITE_ENABLE;

drivers/gpu/drm/i915/display/intel_tc.c

1018

pica_isr = intel_de_read(display, PICAINTERRUPT_ISR);

drivers/gpu/drm/i915/display/intel_tc.c

1019

pch_isr = intel_de_read(display, SDEISR);

drivers/gpu/drm/i915/display/intel_tc.c

1042

return intel_de_read(display, reg) & XELPDP_TCSS_POWER_STATE;

drivers/gpu/drm/i915/display/intel_tc.c

1106

val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_tc.c

1150

val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_tc.c

1166

return intel_de_read(display, reg) & XELPDP_TC_PHY_OWNERSHIP;

drivers/gpu/drm/i915/display/intel_tc.c

1569

return intel_de_read(display, DDI_BUF_CTL(dig_port->base.port)) &

drivers/gpu/drm/i915/display/intel_tc.c

275

lane_mask = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia));

drivers/gpu/drm/i915/display/intel_tc.c

314

val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/intel_tc.c

438

val = intel_de_read(display, PORT_TX_DFLEXDPMLE1(tc->phy_fia));

drivers/gpu/drm/i915/display/intel_tc.c

533

fia_isr = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia));

drivers/gpu/drm/i915/display/intel_tc.c

534

pch_isr = intel_de_read(display, SDEISR);

drivers/gpu/drm/i915/display/intel_tc.c

570

val = intel_de_read(display, PORT_TX_DFLEXDPPMS(tc->phy_fia));

drivers/gpu/drm/i915/display/intel_tc.c

589

val = intel_de_read(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia));

drivers/gpu/drm/i915/display/intel_tc.c

614

val = intel_de_read(display, PORT_TX_DFLEXDPCSSS(tc->phy_fia));

drivers/gpu/drm/i915/display/intel_tc.c

777

val = intel_de_read(display, PORT_TX_DFLEXDPSP(FIA1));

drivers/gpu/drm/i915/display/intel_tc.c

823

cpu_isr = intel_de_read(display, GEN11_DE_HPD_ISR);

drivers/gpu/drm/i915/display/intel_tc.c

824

pch_isr = intel_de_read(display, SDEISR);

drivers/gpu/drm/i915/display/intel_tc.c

853

val = intel_de_read(display, TCSS_DDI_STATUS(tc_port));

drivers/gpu/drm/i915/display/intel_tc.c

886

val = intel_de_read(display, DDI_BUF_CTL(port));

drivers/gpu/drm/i915/display/intel_tv.c

1106

tv_ctl = intel_de_read(display, TV_CTL);

drivers/gpu/drm/i915/display/intel_tv.c

1107

hctl1 = intel_de_read(display, TV_H_CTL_1);

drivers/gpu/drm/i915/display/intel_tv.c

1108

hctl3 = intel_de_read(display, TV_H_CTL_3);

drivers/gpu/drm/i915/display/intel_tv.c

1109

vctl1 = intel_de_read(display, TV_V_CTL_1);

drivers/gpu/drm/i915/display/intel_tv.c

1110

vctl2 = intel_de_read(display, TV_V_CTL_2);

drivers/gpu/drm/i915/display/intel_tv.c

1145

tmp = intel_de_read(display, TV_WIN_POS);

drivers/gpu/drm/i915/display/intel_tv.c

1149

tmp = intel_de_read(display, TV_WIN_SIZE);

drivers/gpu/drm/i915/display/intel_tv.c

1452

tv_ctl = intel_de_read(display, TV_CTL);

drivers/gpu/drm/i915/display/intel_tv.c

1578

intel_de_read(display, TV_DAC) & TV_DAC_SAVE);

drivers/gpu/drm/i915/display/intel_tv.c

1601

save_tv_dac = tv_dac = intel_de_read(display, TV_DAC);

drivers/gpu/drm/i915/display/intel_tv.c

1602

save_tv_ctl = tv_ctl = intel_de_read(display, TV_CTL);

drivers/gpu/drm/i915/display/intel_tv.c

1635

tv_dac = intel_de_read(display, TV_DAC);

drivers/gpu/drm/i915/display/intel_tv.c

1938

if ((intel_de_read(display, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)

drivers/gpu/drm/i915/display/intel_tv.c

1950

save_tv_dac = intel_de_read(display, TV_DAC);

drivers/gpu/drm/i915/display/intel_tv.c

1953

tv_dac_on = intel_de_read(display, TV_DAC);

drivers/gpu/drm/i915/display/intel_tv.c

1956

tv_dac_off = intel_de_read(display, TV_DAC);

drivers/gpu/drm/i915/display/intel_tv.c

919

u32 tmp = intel_de_read(display, TV_CTL);

drivers/gpu/drm/i915/display/intel_vblank.c

135

return intel_de_read(display, PIPE_FRMCOUNT_G4X(display, pipe));

drivers/gpu/drm/i915/display/intel_vblank.c

488

line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;

drivers/gpu/drm/i915/display/intel_vblank.c

490

line2 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;

drivers/gpu/drm/i915/display/intel_vdsc.c

1037

dss_ctl1 = intel_de_read(display, dss_ctl1_reg(crtc, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_vdsc.c

1038

dss_ctl2 = intel_de_read(display, dss_ctl2_reg(crtc, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_vdsc.c

892

val = intel_de_read(display, dsc_reg[0]);

drivers/gpu/drm/i915/display/intel_vdsc.c

895

if (intel_de_read(display, dsc_reg[i]) != val) {

drivers/gpu/drm/i915/display/intel_vga.c

53

tmp = intel_de_read(display, vga_reg);

drivers/gpu/drm/i915/display/intel_vrr.c

1001

intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(pipe));

drivers/gpu/drm/i915/display/intel_vrr.c

1003

intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(pipe));

drivers/gpu/drm/i915/display/intel_vrr.c

1005

intel_de_read(display, PIPEDMC_DCB_SLOPE(pipe));

drivers/gpu/drm/i915/display/intel_vrr.c

1007

intel_de_read(display, PIPEDMC_DCB_VBLANK(pipe));

drivers/gpu/drm/i915/display/intel_vrr.c

1017

trans_vrr_ctl = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_vrr.c

1047

crtc_state->vrr.flipline = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_vrr.c

1049

crtc_state->vrr.vmax = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_vrr.c

1051

crtc_state->vrr.vmin = intel_de_read(display,

drivers/gpu/drm/i915/display/intel_vrr.c

1075

intel_de_read(display,

drivers/gpu/drm/i915/display/intel_vrr.c

1149

tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder));

drivers/gpu/drm/i915/display/intel_vrr.c

1163

tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder));

drivers/gpu/drm/i915/display/intel_vrr.c

1177

tmp = intel_de_read(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder));

drivers/gpu/drm/i915/display/intel_vrr.c

1188

tmp = intel_de_read(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder));

drivers/gpu/drm/i915/display/intel_vrr.c

610

!(intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE));

drivers/gpu/drm/i915/display/intel_vrr.c

753

return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND;

drivers/gpu/drm/i915/display/intel_vrr.c

805

u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_vrr.c

856

u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder));

drivers/gpu/drm/i915/display/intel_vrr.c

992

reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe));

drivers/gpu/drm/i915/display/intel_vrr.c

995

reg_val = intel_de_read(display, PIPEDMC_DCB_VMAX(pipe));

drivers/gpu/drm/i915/display/intel_vrr.c

999

intel_de_read(display, PIPEDMC_DCB_GUARDBAND(pipe));

drivers/gpu/drm/i915/display/skl_scaler.c

979

ctl = intel_de_read(display, SKL_PS_CTRL(crtc->pipe, i));

drivers/gpu/drm/i915/display/skl_scaler.c

992

pos = intel_de_read(display, SKL_PS_WIN_POS(crtc->pipe, i));

drivers/gpu/drm/i915/display/skl_scaler.c

993

size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, i));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1702

error->ctl = intel_de_read(display, PLANE_CTL(crtc->pipe, plane->id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1703

error->surf = intel_de_read(display, PLANE_SURF(crtc->pipe, plane->id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

1704

error->surflive = intel_de_read(display, PLANE_SURFLIVE(crtc->pipe, plane->id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

2831

plane_ctl = intel_de_read(display, PLANE_CTL(plane->pipe, plane->id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

3082

val = intel_de_read(display, PLANE_CTL(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

3092

color_ctl = intel_de_read(display, PLANE_COLOR_CTL(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

3184

base = intel_de_read(display, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK;

drivers/gpu/drm/i915/display/skl_universal_plane.c

3187

offset = intel_de_read(display, PLANE_OFFSET(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

3190

val = intel_de_read(display, PLANE_SIZE(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

3194

val = intel_de_read(display, PLANE_STRIDE(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_universal_plane.c

949

ret = intel_de_read(display, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;

drivers/gpu/drm/i915/display/skl_watermark.c

111

val = intel_de_read(display, MTL_LATENCY_SAGV);

drivers/gpu/drm/i915/display/skl_watermark.c

2991

val = intel_de_read(display, PLANE_WM(pipe, plane_id, level));

drivers/gpu/drm/i915/display/skl_watermark.c

2993

val = intel_de_read(display, CUR_WM(pipe, level));

drivers/gpu/drm/i915/display/skl_watermark.c

2999

val = intel_de_read(display, PLANE_WM_TRANS(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_watermark.c

3001

val = intel_de_read(display, CUR_WM_TRANS(pipe));

drivers/gpu/drm/i915/display/skl_watermark.c

3007

val = intel_de_read(display, PLANE_WM_SAGV(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_watermark.c

3009

val = intel_de_read(display, CUR_WM_SAGV(pipe));

drivers/gpu/drm/i915/display/skl_watermark.c

3014

val = intel_de_read(display, PLANE_WM_SAGV_TRANS(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_watermark.c

3016

val = intel_de_read(display, CUR_WM_SAGV_TRANS(pipe));

drivers/gpu/drm/i915/display/skl_watermark.c

3033

dbuf_state->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;

drivers/gpu/drm/i915/display/skl_watermark.c

3265

val = intel_de_read(display, MTL_LATENCY_LP0_LP1);

drivers/gpu/drm/i915/display/skl_watermark.c

3269

val = intel_de_read(display, MTL_LATENCY_LP2_LP3);

drivers/gpu/drm/i915/display/skl_watermark.c

3273

val = intel_de_read(display, MTL_LATENCY_LP4_LP5);

drivers/gpu/drm/i915/display/skl_watermark.c

691

val = intel_de_read(display, CUR_BUF_CFG(pipe));

drivers/gpu/drm/i915/display/skl_watermark.c

696

val = intel_de_read(display, PLANE_BUF_CFG(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_watermark.c

700

val = intel_de_read(display, PLANE_MIN_BUF_CFG(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_watermark.c

709

val = intel_de_read(display, PLANE_NV12_BUF_CFG(pipe, plane_id));

drivers/gpu/drm/i915/display/skl_watermark.c

83

if (intel_de_read(display, DBUF_CTL_S(slice)) & DBUF_POWER_STATE)

drivers/gpu/drm/i915/display/vlv_dsi.c

1035

if (intel_de_read(display, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)

drivers/gpu/drm/i915/display/vlv_dsi.c

1039

fmt = intel_de_read(display, MIPI_DSI_FUNC_PRG(display, port)) & VID_MODE_FORMAT_MASK;

drivers/gpu/drm/i915/display/vlv_dsi.c

1051

intel_de_read(display,

drivers/gpu/drm/i915/display/vlv_dsi.c

1054

intel_de_read(display,

drivers/gpu/drm/i915/display/vlv_dsi.c

1057

intel_de_read(display,

drivers/gpu/drm/i915/display/vlv_dsi.c

1061

hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port));

drivers/gpu/drm/i915/display/vlv_dsi.c

1067

hsync = intel_de_read(display, MIPI_HSYNC_PADDING_COUNT(display, port));

drivers/gpu/drm/i915/display/vlv_dsi.c

1068

hbp = intel_de_read(display, MIPI_HBP_COUNT(display, port));

drivers/gpu/drm/i915/display/vlv_dsi.c

1085

vfp = intel_de_read(display, MIPI_VFP_COUNT(display, port));

drivers/gpu/drm/i915/display/vlv_dsi.c

1086

vbp = intel_de_read(display, MIPI_VBP_COUNT(display, port));

drivers/gpu/drm/i915/display/vlv_dsi.c

1087

vsync = intel_de_read(display, MIPI_VSYNC_PADDING_COUNT(display, port));

drivers/gpu/drm/i915/display/vlv_dsi.c

125

u32 val = intel_de_read(display, reg);

drivers/gpu/drm/i915/display/vlv_dsi.c

1331

tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A));

drivers/gpu/drm/i915/display/vlv_dsi.c

1337

tmp = intel_de_read(display, MIPI_CTRL(display, port));

drivers/gpu/drm/i915/display/vlv_dsi.c

242

if (cmd == intel_de_read(display, MIPI_DPI_CONTROL(display, port)))

drivers/gpu/drm/i915/display/vlv_dsi.c

347

u32 tmp = intel_de_read(display, MIPI_DEVICE_READY(display, port));

drivers/gpu/drm/i915/display/vlv_dsi.c

363

!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY);

drivers/gpu/drm/i915/display/vlv_dsi.c

387

if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) {

drivers/gpu/drm/i915/display/vlv_dsi.c

448

val = intel_de_read(display, MIPI_DEVICE_READY(display, port));

drivers/gpu/drm/i915/display/vlv_dsi.c

638

temp = intel_de_read(display, port_ctrl);

drivers/gpu/drm/i915/display/vlv_dsi.c

962

bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE;

drivers/gpu/drm/i915/display/vlv_dsi.c

971

enabled = intel_de_read(display,

drivers/gpu/drm/i915/display/vlv_dsi.c

976

u32 tmp = intel_de_read(display,

drivers/gpu/drm/i915/display/vlv_dsi.c

984

if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY))

drivers/gpu/drm/i915/display/vlv_dsi.c

988

u32 tmp = intel_de_read(display, MIPI_CTRL(display, port));

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

278

val = intel_de_read(display, BXT_DSI_PLL_ENABLE);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

292

val = intel_de_read(display, BXT_DSI_PLL_CTL);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

366

config->dsi_pll.ctrl = intel_de_read(display, BXT_DSI_PLL_CTL);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

382

temp = intel_de_read(display, MIPI_CTRL(display, port));

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

447

tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL);

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

588

tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL);