in_le32
#define isa_inl(port) (ISA_SEX ? in_be32(isa_itl(port)) : in_le32(isa_itl(port)))
#define readl(addr) in_le32(addr)
if (!(in_le32(&pci_regs[0][32]) & 1)) {
out_le32(&pci_regs[0][65], in_le32(&pci_regs[0][65]) | 6);
while(in_le32(&((regs)->status)) & (RUN)) \
while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH)) \
u32 val = in_le32(addr);
DEF_MMIO_IN_X(in_le32, 32, lwbrx);
DEF_MMIO_IN_D(in_le32, 32, lwz);
#define __do_readl(addr) in_le32(addr)
#define MACIO_IN32(r) (in_le32(MACIO_FCR32(macio,r)))
*((u32 *)val) = in_le32(addr);
while (attempt && (0 == (in_le32(mbase + PECFG_460SX_DLLSTA)
val = in_le32(mbase + PECFG_TLDLP);
*val = in_le32((u32 *)(addr + offset));
pix_fmt = in_le32(vaddr);
diu_shared_fb.fb_phys = in_le32(vaddr + 4);
value = in_le32(hose->cfg_data);
value = in_le32(hose->cfg_data);
in_le32(&Hydra->Feature_Control));
printk(", now %x\n", in_le32(&Hydra->Feature_Control));
*val = in_le32(cfg_data);
sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
t = in_le32(gg2_pci_config_base+
t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
return in_le32(iob_regs+reg);
return in_le32(mac_regs[intf]+reg);
return in_le32(dma_regs+reg);
return !!(in_le32(gpio_regs+0x40) & (1 << MDIO_PIN(bus)));
regword = in_le32(iob+IOB_AD_REG);
regword = in_le32(iob+IOBCOM_REG);
out_le32(iob_mapbase + PXP_ERR_CFG_REG, in_le32(iob_mapbase + PXP_ERR_CFG_REG) | PXP_IGNORE_PCIE_ERRORS);
out_le32(iob_mapbase + PXP_ERR_CFG_REG, in_le32(iob_mapbase + PXP_ERR_CFG_REG) & ~PXP_IGNORE_PCIE_ERRORS);
*val = in_le32(addr);
tmp = in_le32(addr);
in_le32(mce_regs[i].addr));
save[i].cmdptr_hi = in_le32(&chan->cmdptr_hi);
save[i].cmdptr = in_le32(&chan->cmdptr);
save[i].intr_sel = in_le32(&chan->intr_sel);
save[i].br_sel = in_le32(&chan->br_sel);
save[i].wait_sel = in_le32(&chan->wait_sel);
while (in_le32(&chan->status) & ACTIVE)
} while (in_le32(hose->cfg_addr) != caddr);
*val = swap ? in_le32(addr) : in_be32(addr);
} while (in_le32(hose->cfg_addr) != caddr);
vendev = in_le32(bp->cfg_data);
magic = in_le32(bp->cfg_data);
(void)in_le32(&pmac_irq_hw[i]->ack);
} while((in_le32(&pmac_irq_hw[i]->enable) & bit)
if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
bits |= in_le32(&pmac_irq_hw[i]->level);
bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
bits |= in_le32(&pmac_irq_hw[i]->level);
(void)in_le32(&pmac_irq_hw[0]->event);
(void)in_le32(&pmac_irq_hw[0]->enable);
} while((in_le32(&pmac_irq_hw[i]->enable) & bit)
cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
if (!(in_le32(&in[i].ar) & PEX_RCIWARn_EN))
if (get_immrbase() == in_le32(&in[i].tar))
return (u64)in_le32(&in[i].barh) << 32 |
in_le32(&in[i].barl);
val = in_le32(bp->cfg_data);
(void)in_le32(bp->cfg_data);
*val = in_le32(cfg_data);
return in_le32(rb->base + (reg >> 2));
for (n = 0; (in_le32(&dr->status) & ACTIVE) && n < 1000; n++)
data = (in_le32(rng_regs + SDCRNG_CTL_REG)
*data = in_le32(rng_regs + SDCRNG_VAL_REG);
in_le32(rng_regs + SDCRNG_CTL_REG) & ~ctl);
ret = in_le32(sdcpwr_mapbase + SDCPWR_CFGA0_REG + (astate * 0x10));
ret = in_le32(sdcpwr_mapbase + SDCPWR_PWST0_REG);
giztime = in_le32(sdcpwr_mapbase + SDCPWR_GIZTIME_REG);
busy = (in_le32(dev->trng_base + PPC4XX_TRNG_STAT) &
*data = in_le32(dev->trng_base + PPC4XX_TRNG_DATA);
: in_le32(fdev->regs);
#define fsl_ioread32(p) in_le32(p)
u32 val_lo = in_le32((u32 __iomem *)addr);
u32 val_hi = in_le32((u32 __iomem *)addr + 1);
#define MB_IN32(bay,r) (in_le32(MB_FCR32(bay,r)))
(void)in_le32(rm->i2s_regs + 0x10);
(void)in_le32(&rm->dma_regs->status);
if (cp == bus_to_virt(in_le32(&bp->tx_dma->cmdptr)))
while ((in_le32(&rd->status) & ACTIVE) != 0)
gpio = in_le32(cf->gpio_base+0x40);
&& (in_le32(&md->status) & ACTIVE) != 0) {
in_le32(&md->status), in_le32(&md->cmdptr));
return in_le32(p);
return in_le32(p);
return in_le32(par->ati_regbase + regindex);
sense = (in_le32(CNTRL_REG(p,mon_sense)) & 0x1c0) << 2;
sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0xc0) >> 2;
sense |= ((in_le32(CNTRL_REG(p,mon_sense)) & 0x100) >> 5)
| ((in_le32(CNTRL_REG(p,mon_sense)) & 0x40) >> 4);
sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0x180) >> 7;
ctrl = in_le32(CNTRL_REG(p, ctrl));
return in_le32(base + regindex);
in_le32(par->cmap_adr + 0x58) & ~0x20);
in_le32(par->cmap_adr + 0x58) | 0x20);
in_le32(par->cmap_adr + 0x58) & ~0x20);
in_le32(par->cmap_adr + 0x58) | 0x20);
intreg = in_le32(&dev->intfregs->intr_ctl);
while (in_le32(&pi->dbdma->status) & ACTIVE) {
if (in_le32(&i2sdev->intfregs->serial_format) == sfr
&& in_le32(&i2sdev->intfregs->data_word_sizes) == dws)
!(in_le32(&i2sdev->intfregs->intr_ctl) & I2S_PENDING_CLOCKS_STOPPED)) {
if (in_le32(&pi->dbdma->status) & ACTIVE) {
if (in_le32(&pi->dbdma->status) & ACTIVE) {
pi->frame_count = in_le32(&i2sdev->intfregs->frame_count);
fc = in_le32(&i2sdev->intfregs->frame_count);
fc = in_le32(&i2sdev->intfregs->frame_count);
status = in_le32(&pi->dbdma->status);
while (!(in_le32(&chip->awacs->codec_stat) & MASK_VALID)) {
while (in_le32(&chip->awacs->codec_ctrl) & MASK_NEWECMD) {
return (in_le32(&chip->awacs->codec_stat) & chip->hp_stat_mask) ? 1 : 0;
chip->manufacturer = (in_le32(&chip->awacs->codec_stat) >> 8) & 0xf;
chip->revision = (in_le32(&chip->awacs->codec_stat) >> 12) & 0xf;
val += (in_le32(&chip->awacs->codec_stat) >> 4) & 0xff;
while ((in_le32(&chip->awacs->codec_ctrl) & MASK_NEWECMD) && timeout--)
while (!(in_le32(&chip->awacs->codec_stat) & MASK_EXTEND) && timeout--)
while ((in_le32(&chip->awacs->codec_stat) & MASK_EXTEND) && timeout--)
return (in_le32(&chip->awacs->codec_stat) & chip->hp_stat_mask) ? 1 : 0;
if ((in_le32(&chip->awacs->codec_ctrl) & MASK_ERRCODE) == 0xf0000) {
val += (in_le32(&chip->awacs->codec_stat) >> 4) & 0xff;
val += ((in_le32(&chip->awacs->codec_stat)>>4) & 0xff) <<8;
val += ((in_le32(&chip->awacs->codec_stat)>>4) & 0xff) <<16;
val += ((in_le32(&chip->awacs->codec_stat)>>4) & 0xff) <<24;
while ((in_le32(&rec->dma->status) & RUN) && timeout-- > 0)
(void)in_le32(&rec->dma->status);
(void)in_le32(&rec->dma->status);
(void)in_le32(&rec->dma->status);
(in_le32(&chip->awacs->control) & ~0x1f00)
int ctrl = in_le32(&chip->awacs->control);
int err = (in_le32(&chip->awacs->codec_stat) & MASK_ERRCODE) >> 16;
out_le32(&chip->awacs->control, in_le32(&chip->awacs->control) & 0xfff);