idma
iomd_get_next_sg(idma);
writel(idma->cur_addr, base + cur);
writel(idma->cur_len, base + end);
idma->cur_len == (DMA_END_S|DMA_END_L))
idma->state = state;
struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
return request_irq(idma->irq, iomd_dma_handle,
0, idma->dma.device_id, idma);
struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
free_irq(idma->irq, idma);
struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
void __iomem *base = idma->base;
if (idma->dma.invalid) {
idma->dma.invalid = 0;
if (!idma->dma.sg) {
idma->dma.sg = &idma->dma.buf;
idma->dma.sgcount = 1;
idma->dma.buf.length = idma->dma.count;
idma->dma.buf.dma_address = dma_map_single(&isa_dma_dev,
idma->dma.addr, idma->dma.count,
idma->dma.dma_mode == DMA_MODE_READ ?
idma->dma_addr = idma->dma.sg->dma_address;
idma->dma_len = idma->dma.sg->length;
idma->state = DMA_ST_AB;
if (idma->dma.dma_mode == DMA_MODE_READ)
enable_irq(idma->irq);
struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
void __iomem *base = idma->base;
if (idma->state != ~DMA_ST_AB)
disable_irq(idma->irq);
static void iomd_get_next_sg(struct iomd_dma *idma)
if (idma->dma.sg) {
idma->cur_addr = idma->dma_addr;
offset = idma->cur_addr & ~PAGE_MASK;
end = offset + idma->dma_len;
idma->cur_len = end - TRANSFER_SIZE;
idma->dma_len -= end - offset;
idma->dma_addr += end - offset;
if (idma->dma_len == 0) {
if (idma->dma.sgcount > 1) {
idma->dma.sg = sg_next(idma->dma.sg);
idma->dma_addr = idma->dma.sg->dma_address;
idma->dma_len = idma->dma.sg->length;
idma->dma.sgcount--;
idma->dma.sg = NULL;
idma->cur_addr = 0;
idma->cur_len = 0;
idma->cur_len |= flags;
struct iomd_dma *idma = dev_id;
void __iomem *base = idma->base;
unsigned int state = idma->state;
dma = out ? &io->port->dev->odma[nr] : &io->port->dev->idma[nr];
dma->regs = rm->idma->base + rm->idma->size * nr;
.idma = &octopus_idma,
struct ddb_dma idma[DDB_MAX_INPUT];
const struct ddb_regset *idma;
if (!idma->bounce_buf) {
idma->bounce_buf = dmam_alloc_coherent(dev,
&idma->bounce_dma_addr,
if (!idma->bounce_buf) {
idma->use_bounce_buffer = true;
struct sdmmc_idma *idma = host->dma_priv;
if (idma->use_bounce_buffer) {
idma->bounce_buf, xfer_bytes);
struct sdmmc_idma *idma = host->dma_priv;
if (idma->use_bounce_buffer) {
idma->bounce_buf, xfer_bytes);
struct sdmmc_idma *idma;
idma = devm_kzalloc(dev, sizeof(*idma), GFP_KERNEL);
if (!idma)
host->dma_priv = idma;
idma->sg_cpu = dmam_alloc_coherent(dev, SDMMC_LLI_BUF_LEN,
&idma->sg_dma, GFP_KERNEL);
if (!idma->sg_cpu) {
struct sdmmc_idma *idma = host->dma_priv;
struct sdmmc_lli_desc *desc = (struct sdmmc_lli_desc *)idma->sg_cpu;
idma->use_bounce_buffer) {
if (idma->use_bounce_buffer)
dma_addr = idma->bounce_dma_addr;
writel_relaxed(idma->sg_dma, host->base + MMCI_STM32_IDMABAR);
struct sdmmc_idma *idma = host->dma_priv;
if (!idma->use_bounce_buffer)
struct sdmmc_idma *idma = host->dma_priv;
idma->use_bounce_buffer = false;
struct sge_idma_monitor_state *idma);
struct sge_idma_monitor_state *idma,
struct sge_idma_monitor_state *idma)
idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
idma->idma_stalled[0] = 0;
idma->idma_stalled[1] = 0;
struct sge_idma_monitor_state *idma,
if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
i, idma->idma_qid[i],
idma->idma_stalled[i] / hz);
idma->idma_stalled[i] = 0;
if (idma->idma_stalled[i] == 0) {
idma->idma_stalled[i] = hz;
idma->idma_warn[i] = 0;
idma->idma_stalled[i] += ticks;
idma->idma_warn[i] -= ticks;
if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
if (idma->idma_warn[i] > 0)
idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
i, idma->idma_qid[i], idma->idma_state[i],
idma->idma_stalled[i] / hz,
t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
u32 val = readl(idma.regs + I2SAHB);
guard(spinlock)(&idma.lock);
writel(val, idma.regs + I2SAHB);
u32 mod = readl(idma.regs + I2SMOD);
u32 ahb = readl(idma.regs + I2SAHB);
writel(ahb, idma.regs + I2SAHB);
writel(mod, idma.regs + I2SMOD);
iisahb = readl(idma.regs + I2SAHB);
writel(iisahb, idma.regs + I2SAHB);
addr = readl(idma.regs + I2SLVL0ADDR) - idma.lp_tx_addr;
addr += idma.lp_tx_addr;
writel(addr, idma.regs + I2SLVL0ADDR);
buf->addr = idma.lp_tx_addr;
spin_lock_init(&idma.lock);
idma.regs = regs;
idma.lp_tx_addr = addr;
} idma;
*src = idma.lp_tx_addr +
(readl(idma.regs + I2STRNCNT) & 0xffffff) * 4;
val = idma.lp_tx_addr + prtd->periodsz;
writel(val, idma.regs + I2SLVL0ADDR);
val = idma.lp_tx_addr;
writel(val, idma.regs + I2SSTR0);
val = readl(idma.regs + I2SSIZE);
writel(val, idma.regs + I2SSIZE);
val = readl(idma.regs + I2SAHB);
writel(val, idma.regs + I2SAHB);