drivers/gpu/drm/i915/display/intel_display_reg_defs.h

11

typedef i915_reg_t intel_reg_t;

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

170

static i915_reg_t gen12_get_aux_inv_reg(struct intel_engine_cs *engine)

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

192

i915_reg_t reg = gen12_get_aux_inv_reg(engine);

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

203

i915_reg_t inv_reg = gen12_get_aux_inv_reg(engine);

drivers/gpu/drm/i915/gt/intel_engine_cs.c

1628

const i915_reg_t mode = RING_MI_MODE(engine->mmio_base);

drivers/gpu/drm/i915/gt/intel_engine_cs.c

1700

static const i915_reg_t _reg[I915_NUM_ENGINES] = {

drivers/gpu/drm/i915/gt/intel_engine_types.h

354

i915_reg_t reg;

drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c

143

i915_reg_t reg = FENCE_REG(fence->id);

drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c

168

i915_reg_t reg = FENCE_REG(fence->id);

drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c

64

i915_reg_t fence_reg_lo, fence_reg_hi;

drivers/gpu/drm/i915/gt/intel_gt.c

233

i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt)

drivers/gpu/drm/i915/gt/intel_gt.c

369

i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;

drivers/gpu/drm/i915/gt/intel_gt.h

148

i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt);

drivers/gpu/drm/i915/gt/intel_gt_mcr.c

186

static i915_reg_t mcr_reg_cast(const i915_mcr_reg_t mcr)

drivers/gpu/drm/i915/gt/intel_gt_mcr.c

188

i915_reg_t r = { .reg = mcr.reg };

drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c

18

i915_reg_t reg;

drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c

65

i915_reg_t reg = GRAPHICS_VER(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;

drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c

79

i915_reg_t reg;

drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c

512

i915_reg_t (*reg32)(struct intel_gt *gt);

drivers/gpu/drm/i915/gt/intel_lrc.c

1715

i915_reg_t reg;

drivers/gpu/drm/i915/gt/intel_rc6.c

578

i915_reg_t res_reg[INTEL_RC6_RES_MAX] = {

drivers/gpu/drm/i915/gt/intel_rc6.c

744

static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg)

drivers/gpu/drm/i915/gt/intel_rc6.c

794

i915_reg_t reg = rc6->res_reg[id];

drivers/gpu/drm/i915/gt/intel_rc6.c

861

i915_reg_t reg = gt->rc6.res_reg[id];

drivers/gpu/drm/i915/gt/intel_rc6_types.h

27

i915_reg_t res_reg[INTEL_RC6_RES_MAX];

drivers/gpu/drm/i915/gt/intel_reset.c

367

i915_reg_t lock_reg;

drivers/gpu/drm/i915/gt/intel_reset.c

368

i915_reg_t ack_reg;

drivers/gpu/drm/i915/gt/intel_reset.c

369

i915_reg_t usage_reg;

drivers/gpu/drm/i915/gt/intel_reset.c

565

const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);

drivers/gpu/drm/i915/gt/intel_ring_submission.c

814

i915_reg_t last_reg = INVALID_MMIO_REG; /* keep gcc quiet */

drivers/gpu/drm/i915/gt/intel_ring_submission.c

82

i915_reg_t hwsp;

drivers/gpu/drm/i915/gt/intel_rps.c

2083

i915_reg_t rpstat;

drivers/gpu/drm/i915/gt/intel_rps.c

2117

i915_reg_t r = INVALID_MMIO_REG;

drivers/gpu/drm/i915/gt/intel_rps.c

2710

static u32 rps_read_mmio(struct intel_rps *rps, i915_reg_t reg32)

drivers/gpu/drm/i915/gt/intel_rps.c

2723

i915_reg_t reg32, u32 mask)

drivers/gpu/drm/i915/gt/intel_rps.c

75

static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)

drivers/gpu/drm/i915/gt/intel_rps.h

63

bool rps_read_mask_mmio(struct intel_rps *rps, i915_reg_t reg32, u32 mask);

drivers/gpu/drm/i915/gt/intel_sseu.c

204

fuse_val[i] = intel_uncore_read(uncore, va_arg(argp, i915_reg_t));

drivers/gpu/drm/i915/gt/intel_workarounds.c

1272

i915_reg_t steering_reg,

drivers/gpu/drm/i915/gt/intel_workarounds.c

1863

whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)

drivers/gpu/drm/i915/gt/intel_workarounds.c

1898

whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)

drivers/gpu/drm/i915/gt/intel_workarounds.c

218

static void wa_add(struct i915_wa_list *wal, i915_reg_t reg,

drivers/gpu/drm/i915/gt/intel_workarounds.c

248

wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)

drivers/gpu/drm/i915/gt/intel_workarounds.c

260

wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)

drivers/gpu/drm/i915/gt/intel_workarounds.c

266

wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)

drivers/gpu/drm/i915/gt/intel_workarounds.c

278

wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)

drivers/gpu/drm/i915/gt/intel_workarounds.c

301

wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)

drivers/gpu/drm/i915/gt/intel_workarounds.c

313

wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)

drivers/gpu/drm/i915/gt/intel_workarounds.c

325

wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,

drivers/gpu/drm/i915/gt/intel_workarounds_types.h

17

i915_reg_t reg;

drivers/gpu/drm/i915/gt/selftest_engine_cs.c

44

static i915_reg_t timestamp_reg(struct intel_engine_cs *engine)

drivers/gpu/drm/i915/gt/selftest_engine_pm.c

57

static u32 *emit_srm(u32 *cs, i915_reg_t reg, u32 offset)

drivers/gpu/drm/i915/gt/selftest_workarounds.c

1007

u32 a, u32 b, i915_reg_t reg)

drivers/gpu/drm/i915/gt/selftest_workarounds.c

1024

i915_reg_t reg))

drivers/gpu/drm/i915/gt/selftest_workarounds.c

180

i915_reg_t reg = i < engine->whitelist.count ?

drivers/gpu/drm/i915/gt/selftest_workarounds.c

952

i915_reg_t reg;

drivers/gpu/drm/i915/gt/selftest_workarounds.c

957

i915_reg_t reg,

drivers/gpu/drm/i915/gt/selftest_workarounds.c

973

static bool pardon_reg(struct drm_i915_private *i915, i915_reg_t reg)

drivers/gpu/drm/i915/gt/selftest_workarounds.c

985

u32 a, u32 b, i915_reg_t reg)

drivers/gpu/drm/i915/gt/selftest_workarounds.c

996

static bool writeonly_reg(struct drm_i915_private *i915, i915_reg_t reg)

drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h

89

i915_reg_t reg;

drivers/gpu/drm/i915/gt/uc/intel_guc.c

57

static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)

drivers/gpu/drm/i915/gt/uc/intel_guc.h

234

i915_reg_t notify_reg;

drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c

1505

i915_reg_t reg_ipehr = RING_IPEHR(0);

drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c

1506

i915_reg_t reg_instdone = RING_INSTDONE(0);

drivers/gpu/drm/i915/gt/uc/intel_huc.h

38

i915_reg_t reg;

drivers/gpu/drm/i915/gvt/aperture_gm.c

140

i915_reg_t fence_reg_lo, fence_reg_hi;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1277

i915_reg_t stride_reg;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1278

i915_reg_t ctrl_reg;

drivers/gpu/drm/i915/gvt/cmd_parser.c

1279

i915_reg_t surf_reg;

drivers/gpu/drm/i915/gvt/gvt.h

256

i915_reg_t offset;

drivers/gpu/drm/i915/gvt/handlers.c

737

static i915_reg_t force_nonpriv_white_list[] = {

drivers/gpu/drm/i915/gvt/handlers.c

775

i915_reg_t *array = force_nonpriv_white_list;

drivers/gpu/drm/i915/gvt/handlers.c

858

i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;

drivers/gpu/drm/i915/gvt/handlers.c

898

static unsigned int calc_index(unsigned int offset, i915_reg_t _start,

drivers/gpu/drm/i915/gvt/handlers.c

899

i915_reg_t _next, i915_reg_t _end)

drivers/gpu/drm/i915/gvt/handlers.c

924

i915_reg_t fdi_rx_iir;

drivers/gpu/drm/i915/gvt/handlers.c

968

i915_reg_t status_reg;

drivers/gpu/drm/i915/gvt/interrupt.c

46

i915_reg_t reg_base;

drivers/gpu/drm/i915/gvt/mmio_context.c

185

i915_reg_t offset;

drivers/gpu/drm/i915/gvt/mmio_context.c

374

i915_reg_t reg;

drivers/gpu/drm/i915/gvt/mmio_context.c

423

i915_reg_t offset, l3_offset;

drivers/gpu/drm/i915/gvt/mmio_context.c

55

i915_reg_t reg;

drivers/gpu/drm/i915/gvt/scheduler.c

279

i915_reg_t reg;

drivers/gpu/drm/i915/i915_cmd_parser.c

576

i915_reg_t addr;

drivers/gpu/drm/i915/i915_gpu_error.c

1354

i915_reg_t mmio;

drivers/gpu/drm/i915/i915_hwmon.c

102

hwm_field_read_and_scale(struct hwm_drvdata *ddat, i915_reg_t rgadr,

drivers/gpu/drm/i915/i915_hwmon.c

144

i915_reg_t rgaddr;

drivers/gpu/drm/i915/i915_hwmon.c

37

i915_reg_t gt_perf_status;

drivers/gpu/drm/i915/i915_hwmon.c

38

i915_reg_t pkg_temp;

drivers/gpu/drm/i915/i915_hwmon.c

39

i915_reg_t pkg_power_sku_unit;

drivers/gpu/drm/i915/i915_hwmon.c

40

i915_reg_t pkg_power_sku;

drivers/gpu/drm/i915/i915_hwmon.c

41

i915_reg_t pkg_rapl_limit;

drivers/gpu/drm/i915/i915_hwmon.c

42

i915_reg_t energy_status_all;

drivers/gpu/drm/i915/i915_hwmon.c

43

i915_reg_t energy_status_tile;

drivers/gpu/drm/i915/i915_hwmon.c

44

i915_reg_t fan_speed;

drivers/gpu/drm/i915/i915_hwmon.c

585

i915_reg_t rgaddr;

drivers/gpu/drm/i915/i915_hwmon.c

81

i915_reg_t reg, u32 clear, u32 set)

drivers/gpu/drm/i915/i915_ioctl.c

23

i915_reg_t offset_ldw;

drivers/gpu/drm/i915/i915_ioctl.c

24

i915_reg_t offset_udw;

drivers/gpu/drm/i915/i915_irq.c

174

i915_reg_t reg;

drivers/gpu/drm/i915/i915_irq.c

96

void gen2_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)

drivers/gpu/drm/i915/i915_irq.h

36

void gen2_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg);

drivers/gpu/drm/i915/i915_perf.c

1324

__store_reg_to_mem(struct i915_request *rq, i915_reg_t reg, u32 ggtt_offset)

drivers/gpu/drm/i915/i915_perf.c

1347

__read_reg(struct intel_context *ce, i915_reg_t reg, u32 ggtt_offset)

drivers/gpu/drm/i915/i915_perf.c

1492

i915_reg_t reg = GEN12_OACTXCONTROL(ce->engine->mmio_base);

drivers/gpu/drm/i915/i915_perf.c

1915

bool save, i915_reg_t reg, u32 offset,

drivers/gpu/drm/i915/i915_perf.c

1958

i915_reg_t mi_predicate_result = HAS_MI_SET_PREDICATE(i915) ?

drivers/gpu/drm/i915/i915_perf.c

2420

i915_reg_t reg)

drivers/gpu/drm/i915/i915_perf.c

2454

static const i915_reg_t flex_regs[] = {

drivers/gpu/drm/i915/i915_perf.c

2477

i915_reg_t reg;

drivers/gpu/drm/i915/i915_perf.c

4306

static const i915_reg_t flex_eu_regs[] = {

drivers/gpu/drm/i915/i915_perf.c

905

i915_reg_t oaheadptr;

drivers/gpu/drm/i915/i915_perf.c

954

i915_reg_t oastatus_reg;

drivers/gpu/drm/i915/i915_perf_types.h

50

i915_reg_t oa_head_ptr;

drivers/gpu/drm/i915/i915_perf_types.h

51

i915_reg_t oa_tail_ptr;

drivers/gpu/drm/i915/i915_perf_types.h

52

i915_reg_t oa_buffer;

drivers/gpu/drm/i915/i915_perf_types.h

53

i915_reg_t oa_ctx_ctrl;

drivers/gpu/drm/i915/i915_perf_types.h

54

i915_reg_t oa_ctrl;

drivers/gpu/drm/i915/i915_perf_types.h

55

i915_reg_t oa_debug;

drivers/gpu/drm/i915/i915_perf_types.h

56

i915_reg_t oa_status;

drivers/gpu/drm/i915/i915_perf_types.h

73

i915_reg_t addr;

drivers/gpu/drm/i915/i915_reg_defs.h

16

#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })

drivers/gpu/drm/i915/i915_reg_defs.h

32

_Generic((r), i915_reg_t: (r).reg, i915_mcr_reg_t: (r).reg)

drivers/gpu/drm/i915/i915_reg_defs.h

38

i915_reg_t imr;

drivers/gpu/drm/i915/i915_reg_defs.h

39

i915_reg_t ier;

drivers/gpu/drm/i915/i915_reg_defs.h

40

i915_reg_t iir;

drivers/gpu/drm/i915/i915_reg_defs.h

47

i915_reg_t emr;

drivers/gpu/drm/i915/i915_reg_defs.h

48

i915_reg_t eir;

drivers/gpu/drm/i915/intel_uncore.c

1200

gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)

drivers/gpu/drm/i915/intel_uncore.c

1780

const i915_reg_t reg,

drivers/gpu/drm/i915/intel_uncore.c

1794

const i915_reg_t reg,

drivers/gpu/drm/i915/intel_uncore.c

1806

const i915_reg_t reg, const bool read)

drivers/gpu/drm/i915/intel_uncore.c

1822

const i915_reg_t reg, const bool read)

drivers/gpu/drm/i915/intel_uncore.c

1833

vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \

drivers/gpu/drm/i915/intel_uncore.c

1853

gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \

drivers/gpu/drm/i915/intel_uncore.c

1861

gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \

drivers/gpu/drm/i915/intel_uncore.c

1928

fwtable_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) \

drivers/gpu/drm/i915/intel_uncore.c

1940

fwtable_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) {

drivers/gpu/drm/i915/intel_uncore.c

1961

gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \

drivers/gpu/drm/i915/intel_uncore.c

1969

gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \

drivers/gpu/drm/i915/intel_uncore.c

2005

gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \

drivers/gpu/drm/i915/intel_uncore.c

2018

fwtable_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \

drivers/gpu/drm/i915/intel_uncore.c

2029

fwtable_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)

drivers/gpu/drm/i915/intel_uncore.c

2044

vgpu_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \

drivers/gpu/drm/i915/intel_uncore.c

2081

i915_reg_t reg_set,

drivers/gpu/drm/i915/intel_uncore.c

2082

i915_reg_t reg_ack)

drivers/gpu/drm/i915/intel_uncore.c

2756

i915_reg_t reg,

drivers/gpu/drm/i915/intel_uncore.c

2805

i915_reg_t reg,

drivers/gpu/drm/i915/intel_uncore.c

2905

i915_reg_t reg, unsigned int op)

drivers/gpu/drm/i915/intel_uncore.h

100

i915_reg_t r);

drivers/gpu/drm/i915/intel_uncore.h

103

i915_reg_t r, bool trace);

drivers/gpu/drm/i915/intel_uncore.h

105

i915_reg_t r, bool trace);

drivers/gpu/drm/i915/intel_uncore.h

107

i915_reg_t r, bool trace);

drivers/gpu/drm/i915/intel_uncore.h

109

i915_reg_t r, bool trace);

drivers/gpu/drm/i915/intel_uncore.h

112

i915_reg_t r, u8 val, bool trace);

drivers/gpu/drm/i915/intel_uncore.h

114

i915_reg_t r, u16 val, bool trace);

drivers/gpu/drm/i915/intel_uncore.h

116

i915_reg_t r, u32 val, bool trace);

drivers/gpu/drm/i915/intel_uncore.h

255

i915_reg_t reg, unsigned int op);

drivers/gpu/drm/i915/intel_uncore.h

281

i915_reg_t reg,

drivers/gpu/drm/i915/intel_uncore.h

289

i915_reg_t reg,

drivers/gpu/drm/i915/intel_uncore.h

299

i915_reg_t reg,

drivers/gpu/drm/i915/intel_uncore.h

307

i915_reg_t reg,

drivers/gpu/drm/i915/intel_uncore.h

322

i915_reg_t reg) \

drivers/gpu/drm/i915/intel_uncore.h

332

i915_reg_t reg, u##x__ val) \

drivers/gpu/drm/i915/intel_uncore.h

354

i915_reg_t reg) \

drivers/gpu/drm/i915/intel_uncore.h

361

i915_reg_t reg, u##x__ val) \

drivers/gpu/drm/i915/intel_uncore.h

431

i915_reg_t reg, u32 clear, u32 set)

drivers/gpu/drm/i915/intel_uncore.h

442

i915_reg_t reg, u32 clear, u32 set)

drivers/gpu/drm/i915/intel_uncore.h

454

i915_reg_t lower_reg, i915_reg_t upper_reg)

drivers/gpu/drm/i915/intel_uncore.h

483

i915_reg_t reg, u32 val,

drivers/gpu/drm/i915/intel_uncore.h

98

i915_reg_t r);

drivers/gpu/drm/i915/intel_uncore_trace.h

16

TP_PROTO(bool write, i915_reg_t reg, u64 val, int len, bool trace),

drivers/gpu/drm/i915/selftests/intel_uncore.c

211

i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset);

drivers/gpu/drm/i915/selftests/mock_uncore.c

29

nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { }

drivers/gpu/drm/i915/selftests/mock_uncore.c

36

nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return 0; }

drivers/gpu/drm/i915/vlv_suspend.c

285

i915_reg_t reg = VLV_GTLC_PW_STATUS;

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

102

i915_reg_t i915_reg)

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

110

i915_reg_t i915_reg, u32 val)

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

118

i915_reg_t i915_reg)

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

126

i915_reg_t i915_reg, u32 val)

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

27

i915_reg_t i915_reg)

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

35

i915_reg_t i915_reg)

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

43

i915_reg_t i915_reg, u8 val)

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

51

i915_reg_t i915_reg)

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

60

i915_reg_t i915_lower_reg, i915_reg_t i915_upper_reg)

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

78

i915_reg_t i915_reg)

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

86

i915_reg_t i915_reg, u32 val)

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

94

i915_reg_t i915_reg, u32 clear, u32 set)