drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

2222

*cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i));

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

166

*cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base));

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

206

*cs++ = i915_mmio_reg_offset(BCS_SWCTRL);

drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c

926

*cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE(engine->mmio_base));

drivers/gpu/drm/i915/gt/gen7_renderclear.c

400

batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7));

drivers/gpu/drm/i915/gt/gen7_renderclear.c

406

batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1));

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

210

*cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset;

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

218

*cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset;

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

503

*cs++ = i915_mmio_reg_offset(RING_PREDICATE_RESULT(0));

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

2755

*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i));

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

2757

*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i));

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

3556

i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base));

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

3558

i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base));

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

3565

i915_mmio_reg_offset(RING_ELSP(base));

drivers/gpu/drm/i915/gt/intel_gt_mcr.c

566

u32 offset = i915_mmio_reg_offset(reg);

drivers/gpu/drm/i915/gt/intel_lrc.c

1267

*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));

drivers/gpu/drm/i915/gt/intel_lrc.c

1275

*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));

drivers/gpu/drm/i915/gt/intel_lrc.c

1276

*cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0));

drivers/gpu/drm/i915/gt/intel_lrc.c

1281

*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));

drivers/gpu/drm/i915/gt/intel_lrc.c

1282

*cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0));

drivers/gpu/drm/i915/gt/intel_lrc.c

1295

*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));

drivers/gpu/drm/i915/gt/intel_lrc.c

1311

*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));

drivers/gpu/drm/i915/gt/intel_lrc.c

1319

*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));

drivers/gpu/drm/i915/gt/intel_lrc.c

1320

*cs++ = i915_mmio_reg_offset(RING_CMD_BUF_CCTL(0));

drivers/gpu/drm/i915/gt/intel_lrc.c

1336

*cs++ = i915_mmio_reg_offset(DRAW_WATERMARK);

drivers/gpu/drm/i915/gt/intel_lrc.c

1346

*cs++ = i915_mmio_reg_offset(GEN12_CS_DEBUG_MODE2);

drivers/gpu/drm/i915/gt/intel_lrc.c

1643

*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);

drivers/gpu/drm/i915/gt/intel_lrc.c

1649

*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);

drivers/gpu/drm/i915/gt/intel_lrc.c

1658

*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);

drivers/gpu/drm/i915/gt/intel_lrc.c

1725

*batch++ = i915_mmio_reg_offset(lri->reg);

drivers/gpu/drm/i915/gt/intel_mocs.c

653

return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));

drivers/gpu/drm/i915/gt/intel_ring_submission.c

706

*cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));

drivers/gpu/drm/i915/gt/intel_ring_submission.c

710

*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));

drivers/gpu/drm/i915/gt/intel_ring_submission.c

715

*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));

drivers/gpu/drm/i915/gt/intel_ring_submission.c

720

*cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));

drivers/gpu/drm/i915/gt/intel_ring_submission.c

768

*cs++ = i915_mmio_reg_offset(

drivers/gpu/drm/i915/gt/intel_ring_submission.c

822

*cs++ = i915_mmio_reg_offset(last_reg);

drivers/gpu/drm/i915/gt/intel_ring_submission.c

828

*cs++ = i915_mmio_reg_offset(last_reg);

drivers/gpu/drm/i915/gt/intel_ring_submission.c

863

*cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));

drivers/gpu/drm/i915/gt/intel_workarounds.c

1040

*cs++ = i915_mmio_reg_offset(wa->reg);

drivers/gpu/drm/i915/gt/intel_workarounds.c

151

unsigned int addr = i915_mmio_reg_offset(wa->reg);

drivers/gpu/drm/i915/gt/intel_workarounds.c

1750

name, from, i915_mmio_reg_offset(wa->reg),

drivers/gpu/drm/i915/gt/intel_workarounds.c

179

if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) {

drivers/gpu/drm/i915/gt/intel_workarounds.c

181

} else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) {

drivers/gpu/drm/i915/gt/intel_workarounds.c

189

i915_mmio_reg_offset(wa_->reg),

drivers/gpu/drm/i915/gt/intel_workarounds.c

208

GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) ==

drivers/gpu/drm/i915/gt/intel_workarounds.c

209

i915_mmio_reg_offset(wa_[1].reg));

drivers/gpu/drm/i915/gt/intel_workarounds.c

210

if (i915_mmio_reg_offset(wa_[1].reg) >

drivers/gpu/drm/i915/gt/intel_workarounds.c

211

i915_mmio_reg_offset(wa_[0].reg))

drivers/gpu/drm/i915/gt/intel_workarounds.c

2181

i915_mmio_reg_offset(wa->reg));

drivers/gpu/drm/i915/gt/intel_workarounds.c

2187

i915_mmio_reg_offset(RING_NOPID(base)));

drivers/gpu/drm/i915/gt/intel_workarounds.c

3005

if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg)))

drivers/gpu/drm/i915/gt/intel_workarounds.c

3014

u32 offset = i915_mmio_reg_offset(wa->reg);

drivers/gpu/drm/i915/gt/intel_workarounds.c

3094

if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))

drivers/gpu/drm/i915/gt/selftest_engine_cs.c

70

*cs++ = i915_mmio_reg_offset(timestamp_reg(rq->engine));

drivers/gpu/drm/i915/gt/selftest_engine_pm.c

60

*cs++ = i915_mmio_reg_offset(reg);

drivers/gpu/drm/i915/gt/selftest_execlists.c

1091

*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base));

drivers/gpu/drm/i915/gt/selftest_lrc.c

1597

*cs++ = i915_mmio_reg_offset(RING_START(0));

drivers/gpu/drm/i915/gt/selftest_lrc.c

305

i915_mmio_reg_offset(RING_START(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

310

i915_mmio_reg_offset(RING_CTL(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

315

i915_mmio_reg_offset(RING_HEAD(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

320

i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

325

i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

330

i915_mmio_reg_offset(RING_BBSTATE(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

335

i915_mmio_reg_offset(RING_BB_PER_CTX_PTR(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

340

i915_mmio_reg_offset(RING_INDIRECT_CTX(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

345

i915_mmio_reg_offset(RING_INDIRECT_CTX_OFFSET(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

350

i915_mmio_reg_offset(RING_CTX_TIMESTAMP(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

355

i915_mmio_reg_offset(GEN8_RING_CS_GPR(engine->mmio_base, 0)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

360

i915_mmio_reg_offset(RING_CMD_BUF_CCTL(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

365

i915_mmio_reg_offset(RING_BB_OFFSET(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

445

*cs++ = i915_mmio_reg_offset(RING_START(engine->mmio_base));

drivers/gpu/drm/i915/gt/selftest_lrc.c

452

*cs++ = i915_mmio_reg_offset(RING_TAIL(engine->mmio_base));

drivers/gpu/drm/i915/gt/selftest_lrc.c

769

*cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(rq->engine->mmio_base));

drivers/gpu/drm/i915/gt/selftest_lrc.c

966

if (offset == i915_mmio_reg_offset(RING_PREDICATE_RESULT(0)))

drivers/gpu/drm/i915/gt/selftest_mocs.c

152

u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));

drivers/gpu/drm/i915/gt/selftest_mocs.c

197

u32 reg = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));

drivers/gpu/drm/i915/gt/selftest_rc6.c

178

*cs++ = i915_mmio_reg_offset(GEN8_RC6_CTX_INFO);

drivers/gpu/drm/i915/gt/selftest_rps.c

103

*cs++ = i915_mmio_reg_offset(CS_GPR(i));

drivers/gpu/drm/i915/gt/selftest_rps.c

105

*cs++ = i915_mmio_reg_offset(CS_GPR(i)) + 4;

drivers/gpu/drm/i915/gt/selftest_rps.c

110

*cs++ = i915_mmio_reg_offset(CS_GPR(INC));

drivers/gpu/drm/i915/gt/selftest_rps.c

125

*cs++ = i915_mmio_reg_offset(CS_GPR(COUNT));

drivers/gpu/drm/i915/gt/selftest_rps.c

208

i915_mmio_reg_offset(BXT_RP_STATE_CAP),

drivers/gpu/drm/i915/gt/selftest_rps.c

213

i915_mmio_reg_offset(GEN9_RP_STATE_LIMITS),

drivers/gpu/drm/i915/gt/selftest_timeline.c

778

const u32 gpr = i915_mmio_reg_offset(GEN8_RING_CS_GPR(rq->engine->mmio_base, 0));

drivers/gpu/drm/i915/gt/selftest_workarounds.c

1011

i915_mmio_reg_offset(reg), a);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

1043

if (i915_mmio_reg_offset(wa->reg) &

drivers/gpu/drm/i915/gt/selftest_workarounds.c

157

*cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i));

drivers/gpu/drm/i915/gt/selftest_workarounds.c

184

return i915_mmio_reg_offset(reg);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

465

u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

520

u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

870

u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

906

u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

961

u32 offset = i915_mmio_reg_offset(reg);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

965

i915_mmio_reg_offset(tbl->reg) == offset)

drivers/gpu/drm/i915/gt/selftest_workarounds.c

989

i915_mmio_reg_offset(reg), a, b);

drivers/gpu/drm/i915/gt/uc/intel_guc.c

201

guc->send_regs.base = i915_mmio_reg_offset(MEDIA_SOFT_SCRATCH(0));

drivers/gpu/drm/i915/gt/uc/intel_guc.c

204

guc->send_regs.base = i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));

drivers/gpu/drm/i915/gt/uc/intel_guc.c

214

guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));

drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c

340

i915_mmio_reg_offset(reg), \

drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c

366

return guc_mmio_reg_add(gt, regset, i915_mmio_reg_offset(reg), flags);

drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c

421

ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL0)), false);

drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c

422

ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL1)), false);

drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c

423

ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL2)), false);

drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c

424

ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL3)), false);

drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c

425

ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL4)), false);

drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c

426

ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL5)), false);

drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c

427

ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL6)), false);

drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c

266

ext->reg = _MMIO(i915_mmio_reg_offset(extlist->reg));

drivers/gpu/drm/i915/gt/uc/intel_uc.c

392

i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET),

drivers/gpu/drm/i915/gt/uc/intel_uc.c

395

i915_mmio_reg_offset(GUC_WOPCM_SIZE),

drivers/gpu/drm/i915/gvt/cmd_parser.c

1061

cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR))

drivers/gpu/drm/i915/gvt/cmd_parser.c

931

if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) ||

drivers/gpu/drm/i915/gvt/cmd_parser.c

934

offset == i915_mmio_reg_offset(INSTPM)))

drivers/gpu/drm/i915/gvt/cmd_parser.c

968

if (offset == i915_mmio_reg_offset(DERRMR) ||

drivers/gpu/drm/i915/gvt/cmd_parser.c

969

offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {

drivers/gpu/drm/i915/gvt/edid.c

389

if (offset == i915_mmio_reg_offset(PCH_GMBUS2))

drivers/gpu/drm/i915/gvt/edid.c

391

else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))

drivers/gpu/drm/i915/gvt/edid.c

419

if (offset == i915_mmio_reg_offset(PCH_GMBUS0))

drivers/gpu/drm/i915/gvt/edid.c

421

else if (offset == i915_mmio_reg_offset(PCH_GMBUS1))

drivers/gpu/drm/i915/gvt/edid.c

423

else if (offset == i915_mmio_reg_offset(PCH_GMBUS2))

drivers/gpu/drm/i915/gvt/edid.c

425

else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))

drivers/gpu/drm/i915/gvt/gvt.h

460

(*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))

drivers/gpu/drm/i915/gvt/gvt.h

464

(*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))

drivers/gpu/drm/i915/gvt/handlers.c

1102

if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A)))

drivers/gpu/drm/i915/gvt/handlers.c

1104

else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_B)) ||

drivers/gpu/drm/i915/gvt/handlers.c

1105

reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B)))

drivers/gpu/drm/i915/gvt/handlers.c

1107

else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_C)) ||

drivers/gpu/drm/i915/gvt/handlers.c

1108

reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C)))

drivers/gpu/drm/i915/gvt/handlers.c

1110

else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_D)) ||

drivers/gpu/drm/i915/gvt/handlers.c

1111

reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D)))

drivers/gpu/drm/i915/gvt/handlers.c

1205

offset != i915_mmio_reg_offset(DP_AUX_CH_CTL(port_index))) {

drivers/gpu/drm/i915/gvt/handlers.c

1209

offset != i915_mmio_reg_offset(port_index ?

drivers/gpu/drm/i915/gvt/handlers.c

190

((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)

drivers/gpu/drm/i915/gvt/handlers.c

193

(num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))

drivers/gpu/drm/i915/gvt/handlers.c

1985

offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) ||

drivers/gpu/drm/i915/gvt/handlers.c

1986

offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(engine->mmio_base))) {

drivers/gpu/drm/i915/gvt/handlers.c

2165

ret = setup_mmio_info(gvt, i915_mmio_reg_offset(reg), \

drivers/gpu/drm/i915/gvt/handlers.c

2837

if (offset >= i915_mmio_reg_offset(block->offset) &&

drivers/gpu/drm/i915/gvt/handlers.c

2838

offset < i915_mmio_reg_offset(block->offset) + block->size)

drivers/gpu/drm/i915/gvt/handlers.c

2938

if (size < 1024 || offset == i915_mmio_reg_offset(GEN9_GFX_MOCS(0)))

drivers/gpu/drm/i915/gvt/handlers.c

2962

i915_mmio_reg_offset(gvt->mmio.mmio_block->offset));

drivers/gpu/drm/i915/gvt/handlers.c

3062

if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE)

drivers/gpu/drm/i915/gvt/handlers.c

3066

ret = handler(gvt, i915_mmio_reg_offset(block->offset) + j, data);

drivers/gpu/drm/i915/gvt/handlers.c

804

reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) {

drivers/gpu/drm/i915/gvt/handlers.c

822

if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))

drivers/gpu/drm/i915/gvt/handlers.c

901

u32 start = i915_mmio_reg_offset(_start);

drivers/gpu/drm/i915/gvt/handlers.c

902

u32 next = i915_mmio_reg_offset(_next);

drivers/gpu/drm/i915/gvt/handlers.c

903

u32 end = i915_mmio_reg_offset(_end);

drivers/gpu/drm/i915/gvt/interrupt.c

178

if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg)

drivers/gpu/drm/i915/gvt/interrupt.c

356

regbase_to_iir(i915_mmio_reg_offset(info->reg_base)))

drivers/gpu/drm/i915/gvt/interrupt.c

358

regbase_to_ier(i915_mmio_reg_offset(info->reg_base)));

drivers/gpu/drm/i915/gvt/interrupt.c

385

u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base);

drivers/gpu/drm/i915/gvt/interrupt.c

391

i915_mmio_reg_offset(up_irq_info->reg_base));

drivers/gpu/drm/i915/gvt/interrupt.c

393

i915_mmio_reg_offset(up_irq_info->reg_base));

drivers/gpu/drm/i915/gvt/interrupt.c

474

reg_base = i915_mmio_reg_offset(info->reg_base);

drivers/gpu/drm/i915/gvt/interrupt.c

532

if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &

drivers/gpu/drm/i915/gvt/interrupt.c

543

reg_base = i915_mmio_reg_offset(info->reg_base);

drivers/gpu/drm/i915/gvt/interrupt.c

549

if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ))

drivers/gpu/drm/i915/gvt/mmio_context.c

241

*cs++ = i915_mmio_reg_offset(mmio->reg);

drivers/gpu/drm/i915/gvt/mmio_context.c

271

*cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index));

drivers/gpu/drm/i915/gvt/mmio_context.c

298

*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index));

drivers/gpu/drm/i915/gvt/mmio_context.c

554

i915_mmio_reg_offset(mmio->reg),

drivers/gpu/drm/i915/gvt/scheduler.c

100

i915_mmio_reg_offset(EU_PERF_CNTL0),

drivers/gpu/drm/i915/gvt/scheduler.c

101

i915_mmio_reg_offset(EU_PERF_CNTL1),

drivers/gpu/drm/i915/gvt/scheduler.c

102

i915_mmio_reg_offset(EU_PERF_CNTL2),

drivers/gpu/drm/i915/gvt/scheduler.c

103

i915_mmio_reg_offset(EU_PERF_CNTL3),

drivers/gpu/drm/i915/gvt/scheduler.c

104

i915_mmio_reg_offset(EU_PERF_CNTL4),

drivers/gpu/drm/i915/gvt/scheduler.c

105

i915_mmio_reg_offset(EU_PERF_CNTL5),

drivers/gpu/drm/i915/gvt/scheduler.c

106

i915_mmio_reg_offset(EU_PERF_CNTL6),

drivers/gpu/drm/i915/gvt/scheduler.c

122

i915_mmio_reg_offset(GEN8_OACTXCONTROL);

drivers/gpu/drm/i915/gvt/scheduler.c

282

vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =

drivers/gpu/drm/i915/gvt/scheduler.c

286

vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =

drivers/gpu/drm/i915/gvt/scheduler.c

290

vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =

drivers/gpu/drm/i915/i915_cmd_parser.c

1132

int ret = addr - i915_mmio_reg_offset(table[mid].addr);

drivers/gpu/drm/i915/i915_cmd_parser.c

848

u32 curr = i915_mmio_reg_offset(reg_table[i].addr);

drivers/gpu/drm/i915/i915_debugfs.c

484

i915_mmio_reg_offset(wa->reg),

drivers/gpu/drm/i915/i915_ioctl.c

55

u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);

drivers/gpu/drm/i915/i915_irq.c

105

i915_mmio_reg_offset(reg), val);

drivers/gpu/drm/i915/i915_perf.c

1337

*cs++ = i915_mmio_reg_offset(reg);

drivers/gpu/drm/i915/i915_perf.c

1500

offset = oa_context_image_offset(ce, i915_mmio_reg_offset(reg));

drivers/gpu/drm/i915/i915_perf.c

1928

*cs++ = i915_mmio_reg_offset(reg) + 4 * d;

drivers/gpu/drm/i915/i915_perf.c

2025

*cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)) + 4;

drivers/gpu/drm/i915/i915_perf.c

2028

*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));

drivers/gpu/drm/i915/i915_perf.c

2029

*cs++ = i915_mmio_reg_offset(CS_GPR(START_TS));

drivers/gpu/drm/i915/i915_perf.c

2043

*cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)) + 4;

drivers/gpu/drm/i915/i915_perf.c

2046

*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));

drivers/gpu/drm/i915/i915_perf.c

2047

*cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS));

drivers/gpu/drm/i915/i915_perf.c

2066

*cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));

drivers/gpu/drm/i915/i915_perf.c

2067

*cs++ = i915_mmio_reg_offset(mi_predicate_result);

drivers/gpu/drm/i915/i915_perf.c

2091

*cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET));

drivers/gpu/drm/i915/i915_perf.c

2093

*cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET)) + 4;

drivers/gpu/drm/i915/i915_perf.c

2109

*cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));

drivers/gpu/drm/i915/i915_perf.c

2110

*cs++ = i915_mmio_reg_offset(mi_predicate_result);

drivers/gpu/drm/i915/i915_perf.c

2173

*cs++ = i915_mmio_reg_offset(reg_data[i].addr);

drivers/gpu/drm/i915/i915_perf.c

2422

u32 mmio = i915_mmio_reg_offset(reg);

drivers/gpu/drm/i915/i915_perf.c

2434

if (i915_mmio_reg_offset(oa_config->flex_regs[i].addr) == mmio)

drivers/gpu/drm/i915/i915_perf.c

2522

*cs++ = i915_mmio_reg_offset(flex->reg);

drivers/gpu/drm/i915/i915_perf.c

4318

if (i915_mmio_reg_offset(flex_eu_regs[i]) == addr)

drivers/gpu/drm/i915/i915_perf.c

4325

((addr) == i915_mmio_reg_offset(mmio))

drivers/gpu/drm/i915/i915_query.c

216

unsafe_put_user(i915_mmio_reg_offset(kernel_regs[r].addr),

drivers/gpu/drm/i915/i915_reg_defs.h

33

#define i915_mmio_reg_equal(a, b) (i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b))

drivers/gpu/drm/i915/intel_device_info.c

348

ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS),

drivers/gpu/drm/i915/intel_device_info.c

356

ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

51

ret = iter->handle_mmio_cb(iter, i915_mmio_reg_offset(reg), s); \

drivers/gpu/drm/i915/intel_uncore.c

1787

i915_mmio_reg_offset(reg)))

drivers/gpu/drm/i915/intel_uncore.c

1801

i915_mmio_reg_offset(reg));

drivers/gpu/drm/i915/intel_uncore.c

1884

u32 offset = i915_mmio_reg_offset(reg); \

drivers/gpu/drm/i915/intel_uncore.c

1941

return __fwtable_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg));

drivers/gpu/drm/i915/intel_uncore.c

1990

u32 offset = i915_mmio_reg_offset(reg); \

drivers/gpu/drm/i915/intel_uncore.c

2031

return __fwtable_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg));

drivers/gpu/drm/i915/intel_uncore.c

2098

d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set) + uncore->gsi_offset;

drivers/gpu/drm/i915/intel_uncore.c

2099

d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack) + uncore->gsi_offset;

drivers/gpu/drm/i915/intel_uncore.h

324

u32 offset = i915_mmio_reg_offset(reg); \

drivers/gpu/drm/i915/intel_uncore.h

334

u32 offset = i915_mmio_reg_offset(reg); \

drivers/gpu/drm/i915/intel_uncore.h

514

readl(base + i915_mmio_reg_offset(reg))

drivers/gpu/drm/i915/intel_uncore.h

516

writel(value, base + i915_mmio_reg_offset(reg))

drivers/gpu/drm/i915/intel_uncore_trace.h

31

__entry->reg = i915_mmio_reg_offset(reg);

drivers/gpu/drm/i915/selftests/i915_perf.c

307

gpr0 = i915_mmio_reg_offset(GEN8_RING_CS_GPR(stream->engine->mmio_base, 0));

drivers/gpu/drm/i915/selftests/i915_request.c

1962

*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP((ce->engine->mmio_base)));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

104

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

112

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

120

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

128

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

29

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

37

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

45

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

53

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

62

struct xe_reg lower_reg = XE_REG(i915_mmio_reg_offset(i915_lower_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

63

struct xe_reg upper_reg = XE_REG(i915_mmio_reg_offset(i915_upper_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

80

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

88

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

96

struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));