drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3384

struct dml2_dchub_per_pipe_register_set *hubp_regs = params->hubp_setup2_params.hubp_regs;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3389

hubp->funcs->hubp_setup2(hubp, hubp_regs, global_sync, timing);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3416

struct dml2_dchub_per_pipe_register_set *hubp_regs = params->hubp_setup_interdependent2_params.hubp_regs;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3419

hubp->funcs->hubp_setup_interdependent2(hubp, hubp_regs);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4524

struct dml2_dchub_per_pipe_register_set *hubp_regs,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4531

seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4570

struct dml2_dchub_per_pipe_register_set *hubp_regs)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4575

seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent2_params.hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

6009

det_segments += dpp_pipes[dpp_idx]->hubp_regs.det_size;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

222

memcpy(&pipe_ctx->hubp_regs, pln_prog->phantom_plane.pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

226

memcpy(&pipe_ctx->hubp_regs, pln_prog->pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set));

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1409

const struct dcn_mi_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1415

hubp1->hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

32

hubp1->hubp_regs->reg

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

855

const struct dcn_mi_registers *hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

934

const struct dcn_mi_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1713

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1719

hubp2->hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

38

hubp2->hubp_regs->reg

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

312

const struct dcn_hubp2_registers *hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

321

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

142

const struct dcn201_hubp_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

148

hubp201->hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

33

hubp201->hubp_regs->reg

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

119

const struct dcn201_hubp_registers *hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

128

const struct dcn201_hubp_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

39

hubp21->hubp_regs->reg

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

848

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

854

hubp21->hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

108

const struct dcn_hubp2_registers *hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

118

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

36

hubp2->hubp_regs->reg

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

666

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

672

hubp2->hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

253

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

120

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

126

hubp2->hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

33

hubp2->hubp_regs->reg

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

240

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

232

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

238

hubp2->hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

33

hubp2->hubp_regs->reg

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

66

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

229

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

235

hubp2->hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

31

hubp2->hubp_regs->reg

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h

55

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1085

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1091

hubp2->hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

34

hubp2->hubp_regs->reg

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

321

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

10

hubp2->hubp_regs->reg

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

628

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

634

hubp2->hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h

76

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1705

&pipe_ctx->hubp_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1725

&pipe_ctx->hubp_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1968

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1554

pipe_ctx->hubp_regs.dlg_regs.min_dst_y_next_start);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2275

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2425

pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2852

&pipe_ctx->hubp_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2996

struct dml2_display_dlg_regs old_dlg_regs = old_pipe->hubp_regs.dlg_regs;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2997

struct dml2_display_ttu_regs old_ttu_regs = old_pipe->hubp_regs.ttu_regs;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2998

struct dml2_display_rq_regs old_rq_regs = old_pipe->hubp_regs.rq_regs;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2999

struct dml2_display_dlg_regs *new_dlg_regs = &new_pipe->hubp_regs.dlg_regs;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3000

struct dml2_display_ttu_regs *new_ttu_regs = &new_pipe->hubp_regs.ttu_regs;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3001

struct dml2_display_rq_regs *new_rq_regs = &new_pipe->hubp_regs.rq_regs;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3721

hwss_add_hubp_setup2(seq_state, hubp, &pipe_ctx->hubp_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3736

hwss_add_hubp_setup_interdependent2(seq_state, hubp, &pipe_ctx->hubp_regs);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2241

struct dml2_dchub_per_pipe_register_set *hubp_regs,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2258

struct dml2_dchub_per_pipe_register_set *hubp_regs);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

671

struct dml2_dchub_per_pipe_register_set *hubp_regs;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

691

struct dml2_dchub_per_pipe_register_set *hubp_regs;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

502

struct dml2_dchub_per_pipe_register_set hubp_regs;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1025

&hubp_regs[inst], &hubp_shift, &hubp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

421

static const struct dcn_mi_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

422

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

423

hubp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

424

hubp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

425

hubp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1243

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

525

static const struct dcn_hubp2_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

526

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

527

hubp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

528

hubp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

529

hubp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

530

hubp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

531

hubp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1026

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

523

static const struct dcn201_hubp_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1023

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

306

static const struct dcn_hubp2_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

307

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

308

hubp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

309

hubp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

310

hubp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1366

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

627

static const struct dcn_hubp2_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

628

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

629

hubp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

630

hubp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

631

hubp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

632

hubp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

633

hubp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1204

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

559

static const struct dcn_hubp2_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

560

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

561

hubp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

562

hubp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

563

hubp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

607

static const struct dcn_hubp2_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

608

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

609

hubp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

610

hubp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

611

hubp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

612

hubp_regs(4)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

630

if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

591

static const struct dcn_hubp2_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

592

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

593

hubp_regs(1)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

611

if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1663

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

674

static const struct dcn_hubp2_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

675

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

676

hubp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

677

hubp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

678

hubp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1722

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

681

static const struct dcn_hubp2_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

682

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

683

hubp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

684

hubp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

685

hubp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1665

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

673

static const struct dcn_hubp2_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

674

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

675

hubp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

676

hubp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

677

hubp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1655

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

668

static const struct dcn_hubp2_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

669

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

670

hubp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

671

hubp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

672

hubp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

530

static struct dcn_hubp2_registers hubp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

973

#define REG_STRUCT hubp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

980

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

521

static struct dcn_hubp2_registers hubp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

961

#define REG_STRUCT hubp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

968

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1732

#define REG_STRUCT hubp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1739

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

533

static struct dcn_hubp2_registers hubp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1712

#define REG_STRUCT hubp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1719

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

513

static struct dcn_hubp2_registers hubp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1719

#define REG_STRUCT hubp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1726

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

520

static struct dcn_hubp2_registers hubp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

501

static struct dcn_hubp2_registers hubp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

963

#define REG_STRUCT hubp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

970

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

460

static struct dcn_hubp2_registers hubp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

986

#define REG_STRUCT hubp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

993

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1021

#define REG_STRUCT hubp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1028

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

484

static struct dcn_hubp2_registers hubp_regs[4];