drivers/gpu/drm/amd/display/dc/core/dc.c

1324

dc->hwss.update_visual_confirm_color(dc, pipe, pipe->plane_res.hubp->mpcc_id);

drivers/gpu/drm/amd/display/dc/core/dc.c

2592

mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

3886

(!tmp_pipe->plane_res.mi && !tmp_pipe->plane_res.hubp) ||

drivers/gpu/drm/amd/display/dc/core/dc.c

4942

pipe_ctx->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/core/dc.c

5033

cur_pipe->plane_res.hubp->funcs->validate_dml_output(

drivers/gpu/drm/amd/display/dc/core/dc.c

5034

cur_pipe->plane_res.hubp, dc->ctx,

drivers/gpu/drm/amd/display/dc/core/dc.c

6195

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc.c

6203

if (hubp && hubp->funcs->hubp_is_flip_pending &&

drivers/gpu/drm/amd/display/dc/core/dc.c

6204

hubp->funcs->hubp_is_flip_pending(hubp)) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6468

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/core/dc.c

6483

hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc.c

6484

hubp->funcs->set_blank_regs(hubp, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

6498

hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc.c

6499

hubp->funcs->set_blank_regs(hubp, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

7313

state->hubp[i].valid_stream = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

7317

state->hubp[i].valid_stream = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

7321

state->hubp[i].vtg_sel = pipe_ctx->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/core/dc.c

7323

state->hubp[i].hubp_clock_enable = (pipe_ctx->plane_res.hubp != NULL) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7325

state->hubp[i].valid_plane_state = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

7327

state->hubp[i].valid_plane_state = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

7328

state->hubp[i].surface_pixel_format = pipe_ctx->plane_state->format;

drivers/gpu/drm/amd/display/dc/core/dc.c

7329

state->hubp[i].rotation_angle = pipe_ctx->plane_state->rotation;

drivers/gpu/drm/amd/display/dc/core/dc.c

7330

state->hubp[i].h_mirror_en = pipe_ctx->plane_state->horizontal_mirror ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7334

state->hubp[i].surface_size_width = pipe_ctx->plane_state->plane_size.surface_size.width;

drivers/gpu/drm/amd/display/dc/core/dc.c

7335

state->hubp[i].surface_size_height = pipe_ctx->plane_state->plane_size.surface_size.height;

drivers/gpu/drm/amd/display/dc/core/dc.c

7340

state->hubp[i].pri_viewport_width = pipe_ctx->plane_state->src_rect.width;

drivers/gpu/drm/amd/display/dc/core/dc.c

7341

state->hubp[i].pri_viewport_height = pipe_ctx->plane_state->src_rect.height;

drivers/gpu/drm/amd/display/dc/core/dc.c

7342

state->hubp[i].pri_viewport_x_start = pipe_ctx->plane_state->src_rect.x;

drivers/gpu/drm/amd/display/dc/core/dc.c

7343

state->hubp[i].pri_viewport_y_start = pipe_ctx->plane_state->src_rect.y;

drivers/gpu/drm/amd/display/dc/core/dc.c

7347

state->hubp[i].surface_dcc_en = (pipe_ctx->plane_state->dcc.enable) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7348

state->hubp[i].surface_dcc_ind_64b_blk = pipe_ctx->plane_state->dcc.independent_64b_blks;

drivers/gpu/drm/amd/display/dc/core/dc.c

7349

state->hubp[i].surface_dcc_ind_128b_blk = pipe_ctx->plane_state->dcc.dcc_ind_blk;

drivers/gpu/drm/amd/display/dc/core/dc.c

7352

state->hubp[i].surface_pitch = pipe_ctx->plane_state->plane_size.surface_pitch;

drivers/gpu/drm/amd/display/dc/core/dc.c

7353

state->hubp[i].meta_pitch = pipe_ctx->plane_state->dcc.meta_pitch;

drivers/gpu/drm/amd/display/dc/core/dc.c

7354

state->hubp[i].chroma_pitch = pipe_ctx->plane_state->plane_size.chroma_pitch;

drivers/gpu/drm/amd/display/dc/core/dc.c

7355

state->hubp[i].meta_pitch_c = pipe_ctx->plane_state->dcc.meta_pitch_c;

drivers/gpu/drm/amd/display/dc/core/dc.c

7358

state->hubp[i].primary_surface_address_low = pipe_ctx->plane_state->address.grph.addr.low_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

7359

state->hubp[i].primary_surface_address_high = pipe_ctx->plane_state->address.grph.addr.high_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

7360

state->hubp[i].primary_meta_surface_address_low = pipe_ctx->plane_state->address.grph.meta_addr.low_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

7361

state->hubp[i].primary_meta_surface_address_high = pipe_ctx->plane_state->address.grph.meta_addr.high_part;

drivers/gpu/drm/amd/display/dc/core/dc.c

7364

state->hubp[i].primary_surface_tmz = pipe_ctx->plane_state->address.tmz_surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

7365

state->hubp[i].primary_meta_surface_tmz = pipe_ctx->plane_state->address.tmz_surface;

drivers/gpu/drm/amd/display/dc/core/dc.c

7368

state->hubp[i].min_dc_gfx_version9 = false;

drivers/gpu/drm/amd/display/dc/core/dc.c

7370

state->hubp[i].min_dc_gfx_version9 = true;

drivers/gpu/drm/amd/display/dc/core/dc.c

7371

state->hubp[i].sw_mode = pipe_ctx->plane_state->tiling_info.gfx9.swizzle;

drivers/gpu/drm/amd/display/dc/core/dc.c

7372

state->hubp[i].num_pipes = pipe_ctx->plane_state->tiling_info.gfx9.num_pipes;

drivers/gpu/drm/amd/display/dc/core/dc.c

7373

state->hubp[i].num_banks = pipe_ctx->plane_state->tiling_info.gfx9.num_banks;

drivers/gpu/drm/amd/display/dc/core/dc.c

7374

state->hubp[i].pipe_interleave = pipe_ctx->plane_state->tiling_info.gfx9.pipe_interleave;

drivers/gpu/drm/amd/display/dc/core/dc.c

7375

state->hubp[i].num_shader_engines = pipe_ctx->plane_state->tiling_info.gfx9.num_shader_engines;

drivers/gpu/drm/amd/display/dc/core/dc.c

7376

state->hubp[i].num_rb_per_se = pipe_ctx->plane_state->tiling_info.gfx9.num_rb_per_se;

drivers/gpu/drm/amd/display/dc/core/dc.c

7377

state->hubp[i].num_pkrs = pipe_ctx->plane_state->tiling_info.gfx9.num_pkrs;

drivers/gpu/drm/amd/display/dc/core/dc.c

7383

state->hubp[i].rq_chunk_size = pipe_ctx->rq_regs.rq_regs_l.chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7384

state->hubp[i].rq_min_chunk_size = pipe_ctx->rq_regs.rq_regs_l.min_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7385

state->hubp[i].rq_meta_chunk_size = pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7386

state->hubp[i].rq_min_meta_chunk_size = pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7387

state->hubp[i].rq_dpte_group_size = pipe_ctx->rq_regs.rq_regs_l.dpte_group_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7388

state->hubp[i].rq_mpte_group_size = pipe_ctx->rq_regs.rq_regs_l.mpte_group_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7389

state->hubp[i].rq_swath_height_l = pipe_ctx->rq_regs.rq_regs_l.swath_height;

drivers/gpu/drm/amd/display/dc/core/dc.c

7390

state->hubp[i].rq_pte_row_height_l = pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear;

drivers/gpu/drm/amd/display/dc/core/dc.c

7395

state->hubp[i].rq_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7396

state->hubp[i].rq_min_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.min_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7397

state->hubp[i].rq_meta_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.meta_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7398

state->hubp[i].rq_min_meta_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.min_meta_chunk_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7399

state->hubp[i].rq_dpte_group_size_c = pipe_ctx->rq_regs.rq_regs_c.dpte_group_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7400

state->hubp[i].rq_mpte_group_size_c = pipe_ctx->rq_regs.rq_regs_c.mpte_group_size;

drivers/gpu/drm/amd/display/dc/core/dc.c

7401

state->hubp[i].rq_swath_height_c = pipe_ctx->rq_regs.rq_regs_c.swath_height;

drivers/gpu/drm/amd/display/dc/core/dc.c

7402

state->hubp[i].rq_pte_row_height_c = pipe_ctx->rq_regs.rq_regs_c.pte_row_height_linear;

drivers/gpu/drm/amd/display/dc/core/dc.c

7406

state->hubp[i].drq_expansion_mode = pipe_ctx->rq_regs.drq_expansion_mode;

drivers/gpu/drm/amd/display/dc/core/dc.c

7407

state->hubp[i].prq_expansion_mode = pipe_ctx->rq_regs.prq_expansion_mode;

drivers/gpu/drm/amd/display/dc/core/dc.c

7408

state->hubp[i].mrq_expansion_mode = pipe_ctx->rq_regs.mrq_expansion_mode;

drivers/gpu/drm/amd/display/dc/core/dc.c

7409

state->hubp[i].crq_expansion_mode = pipe_ctx->rq_regs.crq_expansion_mode;

drivers/gpu/drm/amd/display/dc/core/dc.c

7412

state->hubp[i].dst_y_per_vm_vblank = pipe_ctx->dlg_regs.dst_y_per_vm_vblank;

drivers/gpu/drm/amd/display/dc/core/dc.c

7413

state->hubp[i].dst_y_per_row_vblank = pipe_ctx->dlg_regs.dst_y_per_row_vblank;

drivers/gpu/drm/amd/display/dc/core/dc.c

7414

state->hubp[i].dst_y_per_vm_flip = pipe_ctx->dlg_regs.dst_y_per_vm_flip;

drivers/gpu/drm/amd/display/dc/core/dc.c

7415

state->hubp[i].dst_y_per_row_flip = pipe_ctx->dlg_regs.dst_y_per_row_flip;

drivers/gpu/drm/amd/display/dc/core/dc.c

7418

state->hubp[i].dst_y_prefetch = pipe_ctx->dlg_regs.dst_y_prefetch;

drivers/gpu/drm/amd/display/dc/core/dc.c

7419

state->hubp[i].vratio_prefetch = pipe_ctx->dlg_regs.vratio_prefetch;

drivers/gpu/drm/amd/display/dc/core/dc.c

7420

state->hubp[i].vratio_prefetch_c = pipe_ctx->dlg_regs.vratio_prefetch_c;

drivers/gpu/drm/amd/display/dc/core/dc.c

7423

state->hubp[i].qos_level_low_wm = pipe_ctx->ttu_regs.qos_level_low_wm;

drivers/gpu/drm/amd/display/dc/core/dc.c

7424

state->hubp[i].qos_level_high_wm = pipe_ctx->ttu_regs.qos_level_high_wm;

drivers/gpu/drm/amd/display/dc/core/dc.c

7425

state->hubp[i].qos_level_flip = pipe_ctx->ttu_regs.qos_level_flip;

drivers/gpu/drm/amd/display/dc/core/dc.c

7426

state->hubp[i].min_ttu_vblank = pipe_ctx->ttu_regs.min_ttu_vblank;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1032

block_sequence[*num_steps].params.set_flip_control_gsl_params.hubp = current_mpc_pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1117

block_sequence[*num_steps].params.update_visual_confirm_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1123

block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1219

params->set_flip_control_gsl_params.hubp->funcs->hubp_set_flip_control_surface_gsl(

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1220

params->set_flip_control_gsl_params.hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1312

params->hubp_wait_pipe_read_start_params.hubp->funcs->hubp_wait_pipe_read_start(

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1313

params->hubp_wait_pipe_read_start_params.hubp);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1699

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1703

seq_state->steps[*seq_state->num_steps].params.set_flip_control_gsl_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1939

struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1942

seq_state->steps[*seq_state->num_steps].params.hubp_wait_pipe_read_start_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2135

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2139

seq_state->steps[*seq_state->num_steps].params.program_mcache_id_and_split_coordinate.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2274

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2279

seq_state->steps[*seq_state->num_steps].params.hubp_wait_flip_pending_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2305

struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2308

seq_state->steps[*seq_state->num_steps].params.hubp_enable_3dlut_fl_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2403

struct hubp *hubp = params->program_surface_config_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2412

hubp->funcs->hubp_program_surface_config(

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2413

hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2422

hubp->power_gated = false;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2427

struct hubp *hubp = params->program_mcache_id_and_split_coordinate.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2430

hubp->funcs->hubp_program_mcache_id_and_split_coordinate(hubp, mcache_regs);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2550

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2568

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2569

if (!hubp)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2572

mpcc_inst = hubp->inst;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2785

struct hubp *hubp = params->hubp_enable_3dlut_fl_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2787

if (hubp->funcs->hubp_enable_3dlut_fl)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2788

hubp->funcs->hubp_enable_3dlut_fl(hubp, true);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2964

struct hubp *hubp = params->hubp_disconnect_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2966

if (hubp->funcs->hubp_disconnect)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2967

hubp->funcs->hubp_disconnect(hubp);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3013

struct hubp *hubp = params->hubp_wait_flip_pending_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3019

&& hubp->funcs->hubp_is_flip_pending(hubp); j++)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3155

struct hubp *hubp = params->hubp_update_mall_sel_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3159

if (hubp && hubp->funcs->hubp_update_mall_sel)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3160

hubp->funcs->hubp_update_mall_sel(hubp, mall_sel, cache_cursor);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3165

struct hubp *hubp = params->hubp_prepare_subvp_buffering_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3168

if (hubp && hubp->funcs->hubp_prepare_subvp_buffering)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3169

hubp->funcs->hubp_prepare_subvp_buffering(hubp, enable);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3174

struct hubp *hubp = params->hubp_set_blank_en_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3177

if (hubp && hubp->funcs->set_hubp_blank_en)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3178

hubp->funcs->set_hubp_blank_en(hubp, enable);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3183

struct hubp *hubp = params->hubp_disable_control_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3186

if (hubp && hubp->funcs->hubp_disable_control)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3187

hubp->funcs->hubp_disable_control(hubp, disable);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3201

struct hubp *hubp = params->hubp_clk_cntl_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3204

if (hubp && hubp->funcs->hubp_clk_cntl) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3205

hubp->funcs->hubp_clk_cntl(hubp, enable);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3206

hubp->power_gated = !enable;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3212

struct hubp *hubp = params->hubp_init_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3214

if (hubp && hubp->funcs->hubp_init)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3215

hubp->funcs->hubp_init(hubp);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3220

struct hubp *hubp = params->hubp_set_vm_system_aperture_settings_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3227

if (hubp && hubp->funcs->hubp_set_vm_system_aperture_settings)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3228

hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3233

struct hubp *hubp = params->hubp_set_flip_int_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3235

if (hubp && hubp->funcs->hubp_set_flip_int)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3236

hubp->funcs->hubp_set_flip_int(hubp);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3328

struct hubp *hubp = params->hubp_reset_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3330

if (hubp && hubp->funcs->hubp_reset)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3331

hubp->funcs->hubp_reset(hubp);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3374

struct hubp *hubp = params->hubp_vtg_sel_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3377

if (hubp && hubp->funcs->hubp_vtg_sel)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3378

hubp->funcs->hubp_vtg_sel(hubp, otg_inst);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3383

struct hubp *hubp = params->hubp_setup2_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3388

if (hubp && hubp->funcs->hubp_setup2)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3389

hubp->funcs->hubp_setup2(hubp, hubp_regs, global_sync, timing);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3394

struct hubp *hubp = params->hubp_setup_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3400

if (hubp && hubp->funcs->hubp_setup)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3401

hubp->funcs->hubp_setup(hubp, dlg_regs, ttu_regs, rq_regs, pipe_dest);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3406

struct hubp *hubp = params->hubp_set_unbounded_requesting_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3409

if (hubp && hubp->funcs->set_unbounded_requesting)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3410

hubp->funcs->set_unbounded_requesting(hubp, unbounded_req);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3415

struct hubp *hubp = params->hubp_setup_interdependent2_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3418

if (hubp && hubp->funcs->hubp_setup_interdependent2)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3419

hubp->funcs->hubp_setup_interdependent2(hubp, hubp_regs);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3424

struct hubp *hubp = params->hubp_setup_interdependent_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3428

if (hubp && hubp->funcs->hubp_setup_interdependent)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3429

hubp->funcs->hubp_setup_interdependent(hubp, dlg_regs, ttu_regs);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3497

struct hubp *hubp = params->hubp_mem_program_viewport_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3501

if (hubp && hubp->funcs->mem_program_viewport)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3502

hubp->funcs->mem_program_viewport(hubp, viewport, viewport_c);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3570

struct hubp *hubp = params->hubp_set_cursor_attributes_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3573

if (hubp && hubp->funcs->set_cursor_attributes)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3574

hubp->funcs->set_cursor_attributes(hubp, attributes);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3626

struct hubp *hubp = params->hubp_set_blank_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3629

if (hubp && hubp->funcs->set_blank)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3630

hubp->funcs->set_blank(hubp, blank);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3635

struct hubp *hubp = params->phantom_hubp_post_enable_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3637

if (hubp && hubp->funcs->phantom_hubp_post_enable)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3638

hubp->funcs->phantom_hubp_post_enable(hubp);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3751

struct hubp *hubp = params->set_dmdata_attributes_params.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3753

if (!hubp || !hubp->funcs->dmdata_set_attributes)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3756

hubp->funcs->dmdata_set_attributes(hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3901

struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3905

seq_state->steps[*seq_state->num_steps].params.hubp_disconnect_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4051

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4056

seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4235

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4241

seq_state->steps[*seq_state->num_steps].params.hubp_update_mall_sel_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4249

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4254

seq_state->steps[*seq_state->num_steps].params.hubp_prepare_subvp_buffering_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4261

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4266

seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_en_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4273

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4278

seq_state->steps[*seq_state->num_steps].params.hubp_disable_control_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4299

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4304

seq_state->steps[*seq_state->num_steps].params.hubp_clk_cntl_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4429

struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4433

seq_state->steps[*seq_state->num_steps].params.hubp_init_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4439

struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4443

seq_state->steps[*seq_state->num_steps].params.hubp_reset_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4471

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4478

seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4487

struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4491

seq_state->steps[*seq_state->num_steps].params.hubp_set_flip_int_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4511

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4516

seq_state->steps[*seq_state->num_steps].params.hubp_vtg_sel_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4523

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4530

seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4539

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4547

seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4557

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4562

seq_state->steps[*seq_state->num_steps].params.hubp_set_unbounded_requesting_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4569

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4574

seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent2_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4581

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4587

seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4595

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4606

seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4655

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4661

seq_state->steps[*seq_state->num_steps].params.hubp_mem_program_viewport_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4693

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4698

seq_state->steps[*seq_state->num_steps].params.hubp_set_cursor_attributes_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4759

struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4763

seq_state->steps[*seq_state->num_steps].params.phantom_hubp_post_enable_params.hubp = hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5053

seq_state->steps[*seq_state->num_steps].params.set_dmdata_attributes_params.hubp =

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

5054

pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

829

block_sequence[*num_steps].params.set_dmdata_attributes_params.hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

879

block_sequence[*num_steps].params.hubp_set_cursor_attributes_params.hubp =

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

880

current_pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

952

(!current_pipe->plane_res.mi && !current_pipe->plane_res.hubp) ||

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2650

split_pipe->plane_res.hubp = pool->hubps[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3995

pipe_ctx->plane_res.hubp = pool->hubps[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4140

pipe_ctx->plane_res.hubp = pool->hubps[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5867

sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

468

(!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) ||

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

564

pipe_ctx->plane_res.hubp->mpcc_id);

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

882

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

902

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

903

if (hubp == NULL)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

912

if (hubp->funcs->dmdata_set_attributes != NULL &&

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

914

hubp->funcs->dmdata_set_attributes(hubp, attr);

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

77

if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

78

pipe_mask |= (uint8_t)(1 << pipe_ctx->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/dc.h

3134

} hubp[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1046

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1053

if (!dc_get_edp_link_panel_inst(hubp->ctx->dc,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1062

payload->cursor_rect.x = hubp->cur_rect.x;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1063

payload->cursor_rect.y = hubp->cur_rect.y;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1065

payload->cursor_rect.width = hubp->cur_rect.w;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1066

payload->cursor_rect.height = hubp->cur_rect.h;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1068

payload->enable = (uint8_t)hubp->pos.cur_ctl.bits.cur_enable;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1076

const struct hubp *hubp, const struct dpp *dpp)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1079

pl->position_cfg.pHubp.cur_ctl.raw = hubp->pos.cur_ctl.raw;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1080

pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1081

pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1082

pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1091

const struct hubp *hubp, const struct dpp *dpp)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1095

pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1096

pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1097

pl_A->aHubp.cur_ctl.raw = hubp->att.cur_ctl.raw;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1098

pl_A->aHubp.size.raw = hubp->att.size.raw;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1099

pl_A->aHubp.settings.raw = hubp->att.settings.raw;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1147

pCtx->plane_res.hubp, pCtx->plane_res.dpp);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1157

pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

436

fams_pipe_data->pipe_index[pipe_idx++] = (uint8_t)head_pipe->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

441

fams_pipe_data->pipe_index[pipe_idx++] = (uint8_t)split_pipe->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

861

pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = (uint8_t)phantom_pipe->bottom_pipe->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

863

pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = (uint8_t)phantom_pipe->next_odm_pipe->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

135

struct hubp *hubp = pool->hubps[i];

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

136

struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

138

hubp->funcs->hubp_read_state(hubp);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

145

hubp->inst,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

164

hubp->inst,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

514

struct hubp *hubp = pool->hubps[i];

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

515

struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

517

hubp->funcs->hubp_read_state(hubp);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

520

hubp->funcs->hubp_clear_underflow(hubp);

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

538

secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1858

sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

280

if (existing_state->res_ctx.pipe_ctx[i].plane_res.hubp &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

281

existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

321

if ((existing_state->res_ctx.pipe_ctx[i].plane_res.hubp &&

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

322

existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i) ||

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

103

void hubp1_clear_underflow(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

105

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1095

void hubp1_read_state(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1097

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

110

static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1101

hubp1_read_state_common(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

112

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1169

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1172

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1177

hubp->curs_attr = *attr;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

118

void hubp1_vready_workaround(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1201

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1205

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1212

int cursor_height = (int)hubp->curs_attr.height;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1213

int cursor_width = (int)hubp->curs_attr.width;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1217

hubp->curs_pos = *pos;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

122

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1226

if (hubp->curs_attr.address.quad_part == 0)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1275

hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1301

void hubp1_clk_cntl(struct hubp *hubp, bool enable)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1303

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1309

void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1311

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1316

bool hubp1_in_blank(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1319

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1325

void hubp1_soft_reset(struct hubp *hubp, bool reset)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1327

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1337

void hubp1_set_flip_int(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1339

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1352

static void hubp1_wait_pipe_read_start(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1354

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1361

void hubp1_init(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1363

hubp_reset(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

142

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

147

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

165

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

170

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

205

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

209

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

238

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

241

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

351

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

355

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

41

void hubp1_set_blank(struct hubp *hubp, bool blank)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

43

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

517

hubp->request_address = *address;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

522

void hubp1_clear_tiling(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

524

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

536

void hubp1_dcc_control(struct hubp *hubp, bool enable,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

541

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

550

void hubp_reset(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

552

memset(&hubp->pos, 0, sizeof(hubp->pos));

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

553

memset(&hubp->att, 0, sizeof(hubp->att));

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

554

hubp->cursor_offload = false;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

558

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

568

hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

569

hubp1_program_tiling(hubp, tiling_info, format);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

570

hubp1_program_size(hubp, format, plane_size, dcc);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

571

hubp1_program_rotation(hubp, rotation, horizontal_mirror);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

572

hubp1_program_pixel_format(hubp, format);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

576

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

579

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

610

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

614

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

65

hubp->mpcc_id = 0xf;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

66

hubp->opp_id = OPP_ID_INVALID;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

698

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

70

static void hubp1_disconnect(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

707

hubp1_program_requestor(hubp, rq_regs);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

708

hubp1_program_deadline(hubp, dlg_attr, ttu_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

709

hubp1_vready_workaround(hubp, pipe_dest);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

713

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

717

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

72

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

754

bool hubp1_is_flip_pending(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

757

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

760

if (hubp && hubp->power_gated)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

775

if (hubp &&

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

776

earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

785

static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

788

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

81

static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

814

static void hubp1_set_vm_context0_settings(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

817

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

83

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

850

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

854

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

891

void hubp1_read_state_common(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

893

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

90

static unsigned int hubp1_get_underflow_status(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

93

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

30

#define TO_DCN10_HUBP(hubp)\

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

31

container_of(hubp, struct dcn10_hubp, base)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

853

struct hubp base;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

861

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

871

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

876

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

880

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

884

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

890

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

895

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

899

void hubp1_dcc_control(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

903

void hubp_reset(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

906

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

910

bool hubp1_is_flip_pending(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

913

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

917

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

921

void hubp1_set_blank(struct hubp *hubp, bool blank);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

923

void min_set_viewport(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

927

void hubp1_clk_cntl(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

928

void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

938

void hubp1_read_state(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

939

void hubp1_clear_underflow(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

943

void hubp1_vready_workaround(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

946

void hubp1_init(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

947

void hubp1_read_state_common(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

948

bool hubp1_in_blank(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

949

void hubp1_soft_reset(struct hubp *hubp, bool reset);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

951

void hubp1_set_flip_int(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

953

void hubp1_clear_tiling(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1003

int cursor_height = (int)hubp->curs_attr.height;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1004

int cursor_width = (int)hubp->curs_attr.width;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1008

hubp->curs_pos = *pos;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1017

if (hubp->curs_attr.address.quad_part == 0)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1065

if (hubp->pos.cur_ctl.bits.cur_enable != cur_en) {

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1066

bool cursor_not_programmed = hubp->att.SURFACE_ADDR == 0 && hubp->att.SURFACE_ADDR_HIGH == 0;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1069

hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1071

if (!hubp->cursor_offload)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1075

if (!hubp->cursor_offload) {

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1090

hubp->pos.cur_ctl.bits.cur_enable = cur_en;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1091

hubp->pos.position.bits.x_pos = pos->x;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1092

hubp->pos.position.bits.y_pos = pos->y;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1093

hubp->pos.hot_spot.bits.x_hot = pos->x_hotspot;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1094

hubp->pos.hot_spot.bits.y_hot = pos->y_hotspot;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1095

hubp->pos.dst_offset.bits.dst_x_offset = dst_x_offset;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1108

hubp->cur_rect.x = 0;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1109

hubp->cur_rect.y = 0;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1110

hubp->cur_rect.w = param->stream->timing.h_addressable;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1111

hubp->cur_rect.h = param->stream->timing.v_addressable;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1113

hubp->cur_rect.x = src_x_offset + param->viewport.x;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1114

hubp->cur_rect.y = src_y_offset + param->viewport.y;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1118

void hubp2_clk_cntl(struct hubp *hubp, bool enable)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1120

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1126

void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1128

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1133

void hubp2_clear_underflow(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1135

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1140

void hubp2_read_state_common(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1142

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1332

void hubp2_read_state(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1334

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1338

hubp2_read_state_common(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1368

static void hubp2_validate_dml_output(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1374

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

172

void hubp2_vready_at_or_After_vsync(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

176

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

197

static void hubp2_program_requestor(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

200

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

230

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

240

hubp2_vready_at_or_After_vsync(hubp, pipe_dest);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

241

hubp2_program_requestor(hubp, rq_regs);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

242

hubp2_program_deadline(hubp, dlg_attr, ttu_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

247

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

251

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

330

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

335

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

378

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

382

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

410

void hubp2_clear_tiling(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

412

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

424

void hubp2_dcc_control(struct hubp *hubp, bool enable,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

429

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

439

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

442

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

47

void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

50

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

552

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

562

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

564

hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

566

hubp2_program_size(hubp, format, plane_size, dcc);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

567

hubp2_program_rotation(hubp, rotation, horizontal_mirror);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

568

hubp2_program_pixel_format(hubp, format);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

608

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

611

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

616

hubp->curs_attr = *attr;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

618

if (!hubp->cursor_offload) {

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

641

hubp->att.SURFACE_ADDR_HIGH = attr->address.high_part;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

642

hubp->att.SURFACE_ADDR = attr->address.low_part;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

643

hubp->att.size.bits.width = attr->width;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

644

hubp->att.size.bits.height = attr->height;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

645

hubp->att.cur_ctl.bits.mode = attr->color_format;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

647

hubp->cur_rect.w = attr->width;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

648

hubp->cur_rect.h = attr->height;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

650

hubp->att.cur_ctl.bits.pitch = hw_pitch;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

651

hubp->att.cur_ctl.bits.line_per_chunk = lpc;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

652

hubp->att.cur_ctl.bits.cur_2x_magnify = attr->attribute_flags.bits.ENABLE_MAGNIFICATION;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

653

hubp->att.settings.bits.dst_y_offset = 0;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

654

hubp->att.settings.bits.chunk_hdl_adjust = 3;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

658

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

661

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

698

hubp2_dmdata_load(hubp, attr->dmdata_size, attr->dmdata_sw_data);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

709

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

714

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

721

bool hubp2_dmdata_status_done(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

724

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

731

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

735

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

82

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

86

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

888

hubp->request_address = *address;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

894

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

897

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

910

struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

912

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

920

void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

922

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

927

bool hubp2_is_flip_pending(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

930

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

933

if (hubp && hubp->power_gated)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

948

if (hubp &&

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

949

earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

955

void hubp2_set_blank(struct hubp *hubp, bool blank)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

957

hubp2_set_blank_regs(hubp, blank);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

960

hubp->mpcc_id = 0xf;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

961

hubp->opp_id = OPP_ID_INVALID;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

965

void hubp2_set_blank_regs(struct hubp *hubp, bool blank)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

967

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

992

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

996

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

31

#define TO_DCN20_HUBP(hubp)\

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

310

struct hubp base;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

32

container_of(hubp, struct dcn20_hubp, base)

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

326

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

330

void hubp2_vready_at_or_After_vsync(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

334

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

337

void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

345

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

349

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

353

bool hubp2_dmdata_status_done(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

356

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

360

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

362

void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

365

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

370

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

374

void hubp2_dcc_control(struct hubp *hubp, bool enable,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

378

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

384

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

389

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

393

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

402

bool hubp2_is_flip_pending(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

404

void hubp2_set_blank(struct hubp *hubp, bool blank);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

405

void hubp2_set_blank_regs(struct hubp *hubp, bool blank);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

408

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

412

void hubp2_clk_cntl(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

414

void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

416

void hubp2_clear_underflow(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

418

void hubp2_read_state_common(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

420

void hubp2_read_state(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

422

void hubp2_clear_tiling(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

107

hubp2_vready_at_or_After_vsync(hubp, pipe_dest);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

108

hubp201_program_requestor(hubp, rq_regs);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

109

hubp201_program_deadline(hubp, dlg_attr, ttu_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

43

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

52

hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

53

hubp1_program_tiling(hubp, tiling_info, format);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

54

hubp1_program_size(hubp, format, plane_size, dcc);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

55

hubp1_program_pixel_format(hubp, format);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

59

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

63

hubp1_program_deadline(hubp, dlg_attr, ttu_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

66

static void hubp201_program_requestor(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

69

struct dcn201_hubp *hubp201 = TO_DCN201_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

97

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

117

struct hubp base;

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

32

#define TO_DCN201_HUBP(hubp)\

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

33

container_of(hubp, struct dcn201_hubp, base)

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

128

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

132

hubp2_program_deadline(hubp, dlg_attr, ttu_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

134

apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

138

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

141

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

170

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

180

hubp2_vready_at_or_After_vsync(hubp, pipe_dest);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

181

hubp21_program_requestor(hubp, rq_regs);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

182

hubp21_program_deadline(hubp, dlg_attr, ttu_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

187

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

191

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

228

static void hubp21_set_vm_system_aperture_settings(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

231

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

251

static void hubp21_validate_dml_output(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

257

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

594

static void program_surface_flip_and_addr(struct hubp *hubp, struct surface_flip_registers *flip_regs)

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

596

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

667

static void dmcub_PLAT_54186_wa(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

670

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

686

cmd.PLAT_54186_wa.flip.flip_params.hubp_inst = hubp->inst;

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

692

dc_wake_and_execute_dmub_cmd(hubp->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

697

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

78

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

794

if (hubp->ctx->dc->debug.enable_dmcub_surface_flip && address->type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

795

dmcub_PLAT_54186_wa(hubp, &flip_regs);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

797

program_surface_flip_and_addr(hubp, &flip_regs);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

799

hubp->request_address = *address;

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

804

static void hubp21_init(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

809

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

81

struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

813

hubp_reset(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

106

struct hubp base;

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

123

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

127

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

132

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

32

#define TO_DCN21_HUBP(hubp)\

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

33

container_of(hubp, struct dcn21_hubp, base)

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

314

hubp->request_address = *address;

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

338

void hubp3_clear_tiling(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

340

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

354

void hubp3_dcc_control(struct hubp *hubp, bool enable,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

358

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

367

void hubp3_dcc_control_sienna_cichlid(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

370

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

382

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

385

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

413

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

423

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

425

hubp3_dcc_control_sienna_cichlid(hubp, dcc);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

427

hubp2_program_size(hubp, format, plane_size, dcc);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

428

hubp2_program_rotation(hubp, rotation, horizontal_mirror);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

429

hubp2_program_pixel_format(hubp, format);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

433

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

437

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

439

hubp2_program_deadline(hubp, dlg_attr, ttu_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

444

void hubp3_read_state(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

446

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

45

void hubp3_set_vm_system_aperture_settings(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

450

hubp2_read_state_common(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

48

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

481

void hubp3_read_reg_state(struct hubp *hubp, struct dcn_hubp_reg_state *reg_state)

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

483

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

602

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

611

hubp2_vready_at_or_After_vsync(hubp, pipe_dest);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

612

hubp21_program_requestor(hubp, rq_regs);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

613

hubp3_program_deadline(hubp, dlg_attr, ttu_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

616

void hubp3_init(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

621

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

627

hubp_reset(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

69

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

73

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

257

void hubp3_set_vm_system_aperture_settings(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

261

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

266

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

276

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

287

void hubp3_dcc_control(struct hubp *hubp, bool enable,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

290

void hubp3_dcc_control_sienna_cichlid(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

294

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

297

void hubp3_read_state(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

299

void hubp3_read_reg_state(struct hubp *hubp, struct dcn_hubp_reg_state *reg_state);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

301

void hubp3_init(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

303

void hubp3_clear_tiling(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

305

uint32_t hubp3_get_current_read_line(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

307

uint32_t hubp3_get_underflow_status(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

42

void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable)

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

44

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

50

void hubp31_soft_reset(struct hubp *hubp, bool reset)

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

52

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

57

static void hubp31_program_extended_blank(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

60

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

66

struct hubp *hubp, unsigned int min_dst_y_next_start_optimized)

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

68

hubp31_program_extended_blank(hubp, min_dst_y_next_start_optimized);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

71

uint32_t hubp31_get_det_config_error(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

74

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

244

void hubp31_soft_reset(struct hubp *hubp, bool reset);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

246

void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

249

struct hubp *hubp, unsigned int min_dst_y_next_start_optimized);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

251

uint32_t hubp31_get_det_config_error(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

109

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

112

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

141

hubp->curs_attr = *attr;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

143

if (!hubp->cursor_offload) {

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

167

hubp->att.SURFACE_ADDR_HIGH = attr->address.high_part;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

168

hubp->att.SURFACE_ADDR = attr->address.low_part;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

169

hubp->att.size.bits.width = attr->width;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

170

hubp->att.size.bits.height = attr->height;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

171

hubp->att.cur_ctl.bits.mode = attr->color_format;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

173

hubp->cur_rect.w = attr->width;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

174

hubp->cur_rect.h = attr->height;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

176

hubp->att.cur_ctl.bits.pitch = hw_pitch;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

177

hubp->att.cur_ctl.bits.line_per_chunk = lpc;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

178

hubp->att.cur_ctl.bits.cur_2x_magnify = attr->attribute_flags.bits.ENABLE_MAGNIFICATION;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

179

hubp->att.settings.bits.dst_y_offset = 0;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

180

hubp->att.settings.bits.chunk_hdl_adjust = 3;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

181

hubp->use_mall_for_cursor = use_mall_for_cursor;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

183

void hubp32_init(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

185

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

42

void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow)

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

44

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

50

void hubp32_update_force_cursor_pstate_disallow(struct hubp *hubp, bool pstate_disallow)

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

52

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

59

void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor)

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

61

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

68

void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable)

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

70

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

86

void hubp32_phantom_hubp_post_enable(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

89

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

47

void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

49

void hubp32_update_force_cursor_pstate_disallow(struct hubp *hubp, bool pstate_disallow);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

51

void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

53

void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

55

void hubp32_phantom_hubp_post_enable(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

57

void hubp32_cursor_set_attributes(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

60

void hubp32_init(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

173

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

183

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

185

hubp3_dcc_control_sienna_cichlid(hubp, dcc);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

187

hubp2_program_size(hubp, format, plane_size, dcc);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

188

hubp2_program_rotation(hubp, rotation, horizontal_mirror);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

189

hubp35_program_pixel_format(hubp, format);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

41

void hubp35_set_fgcg(struct hubp *hubp, bool enable)

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

43

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

48

void hubp35_init(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

50

hubp3_init(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

52

hubp35_set_fgcg(hubp, hubp->ctx->dc->debug.enable_fine_grain_clock_gating.bits.dchub);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

58

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

61

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h

59

void hubp35_set_fgcg(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h

62

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h

66

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h

75

void hubp35_init(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

101

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1018

void hubp401_set_unbounded_requesting(struct hubp *hubp, bool enable)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1020

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

109

void hubp401_update_3dlut_fl_bias_scale(struct hubp *hubp, uint16_t bias, uint16_t scale)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

111

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

116

void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

118

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

123

void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_format format)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

125

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

131

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

134

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

167

void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

169

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

179

void hubp401_init(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

181

hubp_reset(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

184

void hubp401_vready_at_or_After_vsync(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

198

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

221

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

224

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

249

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

253

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

347

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

355

hubp401_vready_at_or_After_vsync(hubp, pipe_global_sync, timing);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

356

hubp401_program_requestor(hubp, &pipe_regs->rq_regs);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

357

hubp401_program_deadline(hubp, &pipe_regs->dlg_regs, &pipe_regs->ttu_regs);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

361

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

364

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

410

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

414

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

43

void hubp401_program_3dlut_fl_addr(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

46

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

52

void hubp401_program_3dlut_fl_dlg_param(struct hubp *hubp, int refcyc_per_3dlut_group)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

54

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

555

hubp->request_address = *address;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

560

void hubp401_clear_tiling(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

562

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

572

void hubp401_dcc_control(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

575

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

59

void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

597

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

603

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

61

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

632

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

642

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

644

hubp401_dcc_control(hubp, dcc);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

646

hubp401_program_size(hubp, format, plane_size, dcc);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

647

hubp2_program_rotation(hubp, rotation, horizontal_mirror);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

648

hubp2_program_pixel_format(hubp, format);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

652

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

656

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

66

uint32_t hubp401_get_3dlut_fl_done(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

68

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

694

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

697

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

713

void hubp401_set_flip_int(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

715

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

723

bool hubp401_in_blank(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

725

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

734

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

738

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

746

hubp->curs_pos = *pos;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

75

void hubp401_program_3dlut_fl_addressing_mode(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

762

if (hubp->curs_attr.address.quad_part == 0)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

77

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

770

(1 + hubp->curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

784

if (hubp->pos.cur_ctl.bits.cur_enable != cur_en) {

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

786

hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

788

if (!hubp->cursor_offload)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

793

if (!hubp->cursor_offload) {

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

806

hubp->pos.cur_ctl.bits.cur_enable = cur_en;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

807

hubp->pos.position.bits.x_pos = pos->x;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

808

hubp->pos.position.bits.y_pos = pos->y;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

809

hubp->pos.hot_spot.bits.x_hot = pos->x_hotspot;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

810

hubp->pos.hot_spot.bits.y_hot = pos->y_hotspot;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

811

hubp->pos.dst_offset.bits.dst_x_offset = dst_x_offset;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

82

void hubp401_program_3dlut_fl_width(struct hubp *hubp, enum hubp_3dlut_fl_width width)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

822

hubp->cur_rect.x = rec_x_offset + param->recout.x;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

823

hubp->cur_rect.y = rec_y_offset + param->recout.y;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

826

void hubp401_read_state(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

828

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

84

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

89

void hubp401_program_3dlut_fl_tmz_protected(struct hubp *hubp, uint8_t protection_bits)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

91

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

96

void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

259

void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

262

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

268

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

272

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

276

void hubp401_dcc_control(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

285

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

291

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

300

void hubp401_set_viewport(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

304

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

306

void hubp401_set_flip_int(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

308

bool hubp401_in_blank(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

311

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

315

void hubp401_read_state(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

325

void hubp401_init(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

327

uint32_t hubp401_get_3dlut_fl_done(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

329

void hubp401_set_unbounded_requesting(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

331

void hubp401_update_3dlut_fl_bias_scale(struct hubp *hubp, uint16_t bias, uint16_t scale);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

333

void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

338

void hubp401_program_3dlut_fl_tmz_protected(struct hubp *hubp, uint8_t protection_bits);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

340

void hubp401_program_3dlut_fl_width(struct hubp *hubp, enum hubp_3dlut_fl_width width);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

342

void hubp401_program_3dlut_fl_addressing_mode(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

344

void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

346

void hubp401_program_3dlut_fl_dlg_param(struct hubp *hubp, int refcyc_per_3dlut_group);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

348

void hubp401_program_3dlut_fl_addr(struct hubp *hubp, const struct dc_plane_address address);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

350

void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_format format);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

352

void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

355

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

358

void hubp401_clear_tiling(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

360

void hubp401_vready_at_or_After_vsync(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

365

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

369

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

151

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

155

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

19

static void hubp42_set_fgcg(struct hubp *hubp, bool enable)

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

21

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

249

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

252

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

26

static void hubp42_init(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

28

hubp3_init(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

282

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

290

hubp401_vready_at_or_After_vsync(hubp, pipe_global_sync, timing);

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

291

hubp42_program_requestor(hubp, &pipe_regs->rq_regs);

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

292

hubp42_program_deadline(hubp, &pipe_regs->dlg_regs, &pipe_regs->ttu_regs);

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

295

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

30

hubp42_set_fgcg(hubp, hubp->ctx->dc->debug.enable_fine_grain_clock_gating.bits.dchub);

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

305

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

307

hubp3_dcc_control_sienna_cichlid(hubp, dcc);

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

309

hubp2_program_size(hubp, format, plane_size, dcc);

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

310

hubp2_program_rotation(hubp, rotation, horizontal_mirror);

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

311

hubp42_program_pixel_format(hubp, format);

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

314

void hubp42_program_3dlut_fl_crossbar(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

319

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

328

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

332

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

36

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

39

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

573

hubp->request_address = *address;

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

645

void hubp42_read_state(struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

647

struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c

651

hubp401_read_state(hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h

81

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h

86

void hubp42_read_state(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h

89

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h

93

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1081

struct hubp *hubp = dc->res_pool->hubps[0];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1086

hubp->funcs->set_blank(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1101

struct hubp *hubp = dc->res_pool->hubps[0];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1124

hubp->funcs->set_hubp_blank_en(hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1398

struct hubp *hubp ;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1417

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1419

if (hubp != NULL && hubp->funcs->set_hubp_blank_en)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1420

hubp->funcs->set_hubp_blank_en(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1430

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1432

if (hubp != NULL && hubp->funcs->hubp_disable_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1433

hubp->funcs->hubp_disable_control(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1440

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1442

if (hubp != NULL && hubp->funcs->hubp_disable_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1443

hubp->funcs->hubp_disable_control(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1452

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1454

if (hubp != NULL && hubp->funcs->set_hubp_blank_en)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1455

hubp->funcs->set_hubp_blank_en(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1490

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1512

if (hubp->funcs->hubp_disconnect)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1513

hubp->funcs->hubp_disconnect(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1534

struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1547

hws->funcs.hubp_pg_control(hws, hubp->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1549

hubp->funcs->hubp_reset(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1555

"Power gated front end %d\n", hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1568

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1570

int opp_id = hubp->opp_id;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1574

hubp->funcs->hubp_clk_cntl(hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1583

hubp->power_gated = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1588

pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1604

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1659

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1665

if (hubbub && hubp) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1667

hubbub->funcs->program_det_size(hubbub, hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1669

hubbub->funcs->program_det_segments(hubbub, hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1687

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1704

hubp->power_gated = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1712

hubp->funcs->hubp_reset(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1718

pipe_ctx->plane_res.hubp = hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1721

hubp->mpcc_id = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1722

hubp->opp_id = OPP_ID_INVALID;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1723

hubp->power_gated = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1738

pipe_ctx->plane_res.hubp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2064

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2065

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2764

static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2766

struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2773

hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2774

hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2792

pipe_ctx->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2795

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2803

dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2812

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2813

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2939

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2981

mpcc_id = hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3006

hubp->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3011

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3012

hubp->mpcc_id = mpcc_id;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3033

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

308

struct hubp *hubp = pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

309

struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3100

hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3102

hubp->funcs->hubp_setup(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3103

hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3108

hubp->funcs->hubp_setup_interdependent(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3109

hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

311

hubp->funcs->hubp_read_state(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3136

hubp->funcs->mem_program_viewport(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3137

hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

315

hubp->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3173

hubp->funcs->hubp_program_surface_config(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3174

hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3184

hubp->power_gated = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3189

hubp->funcs->set_blank(hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3596

static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3625

struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3631

hubp->funcs->set_blank(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3664

flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3665

pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3703

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3920

hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3921

dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3928

pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3929

pipe_ctx->plane_res.hubp, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4169

struct hubp *hubp = pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4170

struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4172

hubp->funcs->hubp_read_state(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4193

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4195

if (!hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4199

if (clear_tiling && hubp->funcs->hubp_clear_tiling)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4200

hubp->funcs->hubp_clear_tiling(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4203

hubp->funcs->hubp_program_surface_flip_and_addr(hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

860

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

868

if (hubp->funcs->hubp_get_underflow_status(hubp)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

869

hubp->funcs->hubp_clear_underflow(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

200

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1002

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1025

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1296

hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1303

"Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1317

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1320

pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1373

pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1379

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1380

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1422

if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp))

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1681

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1700

hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1702

if (hubp->funcs->hubp_setup2) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1703

hubp->funcs->hubp_setup2(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1704

hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1709

hubp->funcs->hubp_setup(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1710

hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1718

if (pipe_ctx->update_flags.bits.unbounded_req && hubp->funcs->set_unbounded_requesting)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1719

hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1722

if (hubp->funcs->hubp_setup_interdependent2) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1723

hubp->funcs->hubp_setup_interdependent2(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1724

hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1727

hubp->funcs->hubp_setup_interdependent(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1728

hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1786

hubp->funcs->mem_program_viewport(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1787

hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1793

if (hubp->funcs->hubp_program_mcache_id_and_split_coordinate)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1794

hubp->funcs->hubp_program_mcache_id_and_split_coordinate(hubp, &pipe_ctx->mcache_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1825

hubp->opp_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1842

hubp->funcs->hubp_program_surface_config(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1843

hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1851

hubp->power_gated = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1870

hubp->funcs->set_blank(hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1872

if (pipe_mall_type == SUBVP_PHANTOM && hubp->funcs->phantom_hubp_post_enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1873

hubp->funcs->phantom_hubp_post_enable(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1964

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1968

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2136

dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2139

hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2198

pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2201

pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2274

struct hubp *hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2278

&& hubp->funcs->hubp_is_flip_pending(hubp); j++)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2477

if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2480

pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2528

pipe_ctx->plane_res.hubp->funcs->hubp_setup(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2529

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2606

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2608

if (!hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2610

return hubp->funcs->dmdata_status_done(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2646

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2660

hubp->funcs->dmdata_set_attributes(hubp, &attr);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2746

(uint8_t)pipe_ctx->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2748

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2749

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2951

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2998

mpcc_id = hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3024

hubp->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3029

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

303

if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3030

hubp->mpcc_id = mpcc_id;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

304

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

305

pipe_ctx->plane_res.hubp, flip_immediate);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3126

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3139

if (!hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3146

hubp->inst, mode);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3216

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3222

pipe_ctx->plane_res.hubp = hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3225

hubp->mpcc_id = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3226

hubp->opp_id = OPP_ID_INVALID;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3227

hubp->power_gated = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3230

hubp->funcs->hubp_init(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3257

pipe_ctx->plane_res.hubp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

384

if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

385

pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

386

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

701

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

712

if (hubp->funcs->hubp_update_mall_sel)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

713

hubp->funcs->hubp_update_mall_sel(hubp, 0, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

717

hubp->funcs->hubp_clk_cntl(hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

721

hubp->power_gated = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

725

pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

745

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

152

pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

153

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

310

struct hubp *hubp = res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

316

pipe_ctx->plane_res.hubp = hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

319

hubp->mpcc_id = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

320

hubp->opp_id = OPP_ID_INVALID;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

321

hubp->power_gated = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

324

hubp->funcs->hubp_init(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

349

pipe_ctx->plane_res.hubp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

383

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

418

if (hubp->funcs->hubp_disconnect)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

419

hubp->funcs->hubp_disconnect(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

427

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

484

dpp_id = hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

524

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

525

hubp->mpcc_id = mpcc_id;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

565

pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

566

pipe_ctx->plane_res.hubp, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

574

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

591

hubp->funcs->dmdata_set_attributes(hubp, &attr);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1308

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1316

if (hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1317

if (hubp->funcs->hubp_read_reg_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1318

hubp->funcs->hubp_read_reg_state(hubp, out_data->hubp_reg_state[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

261

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

363

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

399

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

909

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

923

if (!hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

933

hubp->inst, dmdata_hdmi);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

939

hubp->inst, mode);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

655

dc->res_pool->hubbub, pipe_ctx_old->plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

658

dc->res_pool->hubbub, pipe_ctx_old->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

450

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

487

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

574

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

618

struct hubp *hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

626

if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

627

hubp->funcs->hubp_update_force_pstate_disallow(hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

628

if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

629

hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

638

struct hubp *hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

663

if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

664

hubp->funcs->hubp_update_force_pstate_disallow(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

665

if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

666

hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

683

struct hubp *hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

685

if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

686

int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

688

switch (hubp->curs_attr.color_format) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

709

hubp->funcs->hubp_update_mall_sel(hubp, 1, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

712

hubp->funcs->hubp_update_mall_sel(hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

743

struct hubp *hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

745

if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

752

hubp->funcs->hubp_prepare_subvp_buffering(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1002

if (!pipe_ctx->top_pipe && pipe_ctx->plane_res.hubp &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1003

pipe_ctx->plane_res.hubp->inst != pipe_ctx->stream_res.dsc->inst) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1082

if (j == PG_HUBP && new_pipe->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1083

update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1108

cur_pipe->plane_res.hubp != new_pipe->plane_res.hubp &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1109

new_pipe->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1110

update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1176

if (new_pipe->plane_res.hubp &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1177

new_pipe->plane_res.hubp->inst != new_pipe->stream_res.dsc->inst) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1691

if (pipe->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1692

pipe->plane_res.hubp->cursor_offload = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1705

if (pipe->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1706

pipe->plane_res.hubp->cursor_offload = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1731

const struct hubp *hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1736

if (!top_pipe || !hubp || !dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1745

p->CURSOR0_0_CURSOR_SURFACE_ADDRESS = hubp->att.SURFACE_ADDR;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1746

p->CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH = hubp->att.SURFACE_ADDR_HIGH;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1747

p->CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH = hubp->att.size.bits.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1748

p->CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT = hubp->att.size.bits.height;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1749

p->CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION = hubp->pos.position.bits.x_pos;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1750

p->CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION = hubp->pos.position.bits.y_pos;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1751

p->CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X = hubp->pos.hot_spot.bits.x_hot;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1752

p->CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y = hubp->pos.hot_spot.bits.y_hot;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1753

p->CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET = hubp->pos.dst_offset.bits.dst_x_offset;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1754

p->CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE = hubp->pos.cur_ctl.bits.cur_enable;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1755

p->CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE = hubp->att.cur_ctl.bits.mode;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1756

p->CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY = hubp->pos.cur_ctl.bits.cur_2x_magnify;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1757

p->CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH = hubp->att.cur_ctl.bits.pitch;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1758

p->CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK = hubp->att.cur_ctl.bits.line_per_chunk;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1769

p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET = hubp->att.settings.bits.dst_y_offset;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1770

p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST = hubp->att.settings.bits.chunk_hdl_adjust;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

684

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

690

if (hubbub && hubp) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

692

hubbub->funcs->program_det_size(hubbub, hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

694

hubbub->funcs->program_det_segments(hubbub, hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

712

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

729

hubp->power_gated = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

737

hubp->funcs->hubp_reset(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

743

pipe_ctx->plane_res.hubp = hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

746

hubp->mpcc_id = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

747

hubp->opp_id = OPP_ID_INVALID;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

748

hubp->power_gated = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

763

pipe_ctx->plane_res.hubp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

841

pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

844

pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

861

pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

868

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

869

pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

877

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

894

hubp->funcs->hubp_clk_cntl(hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

898

hubp->power_gated = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

900

hubp->funcs->hubp_reset(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

921

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

986

if (pipe_ctx->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

987

update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->plane_res.hubp->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

989

if (pipe_ctx->plane_res.dpp && pipe_ctx->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

990

update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->plane_res.hubp->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1128

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1223

if (hubp->curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1224

adjust_hotspot_between_slices_for_2x_magnify(hubp->curs_attr.width, &pos_cpy);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1244

if (hubp->curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1245

adjust_hotspot_between_slices_for_2x_magnify(hubp->curs_attr.width, &pos_cpy);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1267

if (hubp->curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1268

adjust_hotspot_between_slices_for_2x_magnify(hubp->curs_attr.width, &pos_cpy);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1286

if (recout_x_pos + (int)hubp->curs_attr.width <= 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1289

if (recout_y_pos + (int)hubp->curs_attr.height <= 0)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1295

hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1296

dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1550

if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1553

pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1918

dpp_pipe->plane_res.hubp &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1920

hubbub->funcs->wait_for_det_update(hubbub, dpp_pipe->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1923

if (hubbub && opp_heads[slice_idx]->plane_res.hubp && hubbub->funcs->wait_for_det_update)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1924

hubbub->funcs->wait_for_det_update(hubbub, opp_heads[slice_idx]->plane_res.hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2016

if (wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2017

wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2025

if (wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2026

wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2272

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2275

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2420

pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2425

pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2605

dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2608

hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2667

pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2670

pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2706

struct hubp *hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2710

&& hubp->funcs->hubp_is_flip_pending(hubp); j++)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2849

if (pipe_ctx->plane_res.hubp->funcs->hubp_setup2)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2850

pipe_ctx->plane_res.hubp->funcs->hubp_setup2(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2851

pipe_ctx->plane_res.hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3059

struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3075

hws->funcs.hubp_pg_control(hws, hubp->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3077

hubp->funcs->hubp_reset(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3085

"Power gated front end %d\n", hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3095

const struct hubp *hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3100

if (!top_pipe || !hubp || !dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3109

p->CURSOR0_0_CURSOR_SURFACE_ADDRESS = hubp->att.SURFACE_ADDR;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3110

p->CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH = hubp->att.SURFACE_ADDR_HIGH;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3111

p->CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH = hubp->att.size.bits.width;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3112

p->CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT = hubp->att.size.bits.height;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3113

p->CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION = hubp->pos.position.bits.x_pos;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3114

p->CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION = hubp->pos.position.bits.y_pos;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3115

p->CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X = hubp->pos.hot_spot.bits.x_hot;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3116

p->CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y = hubp->pos.hot_spot.bits.y_hot;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3117

p->CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET = hubp->pos.dst_offset.bits.dst_x_offset;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3118

p->CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE = hubp->pos.cur_ctl.bits.cur_enable;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3119

p->CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE = hubp->att.cur_ctl.bits.mode;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3120

p->CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY = hubp->pos.cur_ctl.bits.cur_2x_magnify;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3121

p->CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH = hubp->att.cur_ctl.bits.pitch;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3122

p->CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK = hubp->att.cur_ctl.bits.line_per_chunk;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3140

p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET = hubp->att.settings.bits.dst_y_offset;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3141

p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST = hubp->att.settings.bits.chunk_hdl_adjust;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3142

p->HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR = hubp->use_mall_for_cursor;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3149

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3166

hwss_add_hubp_pg_control(seq_state, hws, hubp->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3169

hwss_add_hubp_reset(seq_state, hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3178

DC_LOG_DEBUG("Power gated front end %d\n", hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3190

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3218

if (hubp->funcs->hubp_disconnect)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3219

hwss_add_hubp_disconnect(seq_state, hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3539

if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3553

if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs->hubp_update_mall_sel)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3554

hwss_add_hubp_update_mall_sel(seq_state, pipe_ctx->plane_res.hubp, 0, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3557

hwss_add_hubp_set_flip_control_gsl(seq_state, pipe_ctx->plane_res.hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3560

hwss_add_hubp_clk_cntl(seq_state, pipe_ctx->plane_res.hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3568

pipe_ctx->plane_res.hubp, seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3638

if (!pipe_ctx->plane_res.dpp || !pipe_ctx->plane_res.hubp || !pipe_ctx->stream_res.opp)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3658

hwss_add_hubp_pg_control(seq_state, hws, pipe_ctx->plane_res.hubp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3665

if (pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3666

hwss_add_hubp_clk_cntl(seq_state, pipe_ctx->plane_res.hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3669

if (pipe_ctx->plane_res.hubp->funcs->hubp_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3670

hwss_add_hubp_init(seq_state, pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3677

if (dc->vm_pa_config.valid && pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3678

hwss_add_hubp_set_vm_system_aperture_settings(seq_state, pipe_ctx->plane_res.hubp, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3686

&& pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3687

hwss_add_hubp_set_flip_int(seq_state, pipe_ctx->plane_res.hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3697

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3704

if (!hubp || !dpp || !plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3717

hwss_add_hubp_vtg_sel(seq_state, hubp, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3720

if (hubp->funcs->hubp_setup2) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3721

hwss_add_hubp_setup2(seq_state, hubp, &pipe_ctx->hubp_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3723

} else if (hubp->funcs->hubp_setup) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3724

hwss_add_hubp_setup(seq_state, hubp, &pipe_ctx->dlg_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3730

if (pipe_ctx->update_flags.bits.unbounded_req && hubp->funcs->set_unbounded_requesting)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3731

hwss_add_hubp_set_unbounded_requesting(seq_state, hubp, pipe_ctx->unbounded_req);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3735

if (hubp->funcs->hubp_setup_interdependent2)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3736

hwss_add_hubp_setup_interdependent2(seq_state, hubp, &pipe_ctx->hubp_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3737

else if (hubp->funcs->hubp_setup_interdependent)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3738

hwss_add_hubp_setup_interdependent(seq_state, hubp, &pipe_ctx->dlg_regs, &pipe_ctx->ttu_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3788

hwss_add_hubp_mem_program_viewport(seq_state, hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3794

if (hubp->funcs->hubp_program_mcache_id_and_split_coordinate)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3795

hwss_add_hubp_program_mcache_id(seq_state, hubp, &pipe_ctx->mcache_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3826

pipe_ctx->stream->csc_color_matrix.matrix, hubp->opp_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3844

hwss_add_hubp_program_surface_config(seq_state, hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3848

hubp->power_gated = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3868

hwss_add_hubp_set_blank(seq_state, hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3871

if (pipe_mall_type == SUBVP_PHANTOM && hubp->funcs->phantom_hubp_post_enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3872

hwss_add_phantom_hubp_post_enable(seq_state, hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3879

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3887

if (!hubp || !pipe_ctx->plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3924

mpcc_id = hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3951

hwss_add_mpc_insert_plane(seq_state, mpc, mpc_tree_params, blnd_cfg, NULL, NULL, hubp->inst, mpcc_id);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3957

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3958

hubp->mpcc_id = mpcc_id;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3961

static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3989

struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3996

if (hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3997

hwss_add_hubp_set_blank(seq_state, hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4047

struct hubp *hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4049

if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4050

int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4052

switch (hubp->curs_attr.color_format) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4073

hwss_add_hubp_update_mall_sel(seq_state, hubp, 1, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4080

hwss_add_hubp_update_mall_sel(seq_state, hubp, mall_sel, cache_cursor);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4088

struct hubp *hubp = pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4090

if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4092

hwss_add_hubp_prepare_subvp_buffering(seq_state, hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4114

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4125

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4126

if (hubp != NULL && hubp->funcs->set_hubp_blank_en)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4127

hwss_add_hubp_set_blank_en(seq_state, hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4139

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4140

if (hubp != NULL && hubp->funcs->hubp_disable_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4141

hwss_add_hubp_disable_control(seq_state, hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4150

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4151

if (hubp != NULL && hubp->funcs->hubp_disable_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4152

hwss_add_hubp_disable_control(seq_state, hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

416

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4164

hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4165

if (hubp != NULL && hubp->funcs->set_hubp_blank_en)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4166

hwss_add_hubp_set_blank_en(seq_state, hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

447

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

448

int mpcc_id = hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

509

if (hubp->funcs->hubp_enable_3dlut_fl)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

510

hubp->funcs->hubp_enable_3dlut_fl(hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

548

if (hubp->funcs->hubp_program_3dlut_fl_addr)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

549

hubp->funcs->hubp_program_3dlut_fl_addr(hubp, mcm_luts.lut3d_data.gpu_mem_params.addr);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

572

if (hubp->funcs->hubp_program_3dlut_fl_mode)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

573

hubp->funcs->hubp_program_3dlut_fl_mode(hubp, mode);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

575

if (hubp->funcs->hubp_program_3dlut_fl_addressing_mode)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

576

hubp->funcs->hubp_program_3dlut_fl_addressing_mode(hubp, addr_mode);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

589

if (hubp->funcs->hubp_program_3dlut_fl_format)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

590

hubp->funcs->hubp_program_3dlut_fl_format(hubp, format);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

591

if (hubp->funcs->hubp_update_3dlut_fl_bias_scale &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

597

hubp->funcs->hubp_update_3dlut_fl_bias_scale(hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

613

if (hubp->funcs->hubp_program_3dlut_fl_crossbar)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

614

hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

626

mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

628

if (hubp->funcs->hubp_enable_3dlut_fl)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

629

hubp->funcs->hubp_enable_3dlut_fl(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

645

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

647

if (hubp->funcs->hubp_enable_3dlut_fl) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

648

hubp->funcs->hubp_enable_3dlut_fl(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

656

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

710

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

119

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

122

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1005

if (pipe_ctx->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1006

update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->plane_res.hubp->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1008

if (pipe_ctx->plane_res.dpp && pipe_ctx->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1009

update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->plane_res.hubp->inst] = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1129

if (j == PG_HUBP && new_pipe->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1130

update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1155

cur_pipe->plane_res.hubp != new_pipe->plane_res.hubp &&

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1156

new_pipe->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1157

update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

300

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

348

mpcc_id = hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

374

hubp->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

379

hubp->opp_id = pipe_ctx->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

380

hubp->mpcc_id = mpcc_id;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

458

static bool dc_is_rmcm_3dlut_supported(struct hubp *hubp, struct mpc *mpc)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

462

hubp->funcs->hubp_program_3dlut_fl_config)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

482

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

501

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

559

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

579

struct dc *dc = hubp->ctx->dc;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

635

if (!dc_is_rmcm_3dlut_supported(hubp, mpc) ||

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

671

mpc_fl_config.hubp_index = hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

681

hubp->funcs->hubp_program_3dlut_fl_config(hubp, &fl_config);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

700

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

701

int mpcc_id = hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

730

hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

782

if (hubp->funcs->hubp_enable_3dlut_fl)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

783

hubp->funcs->hubp_enable_3dlut_fl(hubp, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

820

if (hubp->funcs->hubp_program_3dlut_fl_addr)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

821

hubp->funcs->hubp_program_3dlut_fl_addr(hubp, mcm_luts.lut3d_data.gpu_mem_params.addr);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

827

if (hubp->funcs->hubp_program_3dlut_fl_mode)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

828

hubp->funcs->hubp_program_3dlut_fl_mode(hubp, mode);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

830

if (hubp->funcs->hubp_program_3dlut_fl_addressing_mode)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

831

hubp->funcs->hubp_program_3dlut_fl_addressing_mode(hubp, addr_mode);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

844

if (hubp->funcs->hubp_program_3dlut_fl_format)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

845

hubp->funcs->hubp_program_3dlut_fl_format(hubp, format);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

846

if (hubp->funcs->hubp_update_3dlut_fl_bias_scale &&

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

852

hubp->funcs->hubp_update_3dlut_fl_bias_scale(hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

865

if (hubp->funcs->hubp_program_3dlut_fl_crossbar)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

866

hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

878

mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

880

if (hubp->funcs->hubp_enable_3dlut_fl)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

881

hubp->funcs->hubp_enable_3dlut_fl(hubp, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

897

int mpcc_id = pipe_ctx->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h

27

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

100

hubbub->funcs->program_det_segments(hubbub, hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

122

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

139

hubp->power_gated = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

147

hubp->funcs->hubp_reset(hubp);

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

153

pipe_ctx->plane_res.hubp = hubp;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

156

hubp->mpcc_id = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

157

hubp->opp_id = OPP_ID_INVALID;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

158

hubp->power_gated = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

173

pipe_ctx->plane_res.hubp = NULL;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

90

struct hubp *hubp = dc->res_pool->hubps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

96

if (hubbub && hubp) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

98

hubbub->funcs->program_det_size(hubbub, hubp->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

102

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

184

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1923

struct hubp *hubp, bool flip_immediate);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

195

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1968

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2010

struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2036

struct hubp *hubp, unsigned int timeout_us, unsigned int polling_interval_us);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2054

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

211

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2138

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2143

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2147

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2151

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2160

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2205

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2209

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2212

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2222

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2228

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2236

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2240

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2246

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2253

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2257

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2261

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2265

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2305

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2318

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2341

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2370

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

458

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

472

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

548

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

554

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

559

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

564

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

575

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

580

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

584

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

592

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

618

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

665

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

670

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

677

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

685

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

690

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

695

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

717

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

723

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

754

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

76

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

782

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

787

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

866

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

127

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

130

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

67

struct hubp;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

250

struct hubp *hubps[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

388

struct hubp *hubp;

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

160

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

167

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

173

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

178

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

181

void (*dcc_control)(struct hubp *hubp, bool enable,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

184

void (*hubp_reset)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

187

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

192

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

197

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

203

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

207

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

211

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

220

bool (*hubp_is_flip_pending)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

222

void (*set_blank)(struct hubp *hubp, bool blank);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

223

void (*set_blank_regs)(struct hubp *hubp, bool blank);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

224

void (*phantom_hubp_post_enable)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

225

void (*set_hubp_blank_en)(struct hubp *hubp, bool blank);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

228

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

232

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

236

void (*hubp_disconnect)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

238

void (*hubp_clk_cntl)(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

239

void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

240

void (*hubp_read_state)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

241

void (*hubp_read_reg_state)(struct hubp *hubp, struct dcn_hubp_reg_state *reg_state);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

242

void (*hubp_clear_underflow)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

243

void (*hubp_disable_control)(struct hubp *hubp, bool disable_hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

244

unsigned int (*hubp_get_underflow_status)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

245

void (*hubp_init)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

247

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

251

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

254

bool (*dmdata_status_done)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

256

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

260

struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

263

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

267

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

273

struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

275

bool (*hubp_in_blank)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

276

void (*hubp_soft_reset)(struct hubp *hubp, bool reset);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

278

void (*hubp_set_flip_int)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

280

void (*hubp_update_force_pstate_disallow)(struct hubp *hubp, bool allow);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

281

void (*hubp_update_force_cursor_pstate_disallow)(struct hubp *hubp, bool allow);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

282

void (*hubp_update_mall_sel)(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

283

void (*hubp_prepare_subvp_buffering)(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

284

void (*hubp_surface_update_lock)(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

287

void (*program_extended_blank)(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

290

void (*hubp_wait_pipe_read_start)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

291

void (*hubp_program_mcache_id_and_split_coordinate)(struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

292

void (*hubp_update_3dlut_fl_bias_scale)(struct hubp *hubp, uint16_t bias, uint16_t scale);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

293

void (*hubp_program_3dlut_fl_mode)(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

295

void (*hubp_program_3dlut_fl_format)(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

297

void (*hubp_program_3dlut_fl_addr)(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

299

void (*hubp_program_3dlut_fl_dlg_param)(struct hubp *hubp, int refcyc_per_3dlut_group);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

300

void (*hubp_enable_3dlut_fl)(struct hubp *hubp, bool enable);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

301

void (*hubp_program_3dlut_fl_addressing_mode)(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

302

void (*hubp_program_3dlut_fl_width)(struct hubp *hubp, enum hubp_3dlut_fl_width width);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

303

void (*hubp_program_3dlut_fl_tmz_protected)(struct hubp *hubp, uint8_t protection_bits);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

304

void (*hubp_program_3dlut_fl_crossbar)(struct hubp *hubp,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

308

uint32_t (*hubp_get_3dlut_fl_done)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

309

void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, struct hubp_fl_3dlut_config *cfg);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

310

void (*hubp_clear_tiling)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

311

uint32_t (*hubp_get_current_read_line)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

312

uint32_t (*hubp_get_det_config_error)(struct hubp *hubp);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1014

static struct hubp *dcn10_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1139

idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1232

struct hubp *dcn20_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1528

next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1585

secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2219

sec_dpp_pipe->plane_res.hubp = pool->hubps[sec_dpp_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

105

struct hubp *dcn20_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1015

static struct hubp *dcn201_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1055

idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1012

static struct hubp *dcn21_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1355

static struct hubp *dcn30_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1693

sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1195

static struct hubp *dcn301_hubp_create(struct dc_context *ctx, uint32_t inst)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

623

static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

604

static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1652

static struct hubp *dcn31_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1711

static struct hubp *dcn31_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1654

static struct hubp *dcn31_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1644

static struct hubp *dcn31_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2946

idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

3005

free_pipe->plane_res.hubp = pool->hubps[free_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

3037

free_pipe->plane_res.hubp = pool->hubps[free_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

962

static struct hubp *dcn32_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

45

struct hubp *hubp = pipe_ctx->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

46

uint32_t cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

950

static struct hubp *dcn321_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1721

static struct hubp *dcn35_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1701

static struct hubp *dcn35_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1708

static struct hubp *dcn35_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

952

static struct hubp *dcn401_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

975

static struct hubp *dcn42_hubp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1010

static struct hubp *dcn42b_hubp_create(