arch/mips/kernel/elf.c

267

static inline void set_thread_fp_mode(int hybrid, int regs32)

arch/mips/kernel/elf.c

269

if (hybrid)

arch/x86/events/core.c

1165

union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap);

arch/x86/events/core.c

1570

cntr_mask = hybrid(cpuc->pmu, cntr_mask);

arch/x86/events/core.c

1571

fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask);

arch/x86/events/core.c

1572

pebs_constraints = hybrid(cpuc->pmu, pebs_constraints);

arch/x86/events/core.c

1647

union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap);

arch/x86/events/core.c

173

struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);

arch/x86/events/core.c

2122

pr_info("... generic bitmap: %016llx\n", hybrid(pmu, cntr_mask64));

arch/x86/events/core.c

2124

pr_info("... fixed-purpose bitmap: %016llx\n", hybrid(pmu, fixed_cntr_mask64));

arch/x86/events/core.c

2127

pr_info("... global_ctrl mask: %016llx\n", hybrid(pmu, intel_ctrl));

arch/x86/events/core.c

2560

if (!test_bit(i - INTEL_PMC_IDX_FIXED, hybrid(cpuc->pmu, fixed_cntr_mask)))

arch/x86/events/core.c

569

if (hybrid(pmu, arch_pebs_cap).pdists)

arch/x86/events/intel/core.c

2528

u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);

arch/x86/events/intel/core.c

3205

cap = hybrid(cpuc->pmu, arch_pebs_cap);

arch/x86/events/intel/core.c

3421

unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask);

arch/x86/events/intel/core.c

3422

unsigned long *fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask);

arch/x86/events/intel/core.c

3600

status &= hybrid(cpuc->pmu, intel_ctrl);

arch/x86/events/intel/core.c

3768

struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs);

arch/x86/events/intel/core.c

3803

struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);

arch/x86/events/intel/core.c

3963

struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints);

arch/x86/events/intel/core.c

4500

union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap);

arch/x86/events/intel/core.c

4586

return !!hybrid(pmu, acr_cause_mask64);

arch/x86/events/intel/core.c

4609

caps = hybrid(pmu, arch_pebs_cap).caps;

arch/x86/events/intel/core.c

4619

event->hw.dyn_constraint &= hybrid(event->pmu, acr_cntr_mask64);

arch/x86/events/intel/core.c

4628

event->hw.dyn_constraint &= hybrid(event->pmu, acr_cause_mask64);

arch/x86/events/intel/core.c

4662

struct arch_pebs_cap pebs_cap = hybrid(event->pmu, arch_pebs_cap);

arch/x86/events/intel/core.c

4679

u64 cntr_mask = hybrid(event->pmu, intel_ctrl) &

arch/x86/events/intel/core.c

4848

if (hweight64(cause_mask) > hweight64(hybrid(pmu, acr_cause_mask64)) ||

arch/x86/events/intel/core.c

4849

num > hweight64(hybrid(event->pmu, acr_cntr_mask64)))

arch/x86/events/intel/core.c

5000

u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);

arch/x86/events/intel/core.c

5505

u64 mask = hybrid(dev_get_drvdata(dev), config_mask) & ARCH_PERFMON_EVENTSEL_UMASK2;

arch/x86/events/intel/core.c

5541

mask = hybrid(dev_get_drvdata(dev), config_mask);

arch/x86/events/intel/core.c

5547

union perf_capabilities intel_cap = hybrid(dev_get_drvdata(dev), intel_cap);

arch/x86/events/intel/core.c

5813

mask = hybrid(pmu, acr_cntr_mask64) & GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0);

arch/x86/events/intel/core.c

5816

if (hybrid(pmu, acr_cntr_mask64) == hybrid(pmu, acr_cause_mask64))

arch/x86/events/intel/core.c

5818

mask = hybrid(pmu, acr_cause_mask64) & GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0);

arch/x86/events/intel/core.c

5822

mask = hybrid(pmu, arch_pebs_cap).counters;

arch/x86/events/intel/core.c

5826

mask = hybrid(pmu, arch_pebs_cap).pdists;

arch/x86/events/intel/core.c

5839

struct event_constraint *event_constraints = hybrid(pmu, event_constraints);

arch/x86/events/intel/core.c

5840

struct event_constraint *pebs_constraints = hybrid(pmu, pebs_constraints);

arch/x86/events/intel/core.c

5841

u64 cntr_mask = hybrid(pmu, cntr_mask64);

arch/x86/events/intel/core.c

5842

u64 fixed_cntr_mask = hybrid(pmu, fixed_cntr_mask64);

arch/x86/events/intel/core.c

5843

u64 intel_ctrl = hybrid(pmu, intel_ctrl);

arch/x86/events/intel/core.c

5871

if (hybrid(pmu, arch_pebs_cap).caps & ARCH_PEBS_VECR_XMM)

arch/x86/events/intel/core.c

5877

u64 caps = hybrid(pmu, arch_pebs_cap).caps;

arch/x86/events/intel/core.c

5907

hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_UMASK2;

arch/x86/events/intel/core.c

5909

hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_EQ;

arch/x86/events/intel/core.c

5911

hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE;

arch/x86/events/intel/core.c

5916

hybrid(pmu, cntr_mask64) = eax;

arch/x86/events/intel/core.c

5917

hybrid(pmu, fixed_cntr_mask64) = ebx;

arch/x86/events/intel/core.c

5925

hybrid(pmu, acr_cntr_mask64) = counter_mask(eax, ebx);

arch/x86/events/intel/core.c

5927

hybrid(pmu, acr_cause_mask64) = counter_mask(ecx, edx);

arch/x86/events/intel/core.c

5934

hybrid(pmu, arch_pebs_cap).caps = (u64)ebx << 32;

arch/x86/events/intel/core.c

5940

hybrid(pmu, arch_pebs_cap).counters = pebs_mask;

arch/x86/events/intel/core.c

5941

hybrid(pmu, arch_pebs_cap).pdists = pdists_mask;

arch/x86/events/intel/core.c

5956

rdmsrq(MSR_IA32_PERF_CAPABILITIES, hybrid(pmu, intel_cap).capabilities);

arch/x86/events/intel/core.c

7454

hybrid(pmu, event_constraints) = intel_glc_event_constraints;

arch/x86/events/intel/core.c

7455

hybrid(pmu, pebs_constraints) = intel_glc_pebs_event_constraints;

arch/x86/events/intel/core.c

7474

hybrid(pmu, event_constraints) = intel_grt_event_constraints;

arch/x86/events/intel/core.c

7475

hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints;

arch/x86/events/intel/core.c

7476

hybrid(pmu, extra_regs) = intel_grt_extra_regs;

arch/x86/events/intel/core.c

7484

hybrid(pmu, event_constraints) = intel_lnc_event_constraints;

arch/x86/events/intel/core.c

7485

hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints;

arch/x86/events/intel/core.c

7486

hybrid(pmu, extra_regs) = intel_lnc_extra_regs;

arch/x86/events/intel/core.c

7498

hybrid(pmu, event_constraints) = intel_pnc_event_constraints;

arch/x86/events/intel/core.c

7499

hybrid(pmu, pebs_constraints) = intel_pnc_pebs_event_constraints;

arch/x86/events/intel/core.c

7500

hybrid(pmu, extra_regs) = intel_pnc_extra_regs;

arch/x86/events/intel/core.c

7506

hybrid(pmu, event_constraints) = intel_skt_event_constraints;

arch/x86/events/intel/core.c

7507

hybrid(pmu, extra_regs) = intel_cmt_extra_regs;

arch/x86/events/intel/core.c

7518

hybrid(pmu, event_constraints) = intel_arw_event_constraints;

arch/x86/events/intel/core.c

7519

hybrid(pmu, pebs_constraints) = intel_arw_pebs_event_constraints;

arch/x86/events/intel/core.c

7520

hybrid(pmu, extra_regs) = intel_arw_extra_regs;

arch/x86/events/intel/ds.c

1554

struct event_constraint *pebs_constraints = hybrid(event->pmu, pebs_constraints);

arch/x86/events/intel/ds.c

3197

mask = hybrid(cpuc->pmu, pebs_events_mask) |

arch/x86/events/intel/ds.c

3198

(hybrid(cpuc->pmu, fixed_cntr_mask64) << INTEL_PMC_IDX_FIXED);

arch/x86/events/intel/ds.c

3258

mask = hybrid(cpuc->pmu, arch_pebs_cap).counters & cpuc->pebs_enabled;

arch/x86/events/perf_event.h

1313

return hweight64(hybrid(pmu, cntr_mask64));

arch/x86/events/perf_event.h

1318

return fls64(hybrid(pmu, cntr_mask64));

arch/x86/events/perf_event.h

1323

return hweight64(hybrid(pmu, fixed_cntr_mask64));

arch/x86/events/perf_event.h

1328

return fls64(hybrid(pmu, fixed_cntr_mask64));

arch/x86/events/perf_event.h

1333

return event->attr.config & hybrid(event->pmu, config_mask);

arch/x86/events/perf_event.h

1338

return !!(hybrid(pmu, config_mask) &

arch/x86/events/perf_event.h

1452

u64 intel_ctrl = hybrid(pmu, intel_ctrl);

arch/x86/events/perf_event.h

1853

return fls((u32)hybrid(pmu, pebs_events_mask));

drivers/md/dm-table.c

901

unsigned int bio_based = 0, request_based = 0, hybrid = 0;

drivers/md/dm-table.c

919

hybrid = 1;

drivers/md/dm-table.c

931

if (hybrid && !bio_based && !request_based) {

tools/perf/arch/x86/tests/arch-tests.c

27

TEST_CASE_REASON("x86 hybrid event parsing", hybrid, "not hybrid"),