drivers/clk/clk-bm1880.c

543

data->hw_data.hws[clks[i].pll.id] = hw;

drivers/clk/clk-bm1880.c

550

clk_hw_unregister(data->hw_data.hws[clks[i].pll.id]);

drivers/clk/clk-bm1880.c

577

data->hw_data.hws[clks[i].id] = hw;

drivers/clk/clk-bm1880.c

584

clk_hw_unregister_mux(data->hw_data.hws[clks[i].id]);

drivers/clk/clk-bm1880.c

65

struct clk_hw_onecell_data hw_data;

drivers/clk/clk-bm1880.c

707

data->hw_data.hws[id] = hw;

drivers/clk/clk-bm1880.c

714

clk_hw_unregister(data->hw_data.hws[clks[i].div.id]);

drivers/clk/clk-bm1880.c

740

data->hw_data.hws[clks[i].id] = hw;

drivers/clk/clk-bm1880.c

747

clk_hw_unregister_gate(data->hw_data.hws[clks[i].id]);

drivers/clk/clk-bm1880.c

860

data->hw_data.hws[clks[i].id] = hw;

drivers/clk/clk-bm1880.c

867

clk_hw_unregister_composite(data->hw_data.hws[clks[i].id]);

drivers/clk/clk-bm1880.c

893

clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws,

drivers/clk/clk-bm1880.c

902

clk_data->hw_data.hws[i] = ERR_PTR(-ENOENT);

drivers/clk/clk-bm1880.c

904

clk_data->hw_data.num = num_clks;

drivers/clk/clk-bm1880.c

927

&clk_data->hw_data);

drivers/clk/clk-lan966x.c

226

struct clk_hw_onecell_data *hw_data,

drivers/clk/clk-lan966x.c

235

hw_data->hws[i] =

drivers/clk/clk-lan966x.c

241

if (IS_ERR(hw_data->hws[i]))

drivers/clk/clk-lan966x.c

242

return dev_err_probe(dev, PTR_ERR(hw_data->hws[i]),

drivers/clk/clk-lan966x.c

253

struct clk_hw_onecell_data *hw_data;

drivers/clk/clk-lan966x.c

263

hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, data->num_total_clks),

drivers/clk/clk-lan966x.c

265

if (!hw_data)

drivers/clk/clk-lan966x.c

274

hw_data->num = data->num_generic_clks;

drivers/clk/clk-lan966x.c

278

hw_data->hws[i] = lan966x_gck_clk_register(dev, i);

drivers/clk/clk-lan966x.c

279

if (IS_ERR(hw_data->hws[i])) {

drivers/clk/clk-lan966x.c

282

return PTR_ERR(hw_data->hws[i]);

drivers/clk/clk-lan966x.c

292

hw_data->num = data->num_total_clks;

drivers/clk/clk-lan966x.c

294

ret = lan966x_gate_clk_register(dev, data, hw_data, gate_base);

drivers/clk/clk-lan966x.c

299

return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data);

drivers/clk/clk-loongson1.c

251

struct clk_hw_onecell_data *hw_data)

drivers/clk/clk-loongson1.c

263

for (i = 0; i < hw_data->num; i++) {

drivers/clk/clk-loongson1.c

265

if (!hw_data->hws[i])

drivers/clk/clk-loongson1.c

269

ls1x_clk = to_ls1x_clk(hw_data->hws[i]);

drivers/clk/clk-loongson1.c

273

ret = of_clk_hw_register(np, hw_data->hws[i]);

drivers/clk/clk-loongson1.c

278

ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, hw_data);

drivers/clk/clk-loongson1.c

286

clk_hw_unregister(hw_data->hws[i]);

drivers/clk/clk-twl.c

145

const struct twl_clks_data *hw_data;

drivers/clk/clk-twl.c

152

hw_data = twl6032_clks;

drivers/clk/clk-twl.c

153

for (count = 0; hw_data[count].init.name; count++)

drivers/clk/clk-twl.c

168

cinfo[i].base = hw_data[i].base;

drivers/clk/clk-twl.c

171

cinfo[i].hw.init = &hw_data[i].init;

drivers/clk/clk-twl.c

176

hw_data[i].init.name);

drivers/clk/clk.c

4981

struct clk_hw_onecell_data *hw_data = data;

drivers/clk/clk.c

4984

if (idx >= hw_data->num) {

drivers/clk/clk.c

4989

return hw_data->hws[idx];

drivers/clk/imx/clk-imx8qxp-lpcg.c

165

struct clk_hw_onecell_data *hw_data = data;

drivers/clk/imx/clk-imx8qxp-lpcg.c

168

if (idx >= hw_data->num) {

drivers/clk/imx/clk-imx8qxp-lpcg.c

173

return hw_data->hws[idx];

drivers/clk/keystone/syscon-clk.c

117

struct clk_hw_onecell_data *hw_data;

drivers/clk/keystone/syscon-clk.c

148

hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, num_clks),

drivers/clk/keystone/syscon-clk.c

150

if (!hw_data)

drivers/clk/keystone/syscon-clk.c

153

hw_data->num = num_clks;

drivers/clk/keystone/syscon-clk.c

157

hw_data->hws[i] = ti_syscon_gate_clk_register(dev, regmap,

drivers/clk/keystone/syscon-clk.c

160

if (IS_ERR(hw_data->hws[i]))

drivers/clk/keystone/syscon-clk.c

167

hw_data->hws[0]);

drivers/clk/keystone/syscon-clk.c

168

return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data);

drivers/clk/microchip/clk-mpfs-ccc.c

181

data->hw_data.hws[out_hw->id] = &out_hw->divider.hw;

drivers/clk/microchip/clk-mpfs-ccc.c

219

data->hw_data.hws[pll_hw->id] = &pll_hw->hw;

drivers/clk/microchip/clk-mpfs-ccc.c

240

clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hw_data.hws, num_clks),

drivers/clk/microchip/clk-mpfs-ccc.c

254

clk_data->hw_data.num = num_clks;

drivers/clk/microchip/clk-mpfs-ccc.c

263

&clk_data->hw_data);

drivers/clk/microchip/clk-mpfs-ccc.c

39

struct clk_hw_onecell_data hw_data;

drivers/clk/microchip/clk-mpfs.c

195

data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw;

drivers/clk/microchip/clk-mpfs.c

243

data->hw_data.hws[msspll_out_hw->id] = &msspll_out_hw->output.hw;

drivers/clk/microchip/clk-mpfs.c

349

data->hw_data.hws[id] = &cfg_hw->hw;

drivers/clk/microchip/clk-mpfs.c

466

data->hw_data.hws[id] = &periph_hw->hw;

drivers/clk/microchip/clk-mpfs.c

519

clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL);

drivers/clk/microchip/clk-mpfs.c

530

clk_data->hw_data.num = num_clks;

drivers/clk/microchip/clk-mpfs.c

554

return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data);

drivers/clk/microchip/clk-mpfs.c

56

struct clk_hw_onecell_data hw_data;

drivers/clk/mvebu/armada-37xx-periph.c

58

struct clk_hw_onecell_data *hw_data;

drivers/clk/mvebu/armada-37xx-periph.c

750

driver_data->hw_data = devm_kzalloc(dev,

drivers/clk/mvebu/armada-37xx-periph.c

751

struct_size(driver_data->hw_data,

drivers/clk/mvebu/armada-37xx-periph.c

754

if (!driver_data->hw_data)

drivers/clk/mvebu/armada-37xx-periph.c

756

driver_data->hw_data->num = num_periph;

drivers/clk/mvebu/armada-37xx-periph.c

765

struct clk_hw **hw = &driver_data->hw_data->hws[i];

drivers/clk/mvebu/armada-37xx-periph.c

773

driver_data->hw_data);

drivers/clk/mvebu/armada-37xx-periph.c

776

clk_hw_unregister(driver_data->hw_data->hws[i]);

drivers/clk/mvebu/armada-37xx-periph.c

787

struct clk_hw_onecell_data *hw_data = data->hw_data;

drivers/clk/mvebu/armada-37xx-periph.c

792

for (i = 0; i < hw_data->num; i++)

drivers/clk/mvebu/armada-37xx-periph.c

793

clk_hw_unregister(hw_data->hws[i]);

drivers/clk/qcom/ipq-cmn-pll.c

327

struct clk_hw_onecell_data *hw_data;

drivers/clk/qcom/ipq-cmn-pll.c

342

hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, num_clks + 1),

drivers/clk/qcom/ipq-cmn-pll.c

344

if (!hw_data)

drivers/clk/qcom/ipq-cmn-pll.c

365

hw_data->hws[fixed_clk[i].id] = hw;

drivers/clk/qcom/ipq-cmn-pll.c

372

hw_data->hws[CMN_PLL_CLK] = cmn_pll_hw;

drivers/clk/qcom/ipq-cmn-pll.c

373

hw_data->num = num_clks + 1;

drivers/clk/qcom/ipq-cmn-pll.c

375

ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data);

drivers/clk/qcom/ipq-cmn-pll.c

379

platform_set_drvdata(pdev, hw_data);

drivers/clk/qcom/ipq-cmn-pll.c

385

clk_hw_unregister(hw_data->hws[fixed_clk[--i].id]);

drivers/clk/qcom/ipq-cmn-pll.c

431

struct clk_hw_onecell_data *hw_data = platform_get_drvdata(pdev);

drivers/clk/qcom/ipq-cmn-pll.c

438

for (i = 0; i < hw_data->num; i++) {

drivers/clk/qcom/ipq-cmn-pll.c

440

clk_hw_unregister(hw_data->hws[i]);

drivers/clk/renesas/rzg2l-cpg.c

111

struct clk_hw_data hw_data;

drivers/clk/renesas/rzg2l-cpg.c

115

#define to_sd_mux_hw_data(_hw) container_of(_hw, struct sd_mux_hw_data, hw_data)

drivers/clk/renesas/rzg2l-cpg.c

126

struct clk_hw_data hw_data;

drivers/clk/renesas/rzg2l-cpg.c

133

#define to_div_hw_data(_hw) container_of(_hw, struct div_hw_data, hw_data)

drivers/clk/renesas/rzg2l-cpg.c

410

div_hw_data->hw_data.priv = priv;

drivers/clk/renesas/rzg2l-cpg.c

411

div_hw_data->hw_data.conf = core->conf;

drivers/clk/renesas/rzg2l-cpg.c

412

div_hw_data->hw_data.sconf = core->sconf;

drivers/clk/renesas/rzg2l-cpg.c

418

clk_hw = &div_hw_data->hw_data.hw;

drivers/clk/renesas/rzg2l-cpg.c

554

sd_mux_hw_data->hw_data.priv = priv;

drivers/clk/renesas/rzg2l-cpg.c

555

sd_mux_hw_data->hw_data.conf = core->conf;

drivers/clk/renesas/rzg2l-cpg.c

556

sd_mux_hw_data->hw_data.sconf = core->sconf;

drivers/clk/renesas/rzg2l-cpg.c

565

clk_hw = &sd_mux_hw_data->hw_data.hw;

drivers/clk/uniphier/clk-uniphier-core.c

44

struct clk_hw_onecell_data *hw_data;

drivers/clk/uniphier/clk-uniphier-core.c

66

hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, clk_num),

drivers/clk/uniphier/clk-uniphier-core.c

68

if (!hw_data)

drivers/clk/uniphier/clk-uniphier-core.c

71

hw_data->num = clk_num;

drivers/clk/uniphier/clk-uniphier-core.c

75

hw_data->hws[clk_num] = ERR_PTR(-EINVAL);

drivers/clk/uniphier/clk-uniphier-core.c

86

hw_data->hws[p->idx] = hw;

drivers/clk/uniphier/clk-uniphier-core.c

90

hw_data);

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

151

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

157

ae_mask = get_ae_mask(hw_data);

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

167

hw_data->ae_mask = ae_mask & config_ae_mask;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

412

void adf_init_hw_data_420xx(struct adf_hw_device_data *hw_data, u32 dev_id)

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

414

hw_data->dev_class = &adf_420xx_class;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

415

hw_data->instance_id = adf_420xx_class.instances++;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

416

hw_data->num_banks = ADF_GEN4_ETR_MAX_BANKS;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

417

hw_data->num_banks_per_vf = ADF_GEN4_NUM_BANKS_PER_VF;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

418

hw_data->num_rings_per_bank = ADF_GEN4_NUM_RINGS_PER_BANK;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

419

hw_data->num_accel = ADF_GEN4_MAX_ACCELERATORS;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

420

hw_data->num_engines = ADF_420XX_MAX_ACCELENGINES;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

421

hw_data->num_logical_accel = 1;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

422

hw_data->tx_rx_gap = ADF_GEN4_RX_RINGS_OFFSET;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

423

hw_data->tx_rings_mask = ADF_GEN4_TX_RINGS_MASK;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

424

hw_data->ring_to_svc_map = ADF_GEN4_DEFAULT_RING_TO_SRV_MAP;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

425

hw_data->alloc_irq = adf_isr_resource_alloc;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

426

hw_data->free_irq = adf_isr_resource_free;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

427

hw_data->enable_error_correction = adf_gen4_enable_error_correction;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

428

hw_data->get_accel_mask = adf_gen4_get_accel_mask;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

429

hw_data->get_ae_mask = get_ae_mask;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

430

hw_data->get_num_accels = adf_gen4_get_num_accels;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

431

hw_data->get_num_aes = adf_gen4_get_num_aes;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

432

hw_data->get_sram_bar_id = adf_gen4_get_sram_bar_id;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

433

hw_data->get_etr_bar_id = adf_gen4_get_etr_bar_id;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

434

hw_data->get_misc_bar_id = adf_gen4_get_misc_bar_id;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

435

hw_data->get_arb_info = adf_gen4_get_arb_info;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

436

hw_data->get_admin_info = adf_gen4_get_admin_info;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

437

hw_data->get_accel_cap = get_accel_cap;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

438

hw_data->get_sku = adf_gen4_get_sku;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

439

hw_data->init_admin_comms = adf_init_admin_comms;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

440

hw_data->exit_admin_comms = adf_exit_admin_comms;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

441

hw_data->send_admin_init = adf_send_admin_init;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

442

hw_data->init_arb = adf_init_arb;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

443

hw_data->exit_arb = adf_exit_arb;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

444

hw_data->get_arb_mapping = adf_get_arbiter_mapping;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

445

hw_data->enable_ints = adf_gen4_enable_ints;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

446

hw_data->init_device = adf_gen4_init_device;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

447

hw_data->reset_device = adf_reset_flr;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

448

hw_data->admin_ae_mask = ADF_420XX_ADMIN_AE_MASK;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

449

hw_data->num_rps = ADF_GEN4_MAX_RPS;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

450

hw_data->fw_name = ADF_420XX_FW;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

451

hw_data->fw_mmp_name = ADF_420XX_MMP;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

452

hw_data->uof_get_name = uof_get_name_420xx;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

453

hw_data->uof_get_num_objs = uof_get_num_objs;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

454

hw_data->uof_get_obj_type = uof_get_obj_type;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

455

hw_data->uof_get_ae_mask = uof_get_ae_mask;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

456

hw_data->get_rp_group = get_rp_group;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

457

hw_data->get_ena_thd_mask = get_ena_thd_mask;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

458

hw_data->set_msix_rttable = adf_gen4_set_msix_default_rttable;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

459

hw_data->set_ssm_wdtimer = adf_gen4_set_ssm_wdtimer;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

460

hw_data->get_ring_to_svc_map = adf_gen4_get_ring_to_svc_map;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

461

hw_data->disable_iov = adf_disable_sriov;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

462

hw_data->ring_pair_reset = adf_gen4_ring_pair_reset;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

463

hw_data->bank_state_save = adf_bank_state_save;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

464

hw_data->bank_state_restore = adf_bank_state_restore;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

465

hw_data->enable_pm = adf_gen4_enable_pm;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

466

hw_data->handle_pm_interrupt = adf_gen4_handle_pm_interrupt;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

467

hw_data->dev_config = adf_gen4_dev_config;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

468

hw_data->start_timer = adf_timer_start;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

469

hw_data->stop_timer = adf_timer_stop;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

470

hw_data->get_hb_clock = adf_gen4_get_heartbeat_clock;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

471

hw_data->num_hb_ctrs = ADF_NUM_HB_CNT_PER_AE;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

472

hw_data->clock_frequency = ADF_420XX_AE_FREQ;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

473

hw_data->services_supported = adf_gen4_services_supported;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

474

hw_data->get_svc_slice_cnt = adf_gen4_get_svc_slice_cnt;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

476

adf_gen4_set_err_mask(&hw_data->dev_err_mask);

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

477

adf_gen4_init_hw_csr_ops(&hw_data->csr_ops);

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

478

adf_gen4_init_pf_pfvf_ops(&hw_data->pfvf_ops);

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

479

adf_gen4_init_dc_ops(&hw_data->dc_ops);

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

480

adf_gen4_init_ras_ops(&hw_data->ras_ops);

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

481

adf_gen4_init_tl_data(&hw_data->tl_data);

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

482

adf_gen4_init_vf_mig_ops(&hw_data->vfmig_ops);

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

483

adf_init_rl_data(&hw_data->rl_data);

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

486

void adf_clean_hw_data_420xx(struct adf_hw_device_data *hw_data)

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

488

hw_data->dev_class->instances--;

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.h

52

void adf_init_hw_data_420xx(struct adf_hw_device_data *hw_data, u32 dev_id);

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.h

53

void adf_clean_hw_data_420xx(struct adf_hw_device_data *hw_data);

drivers/crypto/intel/qat/qat_420xx/adf_drv.c

122

hw_data->accel_capabilities_mask = hw_data->get_accel_cap(accel_dev);

drivers/crypto/intel/qat/qat_420xx/adf_drv.c

123

if (!hw_data->accel_capabilities_mask) {

drivers/crypto/intel/qat/qat_420xx/adf_drv.c

37

struct adf_hw_device_data *hw_data;

drivers/crypto/intel/qat/qat_420xx/adf_drv.c

72

hw_data = devm_kzalloc(&pdev->dev, sizeof(*hw_data), GFP_KERNEL);

drivers/crypto/intel/qat/qat_420xx/adf_drv.c

73

if (!hw_data) {

drivers/crypto/intel/qat/qat_420xx/adf_drv.c

78

accel_dev->hw_device = hw_data;

drivers/crypto/intel/qat/qat_420xx/adf_drv.c

82

pci_read_config_dword(pdev, ADF_GEN4_FUSECTL4_OFFSET, &hw_data->fuses[ADF_FUSECTL4]);

drivers/crypto/intel/qat/qat_420xx/adf_drv.c

85

hw_data->accel_mask = hw_data->get_accel_mask(hw_data);

drivers/crypto/intel/qat/qat_420xx/adf_drv.c

86

hw_data->ae_mask = hw_data->get_ae_mask(hw_data);

drivers/crypto/intel/qat/qat_420xx/adf_drv.c

87

accel_pci_dev->sku = hw_data->get_sku(hw_data);

drivers/crypto/intel/qat/qat_420xx/adf_drv.c

89

if (!hw_data->accel_mask || !hw_data->ae_mask ||

drivers/crypto/intel/qat/qat_420xx/adf_drv.c

90

(~hw_data->ae_mask & 0x01)) {

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

387

void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 dev_id)

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

389

hw_data->dev_class = &adf_4xxx_class;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

390

hw_data->instance_id = adf_4xxx_class.instances++;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

391

hw_data->num_banks = ADF_GEN4_ETR_MAX_BANKS;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

392

hw_data->num_banks_per_vf = ADF_GEN4_NUM_BANKS_PER_VF;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

393

hw_data->num_rings_per_bank = ADF_GEN4_NUM_RINGS_PER_BANK;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

394

hw_data->num_accel = ADF_GEN4_MAX_ACCELERATORS;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

395

hw_data->num_engines = ADF_4XXX_MAX_ACCELENGINES;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

396

hw_data->num_logical_accel = 1;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

397

hw_data->tx_rx_gap = ADF_GEN4_RX_RINGS_OFFSET;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

398

hw_data->tx_rings_mask = ADF_GEN4_TX_RINGS_MASK;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

399

hw_data->ring_to_svc_map = ADF_GEN4_DEFAULT_RING_TO_SRV_MAP;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

400

hw_data->alloc_irq = adf_isr_resource_alloc;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

401

hw_data->free_irq = adf_isr_resource_free;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

402

hw_data->enable_error_correction = adf_gen4_enable_error_correction;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

403

hw_data->get_accel_mask = adf_gen4_get_accel_mask;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

404

hw_data->get_ae_mask = get_ae_mask;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

405

hw_data->get_num_accels = adf_gen4_get_num_accels;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

406

hw_data->get_num_aes = adf_gen4_get_num_aes;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

407

hw_data->get_sram_bar_id = adf_gen4_get_sram_bar_id;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

408

hw_data->get_etr_bar_id = adf_gen4_get_etr_bar_id;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

409

hw_data->get_misc_bar_id = adf_gen4_get_misc_bar_id;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

410

hw_data->get_arb_info = adf_gen4_get_arb_info;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

411

hw_data->get_admin_info = adf_gen4_get_admin_info;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

412

hw_data->get_accel_cap = get_accel_cap;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

413

hw_data->get_sku = adf_gen4_get_sku;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

414

hw_data->init_admin_comms = adf_init_admin_comms;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

415

hw_data->exit_admin_comms = adf_exit_admin_comms;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

416

hw_data->send_admin_init = adf_send_admin_init;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

417

hw_data->init_arb = adf_init_arb;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

418

hw_data->exit_arb = adf_exit_arb;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

419

hw_data->get_arb_mapping = adf_get_arbiter_mapping;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

420

hw_data->enable_ints = adf_gen4_enable_ints;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

421

hw_data->init_device = adf_gen4_init_device;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

422

hw_data->reset_device = adf_reset_flr;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

423

hw_data->admin_ae_mask = ADF_4XXX_ADMIN_AE_MASK;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

424

hw_data->num_rps = ADF_GEN4_MAX_RPS;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

427

hw_data->fw_name = ADF_402XX_FW;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

428

hw_data->fw_mmp_name = ADF_402XX_MMP;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

429

hw_data->uof_get_name = uof_get_name_402xx;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

430

hw_data->get_ena_thd_mask = get_ena_thd_mask;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

433

hw_data->fw_name = ADF_4XXX_FW;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

434

hw_data->fw_mmp_name = ADF_4XXX_MMP;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

435

hw_data->uof_get_name = uof_get_name_4xxx;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

436

hw_data->get_ena_thd_mask = get_ena_thd_mask_401xx;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

439

hw_data->fw_name = ADF_4XXX_FW;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

440

hw_data->fw_mmp_name = ADF_4XXX_MMP;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

441

hw_data->uof_get_name = uof_get_name_4xxx;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

442

hw_data->get_ena_thd_mask = get_ena_thd_mask;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

445

hw_data->uof_get_num_objs = uof_get_num_objs;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

446

hw_data->uof_get_obj_type = uof_get_obj_type;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

447

hw_data->uof_get_ae_mask = uof_get_ae_mask;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

448

hw_data->get_rp_group = get_rp_group;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

449

hw_data->set_msix_rttable = adf_gen4_set_msix_default_rttable;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

450

hw_data->set_ssm_wdtimer = adf_gen4_set_ssm_wdtimer;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

451

hw_data->get_ring_to_svc_map = adf_gen4_get_ring_to_svc_map;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

452

hw_data->disable_iov = adf_disable_sriov;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

453

hw_data->ring_pair_reset = adf_gen4_ring_pair_reset;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

454

hw_data->bank_state_save = adf_bank_state_save;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

455

hw_data->bank_state_restore = adf_bank_state_restore;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

456

hw_data->enable_pm = adf_gen4_enable_pm;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

457

hw_data->handle_pm_interrupt = adf_gen4_handle_pm_interrupt;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

458

hw_data->dev_config = adf_gen4_dev_config;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

459

hw_data->start_timer = adf_timer_start;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

460

hw_data->stop_timer = adf_timer_stop;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

461

hw_data->get_hb_clock = adf_gen4_get_heartbeat_clock;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

462

hw_data->num_hb_ctrs = ADF_NUM_HB_CNT_PER_AE;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

463

hw_data->clock_frequency = ADF_4XXX_AE_FREQ;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

464

hw_data->services_supported = adf_gen4_services_supported;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

465

hw_data->get_svc_slice_cnt = adf_gen4_get_svc_slice_cnt;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

467

adf_gen4_set_err_mask(&hw_data->dev_err_mask);

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

468

adf_gen4_init_hw_csr_ops(&hw_data->csr_ops);

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

469

adf_gen4_init_pf_pfvf_ops(&hw_data->pfvf_ops);

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

470

adf_gen4_init_dc_ops(&hw_data->dc_ops);

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

471

adf_gen4_init_ras_ops(&hw_data->ras_ops);

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

472

adf_gen4_init_tl_data(&hw_data->tl_data);

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

473

adf_gen4_init_vf_mig_ops(&hw_data->vfmig_ops);

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

474

adf_init_rl_data(&hw_data->rl_data);

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

477

void adf_clean_hw_data_4xxx(struct adf_hw_device_data *hw_data)

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

479

hw_data->dev_class->instances--;

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.h

59

void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 dev_id);

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.h

60

void adf_clean_hw_data_4xxx(struct adf_hw_device_data *hw_data);

drivers/crypto/intel/qat/qat_4xxx/adf_drv.c

124

hw_data->accel_capabilities_mask = hw_data->get_accel_cap(accel_dev);

drivers/crypto/intel/qat/qat_4xxx/adf_drv.c

125

if (!hw_data->accel_capabilities_mask) {

drivers/crypto/intel/qat/qat_4xxx/adf_drv.c

39

struct adf_hw_device_data *hw_data;

drivers/crypto/intel/qat/qat_4xxx/adf_drv.c

74

hw_data = devm_kzalloc(&pdev->dev, sizeof(*hw_data), GFP_KERNEL);

drivers/crypto/intel/qat/qat_4xxx/adf_drv.c

75

if (!hw_data) {

drivers/crypto/intel/qat/qat_4xxx/adf_drv.c

80

accel_dev->hw_device = hw_data;

drivers/crypto/intel/qat/qat_4xxx/adf_drv.c

84

pci_read_config_dword(pdev, ADF_GEN4_FUSECTL4_OFFSET, &hw_data->fuses[ADF_FUSECTL4]);

drivers/crypto/intel/qat/qat_4xxx/adf_drv.c

87

hw_data->accel_mask = hw_data->get_accel_mask(hw_data);

drivers/crypto/intel/qat/qat_4xxx/adf_drv.c

88

hw_data->ae_mask = hw_data->get_ae_mask(hw_data);

drivers/crypto/intel/qat/qat_4xxx/adf_drv.c

89

accel_pci_dev->sku = hw_data->get_sku(hw_data);

drivers/crypto/intel/qat/qat_4xxx/adf_drv.c

91

if (!hw_data->accel_mask || !hw_data->ae_mask ||

drivers/crypto/intel/qat/qat_4xxx/adf_drv.c

92

(~hw_data->ae_mask & 0x01)) {

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

444

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

448

if (bank_number >= hw_data->num_banks)

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

515

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

516

u32 *thd2arb_map = hw_data->thd_to_arb_map;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

519

for (i = 0; i < hw_data->num_engines; i++) {

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

622

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

626

for (i = 0; i < hw_data->num_banks; i++) {

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

876

void adf_init_hw_data_6xxx(struct adf_hw_device_data *hw_data)

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

878

hw_data->dev_class = &adf_6xxx_class;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

879

hw_data->instance_id = adf_6xxx_class.instances++;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

880

hw_data->num_banks = ADF_GEN6_ETR_MAX_BANKS;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

881

hw_data->num_banks_per_vf = ADF_GEN6_NUM_BANKS_PER_VF;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

882

hw_data->num_rings_per_bank = ADF_GEN6_NUM_RINGS_PER_BANK;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

883

hw_data->num_accel = ADF_GEN6_MAX_ACCELERATORS;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

884

hw_data->num_engines = ADF_6XXX_MAX_ACCELENGINES;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

885

hw_data->num_logical_accel = 1;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

886

hw_data->tx_rx_gap = ADF_GEN6_RX_RINGS_OFFSET;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

887

hw_data->tx_rings_mask = ADF_GEN6_TX_RINGS_MASK;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

888

hw_data->ring_to_svc_map = 0;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

889

hw_data->alloc_irq = adf_isr_resource_alloc;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

890

hw_data->free_irq = adf_isr_resource_free;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

891

hw_data->enable_error_correction = enable_error_correction;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

892

hw_data->get_accel_mask = get_accel_mask;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

893

hw_data->get_ae_mask = get_ae_mask;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

894

hw_data->get_num_accels = get_num_accels;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

895

hw_data->get_num_aes = get_num_aes;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

896

hw_data->get_sram_bar_id = get_sram_bar_id;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

897

hw_data->get_etr_bar_id = get_etr_bar_id;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

898

hw_data->get_misc_bar_id = get_misc_bar_id;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

899

hw_data->get_arb_info = get_arb_info;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

900

hw_data->get_admin_info = get_admin_info;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

901

hw_data->get_accel_cap = get_accel_cap;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

902

hw_data->get_sku = get_sku;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

903

hw_data->init_admin_comms = adf_init_admin_comms;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

904

hw_data->exit_admin_comms = adf_exit_admin_comms;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

905

hw_data->send_admin_init = adf_send_admin_init;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

906

hw_data->init_arb = adf_init_arb;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

907

hw_data->exit_arb = adf_exit_arb;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

908

hw_data->get_arb_mapping = adf_get_arbiter_mapping;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

909

hw_data->enable_ints = enable_ints;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

910

hw_data->reset_device = adf_reset_flr;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

911

hw_data->admin_ae_mask = ADF_6XXX_ADMIN_AE_MASK;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

912

hw_data->fw_name = ADF_6XXX_FW;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

913

hw_data->fw_mmp_name = ADF_6XXX_MMP;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

914

hw_data->uof_get_name = uof_get_name_6xxx;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

915

hw_data->uof_get_num_objs = uof_get_num_objs;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

916

hw_data->uof_get_obj_type = uof_get_obj_type;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

917

hw_data->uof_get_ae_mask = uof_get_ae_mask;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

918

hw_data->set_msix_rttable = set_msix_default_rttable;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

919

hw_data->set_ssm_wdtimer = set_ssm_wdtimer;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

920

hw_data->get_ring_to_svc_map = get_ring_to_svc_map;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

921

hw_data->disable_iov = adf_disable_sriov;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

922

hw_data->ring_pair_reset = ring_pair_reset;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

923

hw_data->dev_config = dev_config;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

924

hw_data->bank_state_save = adf_bank_state_save;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

925

hw_data->bank_state_restore = adf_bank_state_restore;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

926

hw_data->get_hb_clock = get_heartbeat_clock;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

927

hw_data->num_hb_ctrs = ADF_NUM_HB_CNT_PER_AE;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

928

hw_data->start_timer = adf_timer_start;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

929

hw_data->stop_timer = adf_timer_stop;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

930

hw_data->init_device = adf_init_device;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

931

hw_data->enable_pm = enable_pm;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

932

hw_data->services_supported = services_supported;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

933

hw_data->num_rps = ADF_GEN6_ETR_MAX_BANKS;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

934

hw_data->clock_frequency = ADF_6XXX_AE_FREQ;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

935

hw_data->get_svc_slice_cnt = adf_gen6_get_svc_slice_cnt;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

937

adf_gen6_init_hw_csr_ops(&hw_data->csr_ops);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

938

adf_gen6_init_pf_pfvf_ops(&hw_data->pfvf_ops);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

939

adf_gen6_init_dc_ops(&hw_data->dc_ops);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

940

adf_gen6_init_vf_mig_ops(&hw_data->vfmig_ops);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

941

adf_gen6_init_ras_ops(&hw_data->ras_ops);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

942

adf_gen6_init_tl_data(&hw_data->tl_data);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

943

adf_gen6_init_rl_data(&hw_data->rl_data);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

946

void adf_clean_hw_data_6xxx(struct adf_hw_device_data *hw_data)

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

948

if (hw_data->dev_class->instances)

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

949

hw_data->dev_class->instances--;

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.h

165

void adf_init_hw_data_6xxx(struct adf_hw_device_data *hw_data);

drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.h

166

void adf_clean_hw_data_6xxx(struct adf_hw_device_data *hw_data);

drivers/crypto/intel/qat/qat_6xxx/adf_drv.c

110

accel_dev->hw_device = hw_data;

drivers/crypto/intel/qat/qat_6xxx/adf_drv.c

118

hw_data->accel_mask = hw_data->get_accel_mask(hw_data);

drivers/crypto/intel/qat/qat_6xxx/adf_drv.c

119

hw_data->ae_mask = hw_data->get_ae_mask(hw_data);

drivers/crypto/intel/qat/qat_6xxx/adf_drv.c

120

accel_pci_dev->sku = hw_data->get_sku(hw_data);

drivers/crypto/intel/qat/qat_6xxx/adf_drv.c

123

if (!hw_data->accel_mask || !hw_data->ae_mask ||

drivers/crypto/intel/qat/qat_6xxx/adf_drv.c

124

(~hw_data->ae_mask & ADF_GEN6_ACCELERATORS_MASK)) {

drivers/crypto/intel/qat/qat_6xxx/adf_drv.c

148

hw_data->accel_capabilities_mask = hw_data->get_accel_cap(accel_dev);

drivers/crypto/intel/qat/qat_6xxx/adf_drv.c

149

if (!hw_data->accel_capabilities_mask) {

drivers/crypto/intel/qat/qat_6xxx/adf_drv.c

59

struct adf_hw_device_data *hw_data;

drivers/crypto/intel/qat/qat_6xxx/adf_drv.c

85

hw_data = devm_kzalloc(dev, sizeof(*hw_data), GFP_KERNEL);

drivers/crypto/intel/qat/qat_6xxx/adf_drv.c

86

if (!hw_data)

drivers/crypto/intel/qat/qat_6xxx/adf_drv.c

90

pci_read_config_dword(pdev, ADF_GEN6_FUSECTL4_OFFSET, &hw_data->fuses[ADF_FUSECTL4]);

drivers/crypto/intel/qat/qat_6xxx/adf_drv.c

91

pci_read_config_dword(pdev, ADF_GEN6_FUSECTL0_OFFSET, &hw_data->fuses[ADF_FUSECTL0]);

drivers/crypto/intel/qat/qat_6xxx/adf_drv.c

92

pci_read_config_dword(pdev, ADF_GEN6_FUSECTL1_OFFSET, &hw_data->fuses[ADF_FUSECTL1]);

drivers/crypto/intel/qat/qat_6xxx/adf_drv.c

94

if (!(hw_data->fuses[ADF_FUSECTL1] & ICP_ACCEL_GEN6_MASK_WCP_WAT_SLICE))

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

114

void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data)

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

116

hw_data->dev_class = &c3xxx_class;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

117

hw_data->instance_id = c3xxx_class.instances++;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

118

hw_data->num_banks = ADF_C3XXX_ETR_MAX_BANKS;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

119

hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

120

hw_data->num_accel = ADF_C3XXX_MAX_ACCELERATORS;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

121

hw_data->num_logical_accel = 1;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

122

hw_data->num_engines = ADF_C3XXX_MAX_ACCELENGINES;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

123

hw_data->tx_rx_gap = ADF_GEN2_RX_RINGS_OFFSET;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

124

hw_data->tx_rings_mask = ADF_GEN2_TX_RINGS_MASK;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

125

hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

126

hw_data->alloc_irq = adf_isr_resource_alloc;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

127

hw_data->free_irq = adf_isr_resource_free;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

128

hw_data->enable_error_correction = adf_gen2_enable_error_correction;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

129

hw_data->get_accel_mask = get_accel_mask;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

130

hw_data->get_ae_mask = get_ae_mask;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

131

hw_data->get_accel_cap = adf_gen2_get_accel_cap;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

132

hw_data->get_num_accels = adf_gen2_get_num_accels;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

133

hw_data->get_num_aes = adf_gen2_get_num_aes;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

134

hw_data->get_sram_bar_id = get_sram_bar_id;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

135

hw_data->get_etr_bar_id = get_etr_bar_id;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

136

hw_data->get_misc_bar_id = get_misc_bar_id;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

137

hw_data->get_admin_info = adf_gen2_get_admin_info;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

138

hw_data->get_arb_info = adf_gen2_get_arb_info;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

139

hw_data->get_sku = get_sku;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

140

hw_data->fw_name = ADF_C3XXX_FW;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

141

hw_data->fw_mmp_name = ADF_C3XXX_MMP;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

142

hw_data->init_admin_comms = adf_init_admin_comms;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

143

hw_data->exit_admin_comms = adf_exit_admin_comms;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

144

hw_data->configure_iov_threads = configure_iov_threads;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

145

hw_data->send_admin_init = adf_send_admin_init;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

146

hw_data->init_arb = adf_init_arb;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

147

hw_data->exit_arb = adf_exit_arb;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

148

hw_data->get_arb_mapping = adf_get_arbiter_mapping;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

149

hw_data->enable_ints = adf_gen2_enable_ints;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

150

hw_data->reset_device = adf_reset_flr;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

151

hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

152

hw_data->disable_iov = adf_disable_sriov;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

153

hw_data->dev_config = adf_gen2_dev_config;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

154

hw_data->measure_clock = measure_clock;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

155

hw_data->get_hb_clock = get_ts_clock;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

156

hw_data->num_hb_ctrs = ADF_NUM_HB_CNT_PER_AE;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

157

hw_data->check_hb_ctrs = adf_heartbeat_check_ctrs;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

159

adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

160

adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

161

adf_gen2_init_dc_ops(&hw_data->dc_ops);

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

164

void adf_clean_hw_data_c3xxx(struct adf_hw_device_data *hw_data)

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

166

hw_data->dev_class->instances--;

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.h

33

void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data);

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.h

34

void adf_clean_hw_data_c3xxx(struct adf_hw_device_data *hw_data);

drivers/crypto/intel/qat/qat_c3xxx/adf_drv.c

100

hw_data = kzalloc_node(sizeof(*hw_data), GFP_KERNEL,

drivers/crypto/intel/qat/qat_c3xxx/adf_drv.c

102

if (!hw_data) {

drivers/crypto/intel/qat/qat_c3xxx/adf_drv.c

107

accel_dev->hw_device = hw_data;

drivers/crypto/intel/qat/qat_c3xxx/adf_drv.c

111

&hw_data->fuses[ADF_FUSECTL0]);

drivers/crypto/intel/qat/qat_c3xxx/adf_drv.c

113

&hw_data->straps);

drivers/crypto/intel/qat/qat_c3xxx/adf_drv.c

116

hw_data->accel_mask = hw_data->get_accel_mask(hw_data);

drivers/crypto/intel/qat/qat_c3xxx/adf_drv.c

117

hw_data->ae_mask = hw_data->get_ae_mask(hw_data);

drivers/crypto/intel/qat/qat_c3xxx/adf_drv.c

118

accel_pci_dev->sku = hw_data->get_sku(hw_data);

drivers/crypto/intel/qat/qat_c3xxx/adf_drv.c

120

if (!hw_data->accel_mask || !hw_data->ae_mask ||

drivers/crypto/intel/qat/qat_c3xxx/adf_drv.c

121

((~hw_data->ae_mask) & 0x01)) {

drivers/crypto/intel/qat/qat_c3xxx/adf_drv.c

151

hw_data->accel_capabilities_mask = hw_data->get_accel_cap(accel_dev);

drivers/crypto/intel/qat/qat_c3xxx/adf_drv.c

60

struct adf_hw_device_data *hw_data;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

100

adf_devmgr_update_class_index(hw_data);

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

61

void adf_init_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data)

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

63

hw_data->dev_class = &c3xxxiov_class;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

64

hw_data->num_banks = ADF_C3XXXIOV_ETR_MAX_BANKS;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

65

hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

66

hw_data->num_accel = ADF_C3XXXIOV_MAX_ACCELERATORS;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

67

hw_data->num_logical_accel = 1;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

68

hw_data->num_engines = ADF_C3XXXIOV_MAX_ACCELENGINES;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

69

hw_data->tx_rx_gap = ADF_C3XXXIOV_RX_RINGS_OFFSET;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

70

hw_data->tx_rings_mask = ADF_C3XXXIOV_TX_RINGS_MASK;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

71

hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

72

hw_data->alloc_irq = adf_vf_isr_resource_alloc;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

73

hw_data->free_irq = adf_vf_isr_resource_free;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

74

hw_data->enable_error_correction = adf_vf_void_noop;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

75

hw_data->init_admin_comms = adf_vf_int_noop;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

76

hw_data->exit_admin_comms = adf_vf_void_noop;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

77

hw_data->send_admin_init = adf_vf2pf_notify_init;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

78

hw_data->init_arb = adf_vf_int_noop;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

79

hw_data->exit_arb = adf_vf_void_noop;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

80

hw_data->disable_iov = adf_vf2pf_notify_shutdown;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

81

hw_data->get_accel_mask = get_accel_mask;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

82

hw_data->get_ae_mask = get_ae_mask;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

83

hw_data->get_num_accels = get_num_accels;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

84

hw_data->get_num_aes = get_num_aes;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

85

hw_data->get_etr_bar_id = get_etr_bar_id;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

86

hw_data->get_misc_bar_id = get_misc_bar_id;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

87

hw_data->get_sku = get_sku;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

88

hw_data->enable_ints = adf_vf_void_noop;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

89

hw_data->dev_class->instances++;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

90

hw_data->dev_config = adf_gen2_dev_config;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

91

adf_devmgr_update_class_index(hw_data);

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

92

adf_gen2_init_vf_pfvf_ops(&hw_data->pfvf_ops);

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

93

adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

94

adf_gen2_init_dc_ops(&hw_data->dc_ops);

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

97

void adf_clean_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data)

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

99

hw_data->dev_class->instances--;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.h

16

void adf_init_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data);

drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.h

17

void adf_clean_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data);

drivers/crypto/intel/qat/qat_c3xxxvf/adf_drv.c

112

hw_data = kzalloc_node(sizeof(*hw_data), GFP_KERNEL,

drivers/crypto/intel/qat/qat_c3xxxvf/adf_drv.c

114

if (!hw_data) {

drivers/crypto/intel/qat/qat_c3xxxvf/adf_drv.c

118

accel_dev->hw_device = hw_data;

drivers/crypto/intel/qat/qat_c3xxxvf/adf_drv.c

122

hw_data->accel_mask = hw_data->get_accel_mask(hw_data);

drivers/crypto/intel/qat/qat_c3xxxvf/adf_drv.c

123

hw_data->ae_mask = hw_data->get_ae_mask(hw_data);

drivers/crypto/intel/qat/qat_c3xxxvf/adf_drv.c

124

accel_pci_dev->sku = hw_data->get_sku(hw_data);

drivers/crypto/intel/qat/qat_c3xxxvf/adf_drv.c

79

struct adf_hw_device_data *hw_data;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

116

void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data)

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

118

hw_data->dev_class = &c62x_class;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

119

hw_data->instance_id = c62x_class.instances++;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

120

hw_data->num_banks = ADF_C62X_ETR_MAX_BANKS;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

121

hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

122

hw_data->num_accel = ADF_C62X_MAX_ACCELERATORS;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

123

hw_data->num_logical_accel = 1;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

124

hw_data->num_engines = ADF_C62X_MAX_ACCELENGINES;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

125

hw_data->tx_rx_gap = ADF_GEN2_RX_RINGS_OFFSET;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

126

hw_data->tx_rings_mask = ADF_GEN2_TX_RINGS_MASK;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

127

hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

128

hw_data->alloc_irq = adf_isr_resource_alloc;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

129

hw_data->free_irq = adf_isr_resource_free;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

130

hw_data->enable_error_correction = adf_gen2_enable_error_correction;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

131

hw_data->get_accel_mask = get_accel_mask;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

132

hw_data->get_ae_mask = get_ae_mask;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

133

hw_data->get_accel_cap = adf_gen2_get_accel_cap;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

134

hw_data->get_num_accels = adf_gen2_get_num_accels;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

135

hw_data->get_num_aes = adf_gen2_get_num_aes;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

136

hw_data->get_sram_bar_id = get_sram_bar_id;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

137

hw_data->get_etr_bar_id = get_etr_bar_id;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

138

hw_data->get_misc_bar_id = get_misc_bar_id;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

139

hw_data->get_admin_info = adf_gen2_get_admin_info;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

140

hw_data->get_arb_info = adf_gen2_get_arb_info;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

141

hw_data->get_sku = get_sku;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

142

hw_data->fw_name = ADF_C62X_FW;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

143

hw_data->fw_mmp_name = ADF_C62X_MMP;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

144

hw_data->init_admin_comms = adf_init_admin_comms;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

145

hw_data->exit_admin_comms = adf_exit_admin_comms;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

146

hw_data->configure_iov_threads = configure_iov_threads;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

147

hw_data->send_admin_init = adf_send_admin_init;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

148

hw_data->init_arb = adf_init_arb;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

149

hw_data->exit_arb = adf_exit_arb;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

150

hw_data->get_arb_mapping = adf_get_arbiter_mapping;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

151

hw_data->enable_ints = adf_gen2_enable_ints;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

152

hw_data->reset_device = adf_reset_flr;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

153

hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

154

hw_data->disable_iov = adf_disable_sriov;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

155

hw_data->dev_config = adf_gen2_dev_config;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

156

hw_data->measure_clock = measure_clock;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

157

hw_data->get_hb_clock = get_ts_clock;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

158

hw_data->num_hb_ctrs = ADF_NUM_HB_CNT_PER_AE;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

159

hw_data->check_hb_ctrs = adf_heartbeat_check_ctrs;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

161

adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

162

adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

163

adf_gen2_init_dc_ops(&hw_data->dc_ops);

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

166

void adf_clean_hw_data_c62x(struct adf_hw_device_data *hw_data)

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

168

hw_data->dev_class->instances--;

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.h

33

void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data);

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.h

34

void adf_clean_hw_data_c62x(struct adf_hw_device_data *hw_data);

drivers/crypto/intel/qat/qat_c62x/adf_drv.c

100

hw_data = kzalloc_node(sizeof(*hw_data), GFP_KERNEL,

drivers/crypto/intel/qat/qat_c62x/adf_drv.c

102

if (!hw_data) {

drivers/crypto/intel/qat/qat_c62x/adf_drv.c

107

accel_dev->hw_device = hw_data;

drivers/crypto/intel/qat/qat_c62x/adf_drv.c

111

&hw_data->fuses[ADF_FUSECTL0]);

drivers/crypto/intel/qat/qat_c62x/adf_drv.c

113

&hw_data->straps);

drivers/crypto/intel/qat/qat_c62x/adf_drv.c

116

hw_data->accel_mask = hw_data->get_accel_mask(hw_data);

drivers/crypto/intel/qat/qat_c62x/adf_drv.c

117

hw_data->ae_mask = hw_data->get_ae_mask(hw_data);

drivers/crypto/intel/qat/qat_c62x/adf_drv.c

118

accel_pci_dev->sku = hw_data->get_sku(hw_data);

drivers/crypto/intel/qat/qat_c62x/adf_drv.c

120

if (!hw_data->accel_mask || !hw_data->ae_mask ||

drivers/crypto/intel/qat/qat_c62x/adf_drv.c

121

((~hw_data->ae_mask) & 0x01)) {

drivers/crypto/intel/qat/qat_c62x/adf_drv.c

151

hw_data->accel_capabilities_mask = hw_data->get_accel_cap(accel_dev);

drivers/crypto/intel/qat/qat_c62x/adf_drv.c

154

i = (hw_data->fuses[ADF_FUSECTL0] & ADF_DEVICE_FUSECTL_MASK) ? 1 : 0;

drivers/crypto/intel/qat/qat_c62x/adf_drv.c

60

struct adf_hw_device_data *hw_data;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

100

adf_devmgr_update_class_index(hw_data);

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

61

void adf_init_hw_data_c62xiov(struct adf_hw_device_data *hw_data)

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

63

hw_data->dev_class = &c62xiov_class;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

64

hw_data->num_banks = ADF_C62XIOV_ETR_MAX_BANKS;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

65

hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

66

hw_data->num_accel = ADF_C62XIOV_MAX_ACCELERATORS;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

67

hw_data->num_logical_accel = 1;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

68

hw_data->num_engines = ADF_C62XIOV_MAX_ACCELENGINES;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

69

hw_data->tx_rx_gap = ADF_C62XIOV_RX_RINGS_OFFSET;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

70

hw_data->tx_rings_mask = ADF_C62XIOV_TX_RINGS_MASK;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

71

hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

72

hw_data->alloc_irq = adf_vf_isr_resource_alloc;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

73

hw_data->free_irq = adf_vf_isr_resource_free;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

74

hw_data->enable_error_correction = adf_vf_void_noop;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

75

hw_data->init_admin_comms = adf_vf_int_noop;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

76

hw_data->exit_admin_comms = adf_vf_void_noop;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

77

hw_data->send_admin_init = adf_vf2pf_notify_init;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

78

hw_data->init_arb = adf_vf_int_noop;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

79

hw_data->exit_arb = adf_vf_void_noop;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

80

hw_data->disable_iov = adf_vf2pf_notify_shutdown;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

81

hw_data->get_accel_mask = get_accel_mask;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

82

hw_data->get_ae_mask = get_ae_mask;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

83

hw_data->get_num_accels = get_num_accels;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

84

hw_data->get_num_aes = get_num_aes;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

85

hw_data->get_etr_bar_id = get_etr_bar_id;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

86

hw_data->get_misc_bar_id = get_misc_bar_id;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

87

hw_data->get_sku = get_sku;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

88

hw_data->enable_ints = adf_vf_void_noop;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

89

hw_data->dev_class->instances++;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

90

hw_data->dev_config = adf_gen2_dev_config;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

91

adf_devmgr_update_class_index(hw_data);

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

92

adf_gen2_init_vf_pfvf_ops(&hw_data->pfvf_ops);

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

93

adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

94

adf_gen2_init_dc_ops(&hw_data->dc_ops);

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

97

void adf_clean_hw_data_c62xiov(struct adf_hw_device_data *hw_data)

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c

99

hw_data->dev_class->instances--;

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.h

16

void adf_init_hw_data_c62xiov(struct adf_hw_device_data *hw_data);

drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.h

17

void adf_clean_hw_data_c62xiov(struct adf_hw_device_data *hw_data);

drivers/crypto/intel/qat/qat_c62xvf/adf_drv.c

112

hw_data = kzalloc_node(sizeof(*hw_data), GFP_KERNEL,

drivers/crypto/intel/qat/qat_c62xvf/adf_drv.c

114

if (!hw_data) {

drivers/crypto/intel/qat/qat_c62xvf/adf_drv.c

118

accel_dev->hw_device = hw_data;

drivers/crypto/intel/qat/qat_c62xvf/adf_drv.c

122

hw_data->accel_mask = hw_data->get_accel_mask(hw_data);

drivers/crypto/intel/qat/qat_c62xvf/adf_drv.c

123

hw_data->ae_mask = hw_data->get_ae_mask(hw_data);

drivers/crypto/intel/qat/qat_c62xvf/adf_drv.c

124

accel_pci_dev->sku = hw_data->get_sku(hw_data);

drivers/crypto/intel/qat/qat_c62xvf/adf_drv.c

79

struct adf_hw_device_data *hw_data;

drivers/crypto/intel/qat/qat_common/adf_accel_engine.c

128

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_accel_engine.c

131

if (!hw_data->fw_name)

drivers/crypto/intel/qat/qat_common/adf_accel_engine.c

144

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_accel_engine.c

147

if (!hw_data->fw_name)

drivers/crypto/intel/qat/qat_common/adf_accel_engine.c

151

if (hw_data->ae_mask & (1 << ae)) {

drivers/crypto/intel/qat/qat_common/adf_admin.c

390

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_admin.c

411

adf_get_fw_capabilities(accel_dev, &hw_data->fw_capabilities);

drivers/crypto/intel/qat/qat_common/adf_admin.c

437

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_admin.c

440

u32 ae_mask = hw_data->admin_ae_mask;

drivers/crypto/intel/qat/qat_common/adf_admin.c

457

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_admin.c

460

u32 ae_mask = hw_data->admin_ae_mask;

drivers/crypto/intel/qat/qat_common/adf_admin.c

529

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_admin.c

532

u32 ae_mask = hw_data->admin_ae_mask;

drivers/crypto/intel/qat/qat_common/adf_admin.c

542

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_admin.c

574

hw_data->get_admin_info(&admin_csrs_info);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

190

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

194

if (bank_number >= hw_data->num_banks || !state)

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

200

hw_data->num_rings_per_bank);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

220

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

225

if (bank_number >= hw_data->num_banks || !state)

drivers/crypto/intel/qat/qat_common/adf_bank_state.c

231

hw_data->num_rings_per_bank, hw_data->tx_rx_gap);

drivers/crypto/intel/qat/qat_common/adf_cfg_services.c

202

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_cfg_services.c

203

u8 rps_per_bundle = hw_data->num_banks_per_vf;

drivers/crypto/intel/qat/qat_common/adf_cfg_services.c

54

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_cfg_services.c

78

if (hw_data->services_supported && !hw_data->services_supported(mask))

drivers/crypto/intel/qat/qat_common/adf_cnv_dbgfs.c

174

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_cnv_dbgfs.c

191

ae_mask = hw_data->ae_mask & ~hw_data->admin_ae_mask;

drivers/crypto/intel/qat/qat_common/adf_common_drv.h

242

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_common_drv.h

245

pmisc = &GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)];

drivers/crypto/intel/qat/qat_common/adf_common_drv.h

252

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_common_drv.h

255

etr = &GET_BARS(accel_dev)[hw_data->get_etr_bar_id(hw_data)];

drivers/crypto/intel/qat/qat_common/adf_common_drv.h

262

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_common_drv.h

265

param = &GET_BARS(accel_dev)[hw_data->get_sram_bar_id(hw_data)];

drivers/crypto/intel/qat/qat_common/adf_common_drv.h

62

void adf_devmgr_update_class_index(struct adf_hw_device_data *hw_data);

drivers/crypto/intel/qat/qat_common/adf_ctl_drv.c

332

struct adf_hw_device_data *hw_data;

drivers/crypto/intel/qat/qat_common/adf_ctl_drv.c

346

hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_ctl_drv.c

348

dev_info.num_ae = hw_data->get_num_aes(hw_data);

drivers/crypto/intel/qat/qat_common/adf_ctl_drv.c

349

dev_info.num_accel = hw_data->get_num_accels(hw_data);

drivers/crypto/intel/qat/qat_common/adf_ctl_drv.c

350

dev_info.num_logical_accel = hw_data->num_logical_accel;

drivers/crypto/intel/qat/qat_common/adf_ctl_drv.c

351

dev_info.banks_per_accel = hw_data->num_banks

drivers/crypto/intel/qat/qat_common/adf_ctl_drv.c

352

/ hw_data->num_logical_accel;

drivers/crypto/intel/qat/qat_common/adf_ctl_drv.c

353

strscpy(dev_info.name, hw_data->dev_class->name, sizeof(dev_info.name));

drivers/crypto/intel/qat/qat_common/adf_ctl_drv.c

354

dev_info.instance_id = hw_data->instance_id;

drivers/crypto/intel/qat/qat_common/adf_ctl_drv.c

355

dev_info.type = hw_data->dev_class->type;

drivers/crypto/intel/qat/qat_common/adf_dev_mgr.c

97

void adf_devmgr_update_class_index(struct adf_hw_device_data *hw_data)

drivers/crypto/intel/qat/qat_common/adf_dev_mgr.c

99

struct adf_hw_device_class *class = hw_data->dev_class;

drivers/crypto/intel/qat/qat_common/adf_fw_counters.c

109

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_fw_counters.c

120

ae_count = hweight_long(hw_data->ae_mask & ~hw_data->admin_ae_mask);

drivers/crypto/intel/qat/qat_common/adf_fw_counters.c

52

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_fw_counters.c

58

ae_mask = hw_data->ae_mask & ~hw_data->admin_ae_mask;

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

118

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

120

u32 fuses = hw_data->fuses[ADF_FUSECTL0];

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

121

u32 straps = hw_data->straps;

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

158

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

162

unsigned long accel_mask = hw_data->accel_mask;

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

166

for_each_set_bit(i, &accel_mask, hw_data->num_accel) {

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

30

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

32

unsigned long accel_mask = hw_data->accel_mask;

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

33

unsigned long ae_mask = hw_data->ae_mask;

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

37

for_each_set_bit(i, &ae_mask, hw_data->num_engines) {

drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c

47

for_each_set_bit(i, &accel_mask, hw_data->num_accel) {

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

215

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

219

if (bank_number >= hw_data->num_banks)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

284

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

285

u32 *thd2arb_map = hw_data->thd_to_arb_map;

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

292

if (!hw_data->get_rp_group || !hw_data->get_ena_thd_mask ||

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

293

!hw_data->get_num_aes || !hw_data->uof_get_num_objs ||

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

294

!hw_data->uof_get_ae_mask)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

301

ae_cnt = hw_data->get_num_aes(hw_data);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

302

worker_obj_cnt = hw_data->uof_get_num_objs(accel_dev) -

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

315

ae_mask = hw_data->uof_get_ae_mask(accel_dev, i);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

316

rp_group = hw_data->get_rp_group(accel_dev, ae_mask);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

317

thds_mask = hw_data->get_ena_thd_mask(accel_dev, i);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

344

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

350

if (!hw_data->get_rp_group || !hw_data->uof_get_ae_mask ||

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

351

!hw_data->uof_get_obj_type || !hw_data->uof_get_num_objs)

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

361

worker_obj_cnt = hw_data->uof_get_num_objs(accel_dev) -

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

366

ae_mask = hw_data->uof_get_ae_mask(accel_dev, i);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

367

rp_group = hw_data->get_rp_group(accel_dev, ae_mask);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

371

switch (hw_data->uof_get_obj_type(accel_dev, i)) {

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

412

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

437

do_div(wait_us, hw_data->clock_frequency);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

564

struct adf_hw_device_data *hw_data;

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

568

hw_data = container_of(device_data, struct adf_hw_device_data, rl_data);

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c

569

ae_cnt = hweight32(hw_data->get_ae_mask(hw_data));

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

106

for (i = 0; i < hw_data->num_banks_per_vf; i++) {

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

107

u32 pf_bank_nr = i + vf_nr * hw_data->num_banks_per_vf;

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

129

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

138

for (i = 0; i < hw_data->num_banks_per_vf; i++) {

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

139

u32 pf_bank_nr = i + vf_nr * hw_data->num_banks_per_vf;

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

316

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

327

rp_index = vf_nr * hw_data->num_banks_per_vf;

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

356

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

360

pf_bank_nr = vf_bank_info->bank_nr + vf_bank_info->vf_nr * hw_data->num_banks_per_vf;

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

361

ret = hw_data->bank_state_restore(accel_dev, pf_bank_nr,

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

408

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

424

for (i = 0; i < hw_data->num_banks_per_vf; i++) {

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

536

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

547

{&hw_data->accel_capabilities_mask, sizeof(hw_data->accel_capabilities_mask)}},

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

549

{&hw_data->ring_to_svc_map, sizeof(hw_data->ring_to_svc_map)}},

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

551

{&hw_data->extended_dc_capabilities, sizeof(hw_data->extended_dc_capabilities)}},

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

581

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

586

pf_bank_nr += vf_bank_info->vf_nr * hw_data->num_banks_per_vf;

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

588

ret = hw_data->bank_state_save(accel_dev, pf_bank_nr,

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

640

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

655

for (i = 0; i < hw_data->num_banks_per_vf; i++) {

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

782

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

792

{&hw_data->accel_capabilities_mask, sizeof(hw_data->accel_capabilities_mask)}},

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

794

{&hw_data->ring_to_svc_map, sizeof(hw_data->ring_to_svc_map)}},

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

796

{&hw_data->extended_dc_capabilities, sizeof(hw_data->extended_dc_capabilities)}},

drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c

96

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_heartbeat.c

255

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_heartbeat.c

259

if (!hw_data->get_hb_clock)

drivers/crypto/intel/qat/qat_common/adf_heartbeat.c

262

clk_per_sec = hw_data->get_hb_clock(hw_data);

drivers/crypto/intel/qat/qat_common/adf_heartbeat_inject.c

13

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_heartbeat_inject.c

17

if (hw_data->stop_timer)

drivers/crypto/intel/qat/qat_common/adf_heartbeat_inject.c

18

hw_data->stop_timer(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

106

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

114

hw_data->get_arb_info(&info);

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

115

thd_2_arb_cfg = hw_data->get_arb_mapping(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

20

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

22

unsigned long ae_mask = hw_data->ae_mask;

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

28

hw_data->get_arb_info(&info);

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

39

thd_2_arb_cfg = hw_data->get_arb_mapping(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

41

for_each_set_bit(i, &ae_mask, hw_data->num_engines)

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

51

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

53

u32 tx_ring_mask = hw_data->tx_rings_mask;

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

54

u32 shift = hw_data->tx_rx_gap;

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

75

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

82

hw_data->get_arb_info(&info);

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

91

hw_data->get_arb_info(&info);

drivers/crypto/intel/qat/qat_common/adf_hw_arbiter.c

94

for (i = 0; i < hw_data->num_engines; i++)

drivers/crypto/intel/qat/qat_common/adf_init.c

102

if (hw_data->get_ring_to_svc_map)

drivers/crypto/intel/qat/qat_common/adf_init.c

103

hw_data->ring_to_svc_map = hw_data->get_ring_to_svc_map(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_init.c

119

if (hw_data->alloc_irq(accel_dev)) {

drivers/crypto/intel/qat/qat_common/adf_init.c

125

if (hw_data->ras_ops.enable_ras_errors)

drivers/crypto/intel/qat/qat_common/adf_init.c

126

hw_data->ras_ops.enable_ras_errors(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_init.c

128

hw_data->enable_ints(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_init.c

129

hw_data->enable_error_correction(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_init.c

131

ret = hw_data->pfvf_ops.enable_comms(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_init.c

180

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_init.c

192

if (hw_data->send_admin_init(accel_dev)) {

drivers/crypto/intel/qat/qat_common/adf_init.c

197

if (hw_data->measure_clock) {

drivers/crypto/intel/qat/qat_common/adf_init.c

198

ret = hw_data->measure_clock(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_init.c

206

if (hw_data->set_ssm_wdtimer)

drivers/crypto/intel/qat/qat_common/adf_init.c

207

hw_data->set_ssm_wdtimer(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_init.c

210

if (hw_data->enable_pm && hw_data->enable_pm(accel_dev)) {

drivers/crypto/intel/qat/qat_common/adf_init.c

215

if (hw_data->start_timer) {

drivers/crypto/intel/qat/qat_common/adf_init.c

216

ret = hw_data->start_timer(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_init.c

282

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_init.c

323

if (hw_data->stop_timer)

drivers/crypto/intel/qat/qat_common/adf_init.c

324

hw_data->stop_timer(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_init.c

326

hw_data->disable_iov(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_init.c

348

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_init.c

351

if (!hw_data) {

drivers/crypto/intel/qat/qat_common/adf_init.c

384

if (hw_data->ras_ops.disable_ras_errors)

drivers/crypto/intel/qat/qat_common/adf_init.c

385

hw_data->ras_ops.disable_ras_errors(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_init.c

392

hw_data->free_irq(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_init.c

400

if (hw_data->exit_arb)

drivers/crypto/intel/qat/qat_common/adf_init.c

401

hw_data->exit_arb(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_init.c

403

if (hw_data->exit_admin_comms)

drivers/crypto/intel/qat/qat_common/adf_init.c

404

hw_data->exit_admin_comms(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_init.c

67

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_init.c

70

if (!hw_data) {

drivers/crypto/intel/qat/qat_common/adf_init.c

87

if (hw_data->init_device && hw_data->init_device(accel_dev)) {

drivers/crypto/intel/qat/qat_common/adf_init.c

92

if (hw_data->init_admin_comms && hw_data->init_admin_comms(accel_dev)) {

drivers/crypto/intel/qat/qat_common/adf_init.c

97

if (hw_data->init_arb && hw_data->init_arb(accel_dev)) {

drivers/crypto/intel/qat/qat_common/adf_isr.c

126

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_isr.c

128

if (hw_data->handle_pm_interrupt &&

drivers/crypto/intel/qat/qat_common/adf_isr.c

129

hw_data->handle_pm_interrupt(accel_dev))

drivers/crypto/intel/qat/qat_common/adf_isr.c

180

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_isr.c

183

int clust_irq = hw_data->num_banks;

drivers/crypto/intel/qat/qat_common/adf_isr.c

187

for (i = 0; i < hw_data->num_banks; i++) {

drivers/crypto/intel/qat/qat_common/adf_isr.c

205

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_isr.c

208

int clust_irq = hw_data->num_banks;

drivers/crypto/intel/qat/qat_common/adf_isr.c

214

for (i = 0; i < hw_data->num_banks; i++) {

drivers/crypto/intel/qat/qat_common/adf_isr.c

238

cpu = ((accel_dev->accel_id * hw_data->num_banks) +

drivers/crypto/intel/qat/qat_common/adf_isr.c

24

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_isr.c

25

u32 msix_num_entries = hw_data->num_banks + 1;

drivers/crypto/intel/qat/qat_common/adf_isr.c

272

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_isr.c

278

msix_num_entries += hw_data->num_banks;

drivers/crypto/intel/qat/qat_common/adf_isr.c

28

if (hw_data->set_msix_rttable)

drivers/crypto/intel/qat/qat_common/adf_isr.c

29

hw_data->set_msix_rttable(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_isr.c

299

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_isr.c

302

for (i = 0; i < hw_data->num_banks; i++)

drivers/crypto/intel/qat/qat_common/adf_isr.c

312

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_isr.c

315

for (i = 0; i < hw_data->num_banks; i++) {

drivers/crypto/intel/qat/qat_common/adf_pfvf_pf_msg.c

90

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_pfvf_pf_msg.c

93

caps_msg.ext_dc_caps = hw_data->extended_dc_capabilities;

drivers/crypto/intel/qat/qat_common/adf_pfvf_pf_msg.c

94

caps_msg.capabilities = hw_data->accel_capabilities_mask;

drivers/crypto/intel/qat/qat_common/adf_pfvf_pf_proto.c

194

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_pfvf_pf_proto.c

209

if (!hw_data->ring_pair_reset || rsvd_field) {

drivers/crypto/intel/qat/qat_common/adf_pfvf_pf_proto.c

216

if (bank_number >= hw_data->num_banks_per_vf) {

drivers/crypto/intel/qat/qat_common/adf_pfvf_pf_proto.c

225

bank_number = vf_nr * hw_data->num_banks_per_vf + bank_number;

drivers/crypto/intel/qat/qat_common/adf_pfvf_pf_proto.c

226

if (hw_data->ring_pair_reset(accel_dev, bank_number)) {

drivers/crypto/intel/qat/qat_common/adf_pfvf_vf_msg.c

112

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_pfvf_vf_msg.c

133

hw_data->clock_frequency = cap_msg.frequency;

drivers/crypto/intel/qat/qat_common/adf_pfvf_vf_msg.c

139

hw_data->accel_capabilities_mask = cap_msg.capabilities;

drivers/crypto/intel/qat/qat_common/adf_pfvf_vf_msg.c

145

hw_data->extended_dc_capabilities = cap_msg.ext_dc_caps;

drivers/crypto/intel/qat/qat_common/adf_rl.c

1051

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_rl.c

1052

struct adf_rl_hw_data *rl_hw_data = &hw_data->rl_data;

drivers/crypto/intel/qat/qat_common/adf_rl.c

266

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_rl.c

268

u32 base_offset = hw_data->rl_data.r2l_offset;

drivers/crypto/intel/qat/qat_common/adf_rl.c

282

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_rl.c

284

u32 base_offset = hw_data->rl_data.l2c_offset;

drivers/crypto/intel/qat/qat_common/adf_rl.c

296

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_rl.c

298

u32 base_offset = hw_data->rl_data.c2s_offset;

drivers/crypto/intel/qat/qat_common/adf_rl.c

526

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_rl.c

533

avail_slice_cycles = hw_data->clock_frequency;

drivers/crypto/intel/qat/qat_common/adf_rl.c

534

avail_slice_cycles *= hw_data->get_svc_slice_cnt(accel_dev, svc_type);

drivers/crypto/intel/qat/qat_common/adf_rl.c

558

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_rl.c

564

avail_ae_cycles = hw_data->clock_frequency;

drivers/crypto/intel/qat/qat_common/adf_sriov.c

239

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_sriov.c

255

if (hw_data->configure_iov_threads)

drivers/crypto/intel/qat/qat_common/adf_sriov.c

256

hw_data->configure_iov_threads(accel_dev, false);

drivers/crypto/intel/qat/qat_common/adf_sriov.c

56

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_sriov.c

74

if (hw_data->configure_iov_threads)

drivers/crypto/intel/qat/qat_common/adf_sriov.c

75

hw_data->configure_iov_threads(accel_dev, true);

drivers/crypto/intel/qat/qat_common/adf_sysfs.c

120

struct adf_hw_device_data *hw_data;

drivers/crypto/intel/qat/qat_common/adf_sysfs.c

143

hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_sysfs.c

149

hw_data->accel_capabilities_mask = hw_data->get_accel_cap(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_sysfs.c

150

if (!hw_data->accel_capabilities_mask)

drivers/crypto/intel/qat/qat_common/adf_sysfs.c

247

struct adf_hw_device_data *hw_data;

drivers/crypto/intel/qat/qat_common/adf_sysfs.c

255

hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_sysfs.c

262

hw_data->num_banks_per_vf);

drivers/crypto/intel/qat/qat_common/adf_tl_debugfs.c

532

struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);

drivers/crypto/intel/qat/qat_common/adf_tl_debugfs.c

539

if (new_rp_num >= hw_data->num_rps) {

drivers/crypto/intel/qat/qat_common/adf_tl_debugfs.c

544

for (i = 0; i < hw_data->tl_data.max_rp; i++) {

drivers/crypto/intel/qat/qat_common/adf_transport.c

164

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_transport.c

187

if (hw_data->tx_rings_mask & (1 << ring->ring_number))

drivers/crypto/intel/qat/qat_common/adf_transport.c

388

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_transport.c

389

u8 num_rings_per_bank = hw_data->num_rings_per_bank;

drivers/crypto/intel/qat/qat_common/adf_transport.c

390

struct adf_hw_csr_ops *csr_ops = &hw_data->csr_ops;

drivers/crypto/intel/qat/qat_common/adf_transport.c

426

if (hw_data->tx_rings_mask & (1 << i)) {

drivers/crypto/intel/qat/qat_common/adf_transport.c

434

if (i < hw_data->tx_rx_gap) {

drivers/crypto/intel/qat/qat_common/adf_transport.c

439

tx_ring = &bank->rings[i - hw_data->tx_rx_gap];

drivers/crypto/intel/qat/qat_common/adf_transport.c

454

ring_mask = hw_data->tx_rings_mask;

drivers/crypto/intel/qat/qat_common/adf_transport.c

525

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_transport.c

526

u8 num_rings_per_bank = hw_data->num_rings_per_bank;

drivers/crypto/intel/qat/qat_common/adf_transport.c

535

if (hw_data->tx_rings_mask & (1 << i))

drivers/crypto/intel/qat/qat_common/adf_vf_isr.c

135

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/adf_vf_isr.c

136

struct adf_hw_csr_ops *csr_ops = &hw_data->csr_ops;

drivers/crypto/intel/qat/qat_common/adf_vf_isr.c

138

&GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)];

drivers/crypto/intel/qat/qat_common/qat_hal.c

686

struct adf_hw_device_data *hw_data = accel_dev->hw_device;

drivers/crypto/intel/qat/qat_common/qat_hal.c

740

handle->chip_info->icp_rst_mask = (hw_data->ae_mask << RST_CSR_AE_LSB) |

drivers/crypto/intel/qat/qat_common/qat_hal.c

741

(hw_data->accel_mask << RST_CSR_QAT_LSB);

drivers/crypto/intel/qat/qat_common/qat_hal.c

767

handle->chip_info->icp_rst_mask = (hw_data->ae_mask << RST_CSR_AE_LSB) |

drivers/crypto/intel/qat/qat_common/qat_hal.c

768

(hw_data->accel_mask << RST_CSR_QAT_LSB);

drivers/crypto/intel/qat/qat_common/qat_hal.c

795

&pci_info->pci_bars[hw_data->get_sram_bar_id(hw_data)];

drivers/crypto/intel/qat/qat_common/qat_hal.c

799

handle->hal_handle->ae_mask = hw_data->ae_mask;

drivers/crypto/intel/qat/qat_common/qat_hal.c

800

handle->hal_handle->admin_ae_mask = hw_data->admin_ae_mask;

drivers/crypto/intel/qat/qat_common/qat_hal.c

801

handle->hal_handle->slice_mask = hw_data->accel_mask;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

214

void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

216

hw_data->dev_class = &dh895xcc_class;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

217

hw_data->instance_id = dh895xcc_class.instances++;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

218

hw_data->num_banks = ADF_DH895XCC_ETR_MAX_BANKS;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

219

hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

220

hw_data->num_accel = ADF_DH895XCC_MAX_ACCELERATORS;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

221

hw_data->num_logical_accel = 1;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

222

hw_data->num_engines = ADF_DH895XCC_MAX_ACCELENGINES;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

223

hw_data->tx_rx_gap = ADF_GEN2_RX_RINGS_OFFSET;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

224

hw_data->tx_rings_mask = ADF_GEN2_TX_RINGS_MASK;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

225

hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

226

hw_data->alloc_irq = adf_isr_resource_alloc;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

227

hw_data->free_irq = adf_isr_resource_free;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

228

hw_data->enable_error_correction = adf_gen2_enable_error_correction;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

229

hw_data->get_accel_mask = get_accel_mask;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

230

hw_data->get_ae_mask = get_ae_mask;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

231

hw_data->get_accel_cap = get_accel_cap;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

232

hw_data->get_num_accels = adf_gen2_get_num_accels;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

233

hw_data->get_num_aes = adf_gen2_get_num_aes;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

234

hw_data->get_etr_bar_id = get_etr_bar_id;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

235

hw_data->get_misc_bar_id = get_misc_bar_id;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

236

hw_data->get_admin_info = adf_gen2_get_admin_info;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

237

hw_data->get_arb_info = adf_gen2_get_arb_info;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

238

hw_data->get_sram_bar_id = get_sram_bar_id;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

239

hw_data->get_sku = get_sku;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

240

hw_data->fw_name = ADF_DH895XCC_FW;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

241

hw_data->fw_mmp_name = ADF_DH895XCC_MMP;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

242

hw_data->init_admin_comms = adf_init_admin_comms;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

243

hw_data->exit_admin_comms = adf_exit_admin_comms;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

244

hw_data->configure_iov_threads = configure_iov_threads;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

245

hw_data->send_admin_init = adf_send_admin_init;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

246

hw_data->init_arb = adf_init_arb;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

247

hw_data->exit_arb = adf_exit_arb;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

248

hw_data->get_arb_mapping = adf_get_arbiter_mapping;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

249

hw_data->enable_ints = adf_gen2_enable_ints;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

250

hw_data->reset_device = adf_reset_sbr;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

251

hw_data->disable_iov = adf_disable_sriov;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

252

hw_data->dev_config = adf_gen2_dev_config;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

253

hw_data->clock_frequency = ADF_DH895X_AE_FREQ;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

254

hw_data->get_hb_clock = get_ts_clock;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

255

hw_data->num_hb_ctrs = ADF_NUM_HB_CNT_PER_AE;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

256

hw_data->check_hb_ctrs = adf_heartbeat_check_ctrs;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

258

adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

259

hw_data->pfvf_ops.enable_vf2pf_interrupts = enable_vf2pf_interrupts;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

260

hw_data->pfvf_ops.disable_all_vf2pf_interrupts = disable_all_vf2pf_interrupts;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

261

hw_data->pfvf_ops.disable_pending_vf2pf_interrupts = disable_pending_vf2pf_interrupts;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

262

adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

263

adf_gen2_init_dc_ops(&hw_data->dc_ops);

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

266

void adf_clean_hw_data_dh895xcc(struct adf_hw_device_data *hw_data)

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c

268

hw_data->dev_class->instances--;

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h

42

void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data);

drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h

43

void adf_clean_hw_data_dh895xcc(struct adf_hw_device_data *hw_data);

drivers/crypto/intel/qat/qat_dh895xcc/adf_drv.c

100

hw_data = kzalloc_node(sizeof(*hw_data), GFP_KERNEL,

drivers/crypto/intel/qat/qat_dh895xcc/adf_drv.c

102

if (!hw_data) {

drivers/crypto/intel/qat/qat_dh895xcc/adf_drv.c

107

accel_dev->hw_device = hw_data;

drivers/crypto/intel/qat/qat_dh895xcc/adf_drv.c

111

&hw_data->fuses[ADF_FUSECTL0]);

drivers/crypto/intel/qat/qat_dh895xcc/adf_drv.c

114

hw_data->accel_mask = hw_data->get_accel_mask(hw_data);

drivers/crypto/intel/qat/qat_dh895xcc/adf_drv.c

115

hw_data->ae_mask = hw_data->get_ae_mask(hw_data);

drivers/crypto/intel/qat/qat_dh895xcc/adf_drv.c

116

accel_pci_dev->sku = hw_data->get_sku(hw_data);

drivers/crypto/intel/qat/qat_dh895xcc/adf_drv.c

118

if (!hw_data->accel_mask || !hw_data->ae_mask ||

drivers/crypto/intel/qat/qat_dh895xcc/adf_drv.c

119

((~hw_data->ae_mask) & 0x01)) {

drivers/crypto/intel/qat/qat_dh895xcc/adf_drv.c

151

hw_data->accel_capabilities_mask = hw_data->get_accel_cap(accel_dev);

drivers/crypto/intel/qat/qat_dh895xcc/adf_drv.c

60

struct adf_hw_device_data *hw_data;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

100

adf_devmgr_update_class_index(hw_data);

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

61

void adf_init_hw_data_dh895xcciov(struct adf_hw_device_data *hw_data)

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

63

hw_data->dev_class = &dh895xcciov_class;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

64

hw_data->num_banks = ADF_DH895XCCIOV_ETR_MAX_BANKS;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

65

hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

66

hw_data->num_accel = ADF_DH895XCCIOV_MAX_ACCELERATORS;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

67

hw_data->num_logical_accel = 1;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

68

hw_data->num_engines = ADF_DH895XCCIOV_MAX_ACCELENGINES;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

69

hw_data->tx_rx_gap = ADF_DH895XCCIOV_RX_RINGS_OFFSET;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

70

hw_data->tx_rings_mask = ADF_DH895XCCIOV_TX_RINGS_MASK;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

71

hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

72

hw_data->alloc_irq = adf_vf_isr_resource_alloc;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

73

hw_data->free_irq = adf_vf_isr_resource_free;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

74

hw_data->enable_error_correction = adf_vf_void_noop;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

75

hw_data->init_admin_comms = adf_vf_int_noop;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

76

hw_data->exit_admin_comms = adf_vf_void_noop;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

77

hw_data->send_admin_init = adf_vf2pf_notify_init;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

78

hw_data->init_arb = adf_vf_int_noop;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

79

hw_data->exit_arb = adf_vf_void_noop;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

80

hw_data->disable_iov = adf_vf2pf_notify_shutdown;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

81

hw_data->get_accel_mask = get_accel_mask;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

82

hw_data->get_ae_mask = get_ae_mask;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

83

hw_data->get_num_accels = get_num_accels;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

84

hw_data->get_num_aes = get_num_aes;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

85

hw_data->get_etr_bar_id = get_etr_bar_id;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

86

hw_data->get_misc_bar_id = get_misc_bar_id;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

87

hw_data->get_sku = get_sku;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

88

hw_data->enable_ints = adf_vf_void_noop;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

89

hw_data->dev_class->instances++;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

90

hw_data->dev_config = adf_gen2_dev_config;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

91

adf_devmgr_update_class_index(hw_data);

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

92

adf_gen2_init_vf_pfvf_ops(&hw_data->pfvf_ops);

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

93

adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

94

adf_gen2_init_dc_ops(&hw_data->dc_ops);

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

97

void adf_clean_hw_data_dh895xcciov(struct adf_hw_device_data *hw_data)

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c

99

hw_data->dev_class->instances--;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.h

16

void adf_init_hw_data_dh895xcciov(struct adf_hw_device_data *hw_data);

drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.h

17

void adf_clean_hw_data_dh895xcciov(struct adf_hw_device_data *hw_data);

drivers/crypto/intel/qat/qat_dh895xccvf/adf_drv.c

112

hw_data = kzalloc_node(sizeof(*hw_data), GFP_KERNEL,

drivers/crypto/intel/qat/qat_dh895xccvf/adf_drv.c

114

if (!hw_data) {

drivers/crypto/intel/qat/qat_dh895xccvf/adf_drv.c

118

accel_dev->hw_device = hw_data;

drivers/crypto/intel/qat/qat_dh895xccvf/adf_drv.c

122

hw_data->accel_mask = hw_data->get_accel_mask(hw_data);

drivers/crypto/intel/qat/qat_dh895xccvf/adf_drv.c

123

hw_data->ae_mask = hw_data->get_ae_mask(hw_data);

drivers/crypto/intel/qat/qat_dh895xccvf/adf_drv.c

124

accel_pci_dev->sku = hw_data->get_sku(hw_data);

drivers/crypto/intel/qat/qat_dh895xccvf/adf_drv.c

79

struct adf_hw_device_data *hw_data;

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

563

struct hw_gpio *hw_data;

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

593

hw_data = FROM_HW_GPIO_PIN(ddc->pin_data->pin);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

596

config_data.config.ddc.data_en_bit_present = hw_data->store.en != 0;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1465

struct smu8_hwmgr *hw_data = hwmgr->backend;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1468

if (hw_data->cc6_settings.cc6_setting_changed) {

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1470

hw_data->cc6_settings.cc6_setting_changed = false;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1472

smu8_hw_print_display_cfg(&hw_data->cc6_settings);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1474

data |= (hw_data->cc6_settings.cpu_pstate_separation_time

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1478

data |= (hw_data->cc6_settings.cpu_cc6_disable ? 0x1 : 0x0)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1481

data |= (hw_data->cc6_settings.cpu_pstate_disable ? 0x1 : 0x0)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1500

struct smu8_hwmgr *hw_data = hwmgr->backend;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1503

hw_data->cc6_settings.cpu_pstate_separation_time ||

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1504

cc6_disable != hw_data->cc6_settings.cpu_cc6_disable ||

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1505

pstate_disable != hw_data->cc6_settings.cpu_pstate_disable ||

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1506

pstate_switch_disable != hw_data->cc6_settings.nb_pstate_switch_disable) {

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1508

hw_data->cc6_settings.cc6_setting_changed = true;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1510

hw_data->cc6_settings.cpu_pstate_separation_time =

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1512

hw_data->cc6_settings.cpu_cc6_disable =

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1514

hw_data->cc6_settings.cpu_pstate_disable =

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1516

hw_data->cc6_settings.nb_pstate_switch_disable =

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

798

struct smu8_hwmgr *hw_data = hwmgr->backend;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

800

if (hw_data->is_nb_dpm_enabled) {

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

869

struct smu8_hwmgr *hw_data = hwmgr->backend;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

873

if (hw_data->sys_info.nb_dpm_enable) {

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

874

disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

875

enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

931

struct smu8_hwmgr *hw_data = hwmgr->backend;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

933

hw_data->disp_clk_bypass_pending = false;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

934

hw_data->disp_clk_bypass = false;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

939

struct smu8_hwmgr *hw_data = hwmgr->backend;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

941

hw_data->is_nb_dpm_enabled = false;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

946

struct smu8_hwmgr *hw_data = hwmgr->backend;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

948

hw_data->cc6_settings.cc6_setting_changed = false;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

949

hw_data->cc6_settings.cpu_pstate_separation_time = 0;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

950

hw_data->cc6_settings.cpu_cc6_disable = false;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

951

hw_data->cc6_settings.cpu_pstate_disable = false;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1038

struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1040

struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1044

uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1099

hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1104

(hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask & (1 << i)) >> i;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1115

while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1116

((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1120

while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1121

((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1126

((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1210

struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1212

struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1238

hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1243

(hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask & (1 << i)) >> i;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1492

struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1498

for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1499

for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1501

hw_data->dpm_table.sclk_table.dpm_levels[i].value,

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1502

hw_data->dpm_table.mclk_table.dpm_levels[j].value,

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1505

result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1619

struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1629

hw_data->vbios_boot_state.sclk_bootup_value) {

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1638

hw_data->vbios_boot_state.mclk_bootup_value) {

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1916

struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1929

if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control)

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1941

if (hw_data->is_memory_gddr5)

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1944

if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) {

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2030

table->PCIeBootLinkLevel = hw_data->dpm_table.pcie_speed_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2037

hw_data->vr_config = table->VRConfig;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2093

for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1036

struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1038

struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1068

hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1073

(hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask >> i) & 0x1;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1279

struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1287

for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1288

for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1290

hw_data->dpm_table.sclk_table.dpm_levels[i].value,

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1291

hw_data->dpm_table.mclk_table.dpm_levels[j].value,

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1403

struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1413

hw_data->vbios_boot_state.sclk_bootup_value) {

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1422

hw_data->vbios_boot_state.mclk_bootup_value) {

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1920

struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1937

if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control)

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1949

if (hw_data->is_memory_gddr5)

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1952

if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) {

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2034

PP_ASSERT_WITH_CODE(hw_data->dpm_table.pcie_speed_table.count >= 1,

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2038

hw_data->dpm_table.pcie_speed_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2103

for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

866

struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

868

struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

872

uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

910

hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

915

(hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask >> i) & 0x1;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

926

while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

927

((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

931

while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

932

((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

937

((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &

drivers/media/i2c/ds90ub953.c

1064

priv->hw_data->model, dev_name(dev)),

drivers/media/i2c/ds90ub953.c

1216

dev_info(dev, "Found %s rev/mask %#04x\n", priv->hw_data->model, v);

drivers/media/i2c/ds90ub953.c

1316

priv->hw_data = device_get_match_data(dev);

drivers/media/i2c/ds90ub953.c

64

const struct ub953_hw_data *hw_data;

drivers/media/i2c/ds90ub953.c

832

if (priv->hw_data->is_ub971)

drivers/media/i2c/ds90ub953.c

917

if (priv->hw_data->is_ub971) {

drivers/media/i2c/ds90ub953.c

952

if (priv->hw_data->is_ub971)

drivers/media/i2c/ds90ub953.c

997

if (priv->hw_data->is_ub971) {

drivers/media/i2c/ds90ub960.c

1354

priv->hw_data->num_rxports, 0);

drivers/media/i2c/ds90ub960.c

1845

if (port_mask >= BIT(priv->hw_data->num_rxports))

drivers/media/i2c/ds90ub960.c

1857

priv->hw_data->num_rxports) {

drivers/media/i2c/ds90ub960.c

1908

for_each_set_bit(nport, &port_mask, priv->hw_data->num_rxports) {

drivers/media/i2c/ds90ub960.c

1927

if (priv->hw_data->is_ub9702) {

drivers/media/i2c/ds90ub960.c

2189

if (priv->hw_data->is_ub9702)

drivers/media/i2c/ds90ub960.c

2355

if (priv->hw_data->is_ub9702)

drivers/media/i2c/ds90ub960.c

2363

for (unsigned int nport = 0; nport < priv->hw_data->num_txports;

drivers/media/i2c/ds90ub960.c

3627

if (!priv->hw_data->is_ub9702) {

drivers/media/i2c/ds90ub960.c

4033

.source_pad = priv->hw_data->num_rxports,

drivers/media/i2c/ds90ub960.c

4143

for (unsigned int nport = 0; nport < priv->hw_data->num_txports;

drivers/media/i2c/ds90ub960.c

4253

if (!priv->hw_data->is_ub9702) {

drivers/media/i2c/ds90ub960.c

4323

for (unsigned int i = 0; i < priv->hw_data->num_txports; i++) {

drivers/media/i2c/ds90ub960.c

4358

for (nport = 0; nport < priv->hw_data->num_txports; nport++) {

drivers/media/i2c/ds90ub960.c

4411

if (!priv->hw_data->is_fpdlink4 && cdr_mode == RXPORT_CDR_FPD4) {

drivers/media/i2c/ds90ub960.c

4705

for (nport = 0; nport < priv->hw_data->num_txports; nport++) {

drivers/media/i2c/ds90ub960.c

4706

unsigned int port = nport + priv->hw_data->num_rxports;

drivers/media/i2c/ds90ub960.c

4868

for (i = 0; i < priv->hw_data->num_rxports + priv->hw_data->num_txports; i++) {

drivers/media/i2c/ds90ub960.c

4875

priv->hw_data->num_rxports +

drivers/media/i2c/ds90ub960.c

4876

priv->hw_data->num_txports,

drivers/media/i2c/ds90ub960.c

5006

dev_dbg(dev, "Found %s (rev/mask %#04x)\n", priv->hw_data->model,

drivers/media/i2c/ds90ub960.c

5013

if (priv->hw_data->is_ub9702)

drivers/media/i2c/ds90ub960.c

5032

if (priv->hw_data->is_ub9702) {

drivers/media/i2c/ds90ub960.c

5071

priv->hw_data = device_get_match_data(dev);

drivers/media/i2c/ds90ub960.c

5105

if (priv->hw_data->is_ub9702)

drivers/media/i2c/ds90ub960.c

549

const struct ub960_hw_data *hw_data;

drivers/media/i2c/ds90ub960.c

604

return pad < priv->hw_data->num_rxports;

drivers/media/i2c/ds90ub960.c

609

return pad >= priv->hw_data->num_rxports;

drivers/media/i2c/ds90ub960.c

617

return pad - priv->hw_data->num_rxports;

drivers/media/i2c/ds90ub960.c

677

for (; it.nport < priv->hw_data->num_rxports; it.nport++) {

drivers/media/i2c/ds90ub960.c

699

it.nport < (priv)->hw_data->num_rxports; \

drivers/media/i2c/ds90ub960.c

706

it.nport < (priv)->hw_data->num_rxports; \

drivers/media/i2c/ds90ub960.c

715

it.nport < (priv)->hw_data->num_rxports; \

drivers/net/wireless/intel/ipw2x00/ipw2100.c

3538

} hw_data[] = {

drivers/net/wireless/intel/ipw2x00/ipw2100.c

3780

for (i = 0; i < ARRAY_SIZE(hw_data); i++) {

drivers/net/wireless/intel/ipw2x00/ipw2100.c

3781

read_register(dev, hw_data[i].addr, &val);

drivers/net/wireless/intel/ipw2x00/ipw2100.c

3783

hw_data[i].name, hw_data[i].addr, val);

drivers/regulator/qcom-rpmh-regulator.c

1052

.hw_data = _hw_data, \

drivers/regulator/qcom-rpmh-regulator.c

160

const struct rpmh_vreg_hw_data *hw_data;

drivers/regulator/qcom-rpmh-regulator.c

185

const struct rpmh_vreg_hw_data *hw_data;

drivers/regulator/qcom-rpmh-regulator.c

309

pmic_mode = vreg->hw_data->pmic_mode_map[mode];

drivers/regulator/qcom-rpmh-regulator.c

361

if (load_uA >= vreg->hw_data->hpm_min_load_uA)

drivers/regulator/qcom-rpmh-regulator.c

491

vreg->hw_data = rpmh_data->hw_data;

drivers/regulator/qcom-rpmh-regulator.c

497

if (rpmh_data->hw_data->n_voltages) {

drivers/regulator/qcom-rpmh-regulator.c

498

vreg->rdesc.linear_ranges = rpmh_data->hw_data->voltage_ranges;

drivers/regulator/qcom-rpmh-regulator.c

499

vreg->rdesc.n_linear_ranges = rpmh_data->hw_data->n_linear_ranges;

drivers/regulator/qcom-rpmh-regulator.c

500

vreg->rdesc.n_voltages = rpmh_data->hw_data->n_voltages;

drivers/regulator/qcom-rpmh-regulator.c

508

vreg->rdesc.ops = vreg->hw_data->ops;

drivers/regulator/qcom-rpmh-regulator.c

509

vreg->rdesc.of_map_mode = vreg->hw_data->of_map_mode;

drivers/regulator/qcom-rpmh-regulator.c

515

if (rpmh_data->hw_data->regulator_type == XOB &&

drivers/video/backlight/apple_bl.c

126

static const struct hw_data nvidia_chipset_data = {

drivers/video/backlight/apple_bl.c

151

hw_data = &intel_chipset_data;

drivers/video/backlight/apple_bl.c

153

hw_data = &nvidia_chipset_data;

drivers/video/backlight/apple_bl.c

157

if (!hw_data) {

drivers/video/backlight/apple_bl.c

164

intensity = hw_data->backlight_ops.get_brightness(NULL);

drivers/video/backlight/apple_bl.c

167

hw_data->set_brightness(1);

drivers/video/backlight/apple_bl.c

168

if (!hw_data->backlight_ops.get_brightness(NULL))

drivers/video/backlight/apple_bl.c

171

hw_data->set_brightness(0);

drivers/video/backlight/apple_bl.c

174

if (!request_region(hw_data->iostart, hw_data->iolen,

drivers/video/backlight/apple_bl.c

182

NULL, NULL, &hw_data->backlight_ops, &props);

drivers/video/backlight/apple_bl.c

185

release_region(hw_data->iostart, hw_data->iolen);

drivers/video/backlight/apple_bl.c

190

hw_data->backlight_ops.get_brightness(apple_backlight_device);

drivers/video/backlight/apple_bl.c

200

release_region(hw_data->iostart, hw_data->iolen);

drivers/video/backlight/apple_bl.c

201

hw_data = NULL;

drivers/video/backlight/apple_bl.c

40

static const struct hw_data *hw_data;

drivers/video/backlight/apple_bl.c

81

static const struct hw_data intel_chipset_data = {

include/sound/pcm-indirect.h

126

size_t hw_to_end = rec->hw_buffer_size - rec->hw_data;

include/sound/pcm-indirect.h

138

rec->hw_data += bytes;

include/sound/pcm-indirect.h

139

if ((int)rec->hw_data == rec->hw_buffer_size)

include/sound/pcm-indirect.h

140

rec->hw_data = 0;

include/sound/pcm-indirect.h

17

unsigned int hw_data; /* Offset to next dst (or src) in hw ring buffer */

include/sound/pcm-indirect.h

53

unsigned int hw_to_end = rec->hw_buffer_size - rec->hw_data;

include/sound/pcm-indirect.h

65

rec->hw_data += bytes;

include/sound/pcm-indirect.h

66

if (rec->hw_data == rec->hw_buffer_size)

include/sound/pcm-indirect.h

67

rec->hw_data = 0;

net/core/drop_monitor.c

1004

spin_unlock_irqrestore(&hw_data->drop_queue.lock, flags);

net/core/drop_monitor.c

1005

u64_stats_update_begin(&hw_data->stats.syncp);

net/core/drop_monitor.c

1006

u64_stats_inc(&hw_data->stats.dropped);

net/core/drop_monitor.c

1007

u64_stats_update_end(&hw_data->stats.syncp);

net/core/drop_monitor.c

1066

struct per_cpu_dm_data *hw_data = &per_cpu(dm_hw_cpu_data, cpu);

net/core/drop_monitor.c

1069

INIT_WORK(&hw_data->dm_alert_work, ops->hw_work_item_func);

net/core/drop_monitor.c

1070

timer_setup(&hw_data->send_timer, sched_send_work, 0);

net/core/drop_monitor.c

1071

hw_entries = net_dm_hw_reset_per_cpu_data(hw_data);

net/core/drop_monitor.c

1087

struct per_cpu_dm_data *hw_data = &per_cpu(dm_hw_cpu_data, cpu);

net/core/drop_monitor.c

1090

timer_delete_sync(&hw_data->send_timer);

net/core/drop_monitor.c

1091

cancel_work_sync(&hw_data->dm_alert_work);

net/core/drop_monitor.c

1092

while ((skb = __skb_dequeue(&hw_data->drop_queue))) {

net/core/drop_monitor.c

1121

struct per_cpu_dm_data *hw_data = &per_cpu(dm_hw_cpu_data, cpu);

net/core/drop_monitor.c

1124

timer_delete_sync(&hw_data->send_timer);

net/core/drop_monitor.c

1125

cancel_work_sync(&hw_data->dm_alert_work);

net/core/drop_monitor.c

1126

while ((skb = __skb_dequeue(&hw_data->drop_queue))) {

net/core/drop_monitor.c

1490

struct per_cpu_dm_data *hw_data = &per_cpu(dm_hw_cpu_data, cpu);

net/core/drop_monitor.c

1491

struct net_dm_stats *cpu_stats = &hw_data->stats;

net/core/drop_monitor.c

1710

struct per_cpu_dm_data *hw_data;

net/core/drop_monitor.c

1712

hw_data = &per_cpu(dm_hw_cpu_data, cpu);

net/core/drop_monitor.c

1713

__net_dm_cpu_data_init(hw_data);

net/core/drop_monitor.c

1718

struct per_cpu_dm_data *hw_data;

net/core/drop_monitor.c

1720

hw_data = &per_cpu(dm_hw_cpu_data, cpu);

net/core/drop_monitor.c

1721

kfree(hw_data->hw_entries);

net/core/drop_monitor.c

1722

__net_dm_cpu_data_fini(hw_data);

net/core/drop_monitor.c

304

net_dm_hw_reset_per_cpu_data(struct per_cpu_dm_data *hw_data)

net/core/drop_monitor.c

315

mod_timer(&hw_data->send_timer, jiffies + HZ / 10);

net/core/drop_monitor.c

318

raw_spin_lock_irqsave(&hw_data->lock, flags);

net/core/drop_monitor.c

319

swap(hw_data->hw_entries, hw_entries);

net/core/drop_monitor.c

320

raw_spin_unlock_irqrestore(&hw_data->lock, flags);

net/core/drop_monitor.c

411

struct per_cpu_dm_data *hw_data;

net/core/drop_monitor.c

415

hw_data = container_of(work, struct per_cpu_dm_data, dm_alert_work);

net/core/drop_monitor.c

417

hw_entries = net_dm_hw_reset_per_cpu_data(hw_data);

net/core/drop_monitor.c

444

struct per_cpu_dm_data *hw_data;

net/core/drop_monitor.c

451

hw_data = this_cpu_ptr(&dm_hw_cpu_data);

net/core/drop_monitor.c

452

raw_spin_lock_irqsave(&hw_data->lock, flags);

net/core/drop_monitor.c

453

hw_entries = hw_data->hw_entries;

net/core/drop_monitor.c

475

if (!timer_pending(&hw_data->send_timer)) {

net/core/drop_monitor.c

476

hw_data->send_timer.expires = jiffies + dm_delay * HZ;

net/core/drop_monitor.c

477

add_timer(&hw_data->send_timer);

net/core/drop_monitor.c

481

raw_spin_unlock_irqrestore(&hw_data->lock, flags);

net/core/drop_monitor.c

945

struct per_cpu_dm_data *hw_data;

net/core/drop_monitor.c

950

hw_data = container_of(work, struct per_cpu_dm_data, dm_alert_work);

net/core/drop_monitor.c

954

spin_lock_irqsave(&hw_data->drop_queue.lock, flags);

net/core/drop_monitor.c

955

skb_queue_splice_tail_init(&hw_data->drop_queue, &list);

net/core/drop_monitor.c

956

spin_unlock_irqrestore(&hw_data->drop_queue.lock, flags);

net/core/drop_monitor.c

969

struct per_cpu_dm_data *hw_data;

net/core/drop_monitor.c

990

hw_data = this_cpu_ptr(&dm_hw_cpu_data);

net/core/drop_monitor.c

992

spin_lock_irqsave(&hw_data->drop_queue.lock, flags);

net/core/drop_monitor.c

993

if (skb_queue_len(&hw_data->drop_queue) < net_dm_queue_len)

net/core/drop_monitor.c

994

__skb_queue_tail(&hw_data->drop_queue, nskb);

net/core/drop_monitor.c

997

spin_unlock_irqrestore(&hw_data->drop_queue.lock, flags);

net/core/drop_monitor.c

999

schedule_work(&hw_data->dm_alert_work);

sound/i2c/cs8427.c

108

char *hw_data = udata ?

sound/i2c/cs8427.c

113

if (!memcmp(hw_data, ndata, count))

sound/i2c/cs8427.c

118

memcpy(hw_data, ndata, count);

sound/i2c/cs8427.c

121

if (memcmp(hw_data, data, count) == 0) {

sound/mips/hal2.c

577

unsigned char *buf = hal2->dac.buffer + rec->hw_data;

sound/mips/hal2.c

581

hal2->dac.buffer_dma + rec->hw_data, bytes,

sound/mips/hal2.c

662

unsigned char *buf = hal2->adc.buffer + rec->hw_data;

sound/mips/hal2.c

665

hal2->adc.buffer_dma + rec->hw_data, bytes,

sound/pci/cs46xx/cs46xx_lib.c

865

memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);

sound/pci/cs46xx/cs46xx_lib.c

882

chip->capt.hw_buf.area + rec->hw_data, bytes);

sound/pci/rme32.c

1028

rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);

sound/pci/rme32.c

1031

rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);

sound/pci/rme32.c

1084

memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,

sound/pci/rme32.c

1109

rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,