drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2963

struct dml2_dchub_per_pipe_register_set *hubp_regs = params->hubp_setup2_params.hubp_regs;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2968

hubp->funcs->hubp_setup2(hubp, hubp_regs, global_sync, timing);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2995

struct dml2_dchub_per_pipe_register_set *hubp_regs = params->hubp_setup_interdependent2_params.hubp_regs;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2998

hubp->funcs->hubp_setup_interdependent2(hubp, hubp_regs);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3807

struct dml2_dchub_per_pipe_register_set *hubp_regs,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3814

seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3853

struct dml2_dchub_per_pipe_register_set *hubp_regs)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3858

seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent2_params.hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5698

det_segments += dpp_pipes[dpp_idx]->hubp_regs.det_size;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

221

memcpy(&pipe_ctx->hubp_regs, pln_prog->phantom_plane.pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

225

memcpy(&pipe_ctx->hubp_regs, pln_prog->pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set));

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1407

const struct dcn_mi_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1413

hubp1->hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

32

hubp1->hubp_regs->reg

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

855

const struct dcn_mi_registers *hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

934

const struct dcn_mi_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1711

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1717

hubp2->hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

38

hubp2->hubp_regs->reg

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

306

const struct dcn_hubp2_registers *hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

315

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

142

const struct dcn201_hubp_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

148

hubp201->hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

33

hubp201->hubp_regs->reg

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

119

const struct dcn201_hubp_registers *hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.h

128

const struct dcn201_hubp_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

39

hubp21->hubp_regs->reg

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

848

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

854

hubp21->hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

108

const struct dcn_hubp2_registers *hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.h

118

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

36

hubp2->hubp_regs->reg

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

664

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

670

hubp2->hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h

253

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

120

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

126

hubp2->hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

33

hubp2->hubp_regs->reg

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h

240

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

232

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

238

hubp2->hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

33

hubp2->hubp_regs->reg

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.h

66

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

228

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

234

hubp2->hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

31

hubp2->hubp_regs->reg

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.h

55

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1081

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1087

hubp2->hubp_regs = hubp_regs;

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

34

hubp2->hubp_regs->reg

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

321

const struct dcn_hubp2_registers *hubp_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1694

&pipe_ctx->hubp_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1714

&pipe_ctx->hubp_regs);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1957

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2175

dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2321

pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2745

&pipe_ctx->hubp_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2889

struct dml2_display_dlg_regs old_dlg_regs = old_pipe->hubp_regs.dlg_regs;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2890

struct dml2_display_ttu_regs old_ttu_regs = old_pipe->hubp_regs.ttu_regs;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2891

struct dml2_display_rq_regs old_rq_regs = old_pipe->hubp_regs.rq_regs;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2892

struct dml2_display_dlg_regs *new_dlg_regs = &new_pipe->hubp_regs.dlg_regs;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2893

struct dml2_display_ttu_regs *new_ttu_regs = &new_pipe->hubp_regs.ttu_regs;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2894

struct dml2_display_rq_regs *new_rq_regs = &new_pipe->hubp_regs.rq_regs;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3615

hwss_add_hubp_setup2(seq_state, hubp, &pipe_ctx->hubp_regs,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3630

hwss_add_hubp_setup_interdependent2(seq_state, hubp, &pipe_ctx->hubp_regs);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1918

struct dml2_dchub_per_pipe_register_set *hubp_regs,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1935

struct dml2_dchub_per_pipe_register_set *hubp_regs);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

643

struct dml2_dchub_per_pipe_register_set *hubp_regs;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

663

struct dml2_dchub_per_pipe_register_set *hubp_regs;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

492

struct dml2_dchub_per_pipe_register_set hubp_regs;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1024

&hubp_regs[inst], &hubp_shift, &hubp_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

421

static const struct dcn_mi_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

422

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

423

hubp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

424

hubp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

425

hubp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1242

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

525

static const struct dcn_hubp2_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

526

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

527

hubp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

528

hubp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

529

hubp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

530

hubp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

531

hubp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1026

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

523

static const struct dcn201_hubp_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1016

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

306

static const struct dcn_hubp2_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

307

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

308

hubp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

309

hubp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

310

hubp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1242

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

586

static const struct dcn_hubp2_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

587

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

588

hubp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

589

hubp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

590

hubp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

591

hubp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

592

hubp_regs(5)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1202

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

559

static const struct dcn_hubp2_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

560

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

561

hubp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

562

hubp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

563

hubp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

519

static const struct dcn_hubp2_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

520

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

521

hubp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

522

hubp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

523

hubp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

524

hubp_regs(4)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

542

if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

503

static const struct dcn_hubp2_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

504

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

505

hubp_regs(1)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

523

if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1538

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

633

static const struct dcn_hubp2_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

634

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

635

hubp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

636

hubp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

637

hubp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1596

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

640

static const struct dcn_hubp2_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

641

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

642

hubp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

643

hubp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

644

hubp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1539

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

632

static const struct dcn_hubp2_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

633

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

634

hubp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

635

hubp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

636

hubp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1531

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

627

static const struct dcn_hubp2_registers hubp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

628

hubp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

629

hubp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

630

hubp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

631

hubp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

489

static struct dcn_hubp2_registers hubp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

931

#define REG_STRUCT hubp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

938

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

486

static struct dcn_hubp2_registers hubp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

925

#define REG_STRUCT hubp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

932

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1614

#define REG_STRUCT hubp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1621

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

498

static struct dcn_hubp2_registers hubp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1594

#define REG_STRUCT hubp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1601

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

478

static struct dcn_hubp2_registers hubp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1601

#define REG_STRUCT hubp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1608

&hubp_regs[inst], &hubp_shift, &hubp_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

485

static struct dcn_hubp2_registers hubp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

466

static struct dcn_hubp2_registers hubp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

927

#define REG_STRUCT hubp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

934

&hubp_regs[inst], &hubp_shift, &hubp_mask))