gpu_read64
busy_cycles = gpu_read64(gpu, REG_A3XX_RBBM_PERFCTR_RBBM_1_LO);
return gpu_read64(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_LO);
busy_cycles = gpu_read64(gpu, REG_A4XX_RBBM_PERFCTR_RBBM_1_LO);
uint64_t addr = gpu_read64(gpu, REG_A5XX_UCHE_TRAP_LOG);
gpu_read64(gpu, REG_A5XX_CP_IB1_BASE),
gpu_read64(gpu, REG_A5XX_CP_IB2_BASE),
return gpu_read64(gpu, REG_A5XX_RBBM_ALWAYSON_COUNTER_LO);
busy_cycles = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_0_LO);
gpu_read64(gpu, REG_A6XX_CP_IB1_BASE),
gpu_read64(gpu, REG_A6XX_CP_IB2_BASE),
return gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER);
.ib1_base = gpu_read64(gpu, REG_A6XX_CP_IB1_BASE),
.ib2_base = gpu_read64(gpu, REG_A6XX_CP_IB2_BASE),
uint64_t val = gpu_read64(gpu, counter->counter_reg_lo);
read_poll_timeout(gpu_read64, val, cond, delay_us, timeout_us, false, \
read_poll_timeout_atomic(gpu_read64, val, cond, delay_us, timeout_us, \
u64 address = gpu_read64(gpu->iomem, GPU_FAULT_ADDR);
return gpu_read64(ptdev->gpu->iomem, GPU_TIMESTAMP_OFFSET);
gpu_read64(gpu->iomem, SHADER_READY),
gpu_read64(gpu->iomem, TILER_READY),
gpu_read64(gpu->iomem, L2_READY));
ptdev->gpu_info.gpu_features = gpu_read64(gpu_iomem, GPU_FEATURES);
ptdev->gpu_info.l2_present = gpu_read64(pwr_iomem, PWR_L2_PRESENT);
ptdev->gpu_info.tiler_present = gpu_read64(pwr_iomem, PWR_TILER_PRESENT);
ptdev->gpu_info.shader_present = gpu_read64(pwr_iomem, PWR_SHADER_PRESENT);
ptdev->gpu_info.shader_present = gpu_read64(gpu_iomem, GPU_SHADER_PRESENT);
ptdev->gpu_info.tiler_present = gpu_read64(gpu_iomem, GPU_TILER_PRESENT);
ptdev->gpu_info.l2_present = gpu_read64(gpu_iomem, GPU_L2_PRESENT);
addr = gpu_read64(mmu->iomem, AS_FAULTADDRESS(as));
drm_info(&ptdev->base, "PWR_STATUS: 0x%016llx", gpu_read64(pwr->iomem, PWR_STATUS));
drm_info(&ptdev->base, "L2_PRESENT: 0x%016llx", gpu_read64(pwr->iomem, PWR_L2_PRESENT));
drm_info(&ptdev->base, "L2_PWRTRANS: 0x%016llx", gpu_read64(pwr->iomem, PWR_L2_PWRTRANS));
drm_info(&ptdev->base, "L2_READY: 0x%016llx", gpu_read64(pwr->iomem, PWR_L2_READY));
drm_info(&ptdev->base, "TILER_PRESENT: 0x%016llx", gpu_read64(pwr->iomem, PWR_TILER_PRESENT));
drm_info(&ptdev->base, "TILER_PWRTRANS: 0x%016llx", gpu_read64(pwr->iomem, PWR_TILER_PWRTRANS));
drm_info(&ptdev->base, "TILER_READY: 0x%016llx", gpu_read64(pwr->iomem, PWR_TILER_READY));
drm_info(&ptdev->base, "SHADER_PRESENT: 0x%016llx", gpu_read64(pwr->iomem, PWR_SHADER_PRESENT));
drm_info(&ptdev->base, "SHADER_PWRTRANS: 0x%016llx", gpu_read64(pwr->iomem, PWR_SHADER_PWRTRANS));
drm_info(&ptdev->base, "SHADER_READY: 0x%016llx", gpu_read64(pwr->iomem, PWR_SHADER_READY));
if ((gpu_read64(pwr->iomem, ready_reg) & mask) == expected_val)
const u64 pwr_status = gpu_read64(pwr->iomem, PWR_STATUS);
const u64 pwr_status = gpu_read64(pwr->iomem, PWR_STATUS);
const u64 domain_ready = gpu_read64(pwr->iomem, get_domain_ready_reg(domain));
if (!(gpu_read64(pwr->iomem, PWR_STATUS) & PWR_STATUS_ALLOW_SOFT_RESET)) {
const u64 pwr_status = gpu_read64(pwr->iomem, PWR_STATUS);
const u32 pwr_status = gpu_read64(pwr->iomem, PWR_STATUS);