arch/mips/bcm47xx/prom.c

117

setup_8250_early_printk_port(CKSEG1ADDR(BCM47XX_SERIAL_ADDR), 0, 0);

arch/mips/bmips/setup.c

34

#define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))

arch/mips/boot/compressed/uart-16550.c

15

#define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset))

arch/mips/boot/compressed/uart-16550.c

20

#define PORT(offset) (CKSEG1ADDR(INGENIC_UART_BASE_ADDR) + (4 * offset))

arch/mips/boot/compressed/uart-16550.c

25

#define PORT(offset) (CKSEG1ADDR(EN75_UART_BASE) + (4 * (offset)))

arch/mips/cobalt/pci.c

38

.io_map_base = CKSEG1ADDR(GT_DEF_PCI0_IO_BASE),

arch/mips/cobalt/reset.c

20

#define RESET_PORT ((void __iomem *)CKSEG1ADDR(0x1c000000))

arch/mips/cobalt/setup.c

115

setup_8250_early_printk_port(CKSEG1ADDR(0x1c800000), 0, 0);

arch/mips/cobalt/setup.c

81

set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));

arch/mips/dec/ecc-berr.c

144

(void *)CKSEG1ADDR(address);

arch/mips/dec/ecc-berr.c

227

volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);

arch/mips/dec/ecc-berr.c

229

kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);

arch/mips/dec/ecc-berr.c

230

kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);

arch/mips/dec/ecc-berr.c

245

volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR);

arch/mips/dec/ecc-berr.c

246

volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);

arch/mips/dec/ecc-berr.c

248

kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR);

arch/mips/dec/ecc-berr.c

249

kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN);

arch/mips/dec/kn01-berr.c

150

volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);

arch/mips/dec/kn01-berr.c

177

volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);

arch/mips/dec/kn01-berr.c

49

volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);

arch/mips/dec/kn01-berr.c

62

volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE +

arch/mips/dec/kn02-irq.c

30

volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +

arch/mips/dec/kn02-irq.c

39

volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +

arch/mips/dec/kn02-irq.c

62

volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +

arch/mips/dec/kn02xa-berr.c

126

volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);

arch/mips/dec/kn02xa-berr.c

29

volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER);

arch/mips/dec/kn02xa-berr.c

30

volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR);

arch/mips/dec/kn02xa-berr.c

40

volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER);

arch/mips/dec/kn02xa-berr.c

41

volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR);

arch/mips/dec/prom/identify.c

100

ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL);

arch/mips/dec/prom/identify.c

101

dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY);

arch/mips/dec/prom/identify.c

110

ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL);

arch/mips/dec/prom/identify.c

111

dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY);

arch/mips/dec/prom/identify.c

74

dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC);

arch/mips/dec/prom/identify.c

82

dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC);

arch/mips/dec/prom/identify.c

91

dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN02_RTC);

arch/mips/dec/reset.c

17

noret_func_t func = (void *)CKSEG1ADDR(0x1fc00000);

arch/mips/econet/init.c

20

#define CR_AHB_RSTCR ((void __iomem *)CKSEG1ADDR(0x1fb00040))

arch/mips/econet/init.c

23

#define UART_BASE CKSEG1ADDR(0x1fbf0003)

arch/mips/fw/sni/sniprom.c

35

#define PROM_VEC (u64 *)CKSEG1ADDR(0x1fc00000)

arch/mips/fw/sni/sniprom.c

87

return (void *)CKSEG1ADDR(hwconf);

arch/mips/generic/board-sead3.c

19

#define SEAD_CONFIG CKSEG1ADDR(0x1b100110)

arch/mips/generic/board-sead3.c

22

#define MIPS_REVISION CKSEG1ADDR(0x1fc00010)

arch/mips/include/asm/barrier.h

56

: "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \

arch/mips/include/asm/dec/prom.h

22

#define VEC_RESET (u64 *)CKSEG1ADDR(0x1fc00000)

arch/mips/include/asm/mach-cobalt/mach-gt64120.h

12

#define GT64120_BASE CKSEG1ADDR(GT_DEF_BASE)

arch/mips/include/asm/mach-generic/spaces.h

53

#define CKSEG1ADDR_OR_64BIT(x) CKSEG1ADDR(x)

arch/mips/include/asm/mach-loongson2ef/loongson.h

65

(*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))

arch/mips/include/asm/mach-loongson64/loongson.h

67

(*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))

arch/mips/include/asm/sni.h

100

#define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0060)

arch/mips/include/asm/sni.h

101

#define PCIMT_ECCREG CKSEG1ADDR(0xbfff0068)

arch/mips/include/asm/sni.h

102

#define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0070)

arch/mips/include/asm/sni.h

103

#define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff0078) /* read */

arch/mips/include/asm/sni.h

104

#define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff0078) /* write */

arch/mips/include/asm/sni.h

105

#define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0080)

arch/mips/include/asm/sni.h

106

#define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff0088)

arch/mips/include/asm/sni.h

107

#define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0090)

arch/mips/include/asm/sni.h

108

#define PCIMT_CACHECONF CKSEG1ADDR(0xbfff0098)

arch/mips/include/asm/sni.h

109

#define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a0)

arch/mips/include/asm/sni.h

112

#define PCIMT_PCI_CONF CKSEG1ADDR(0xbfff0100)

arch/mips/include/asm/sni.h

122

#define PCIMT_CSMSR CKSEG1ADDR(0xbfd00000)

arch/mips/include/asm/sni.h

123

#define PCIMT_CSSWITCH CKSEG1ADDR(0xbfd10000)

arch/mips/include/asm/sni.h

124

#define PCIMT_CSITPEND CKSEG1ADDR(0xbfd20000)

arch/mips/include/asm/sni.h

125

#define PCIMT_AUTO_PO_EN CKSEG1ADDR(0xbfd30000)

arch/mips/include/asm/sni.h

126

#define PCIMT_CLR_TEMP CKSEG1ADDR(0xbfd40000)

arch/mips/include/asm/sni.h

127

#define PCIMT_AUTO_PO_DIS CKSEG1ADDR(0xbfd50000)

arch/mips/include/asm/sni.h

128

#define PCIMT_EXMSR CKSEG1ADDR(0xbfd60000)

arch/mips/include/asm/sni.h

129

#define PCIMT_UNUSED1 CKSEG1ADDR(0xbfd70000)

arch/mips/include/asm/sni.h

130

#define PCIMT_CSWCSM CKSEG1ADDR(0xbfd80000)

arch/mips/include/asm/sni.h

131

#define PCIMT_UNUSED2 CKSEG1ADDR(0xbfd90000)

arch/mips/include/asm/sni.h

132

#define PCIMT_CSLED CKSEG1ADDR(0xbfda0000)

arch/mips/include/asm/sni.h

133

#define PCIMT_CSMAPISA CKSEG1ADDR(0xbfdb0000)

arch/mips/include/asm/sni.h

134

#define PCIMT_CSRSTBP CKSEG1ADDR(0xbfdc0000)

arch/mips/include/asm/sni.h

135

#define PCIMT_CLRPOFF CKSEG1ADDR(0xbfdd0000)

arch/mips/include/asm/sni.h

136

#define PCIMT_CSTIMER CKSEG1ADDR(0xbfde0000)

arch/mips/include/asm/sni.h

137

#define PCIMT_PWDN CKSEG1ADDR(0xbfdf0000)

arch/mips/include/asm/sni.h

142

#define A20R_PT_CLOCK_BASE CKSEG1ADDR(0xbc040000)

arch/mips/include/asm/sni.h

143

#define A20R_PT_TIM0_ACK CKSEG1ADDR(0xbc050000)

arch/mips/include/asm/sni.h

144

#define A20R_PT_TIM1_ACK CKSEG1ADDR(0xbc060000)

arch/mips/include/asm/sni.h

149

#define SNI_PCIT_INT_REG CKSEG1ADDR(0xbfff000c)

arch/mips/include/asm/sni.h

191

#define PCIMT_EISA_BASE CKSEG1ADDR(0xb0000000)

arch/mips/include/asm/sni.h

194

#define PCIMT_INT_ACKNOWLEDGE CKSEG1ADDR(0xba000000)

arch/mips/include/asm/sni.h

209

#define SNI_IDPROM_BASE CKSEG1ADDR(0x1ff00000)

arch/mips/include/asm/sni.h

40

#define SNI_PORT_BASE CKSEG1ADDR(0xb4000000)

arch/mips/include/asm/sni.h

46

#define PCIMT_UCONF CKSEG1ADDR(0xbfff0004)

arch/mips/include/asm/sni.h

47

#define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff000c)

arch/mips/include/asm/sni.h

48

#define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0014)

arch/mips/include/asm/sni.h

49

#define PCIMT_IOMMU CKSEG1ADDR(0xbfff001c)

arch/mips/include/asm/sni.h

50

#define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0024)

arch/mips/include/asm/sni.h

51

#define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff002c)

arch/mips/include/asm/sni.h

52

#define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0034)

arch/mips/include/asm/sni.h

53

#define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff003c)

arch/mips/include/asm/sni.h

54

#define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0044)

arch/mips/include/asm/sni.h

55

#define PCIMT_SYNDROME CKSEG1ADDR(0xbfff004c)

arch/mips/include/asm/sni.h

56

#define PCIMT_ITPEND CKSEG1ADDR(0xbfff0054)

arch/mips/include/asm/sni.h

65

#define PCIMT_IRQSEL CKSEG1ADDR(0xbfff005c)

arch/mips/include/asm/sni.h

66

#define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0064)

arch/mips/include/asm/sni.h

67

#define PCIMT_ECCREG CKSEG1ADDR(0xbfff006c)

arch/mips/include/asm/sni.h

68

#define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0074)

arch/mips/include/asm/sni.h

69

#define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff007c) /* read */

arch/mips/include/asm/sni.h

70

#define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff007c) /* write */

arch/mips/include/asm/sni.h

71

#define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0084)

arch/mips/include/asm/sni.h

72

#define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff008c)

arch/mips/include/asm/sni.h

73

#define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0094)

arch/mips/include/asm/sni.h

74

#define PCIMT_CACHECONF CKSEG1ADDR(0xbfff009c)

arch/mips/include/asm/sni.h

75

#define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a4)

arch/mips/include/asm/sni.h

80

#define PCIMT_UCONF CKSEG1ADDR(0xbfff0000)

arch/mips/include/asm/sni.h

81

#define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff0008)

arch/mips/include/asm/sni.h

82

#define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0010)

arch/mips/include/asm/sni.h

83

#define PCIMT_IOMMU CKSEG1ADDR(0xbfff0018)

arch/mips/include/asm/sni.h

84

#define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0020)

arch/mips/include/asm/sni.h

85

#define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff0028)

arch/mips/include/asm/sni.h

86

#define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0030)

arch/mips/include/asm/sni.h

87

#define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff0038)

arch/mips/include/asm/sni.h

88

#define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0040)

arch/mips/include/asm/sni.h

89

#define PCIMT_SYNDROME CKSEG1ADDR(0xbfff0048)

arch/mips/include/asm/sni.h

90

#define PCIMT_ITPEND CKSEG1ADDR(0xbfff0050)

arch/mips/include/asm/sni.h

99

#define PCIMT_IRQSEL CKSEG1ADDR(0xbfff0058)

arch/mips/include/asm/vga.h

19

#define VGA_MAP_MEM(x, s) CKSEG1ADDR(0x10000000L + (unsigned long)(x))

arch/mips/jazz/jazzdma.c

75

pgtbl = (VDMA_PGTBL_ENTRY *)CKSEG1ADDR((unsigned long)pgtbl);

arch/mips/kernel/smp-cps.c

129

UASM_i_LA(&p, GPR_T9, CKSEG1ADDR(__pa_symbol(mips_cps_core_boot)));

arch/mips/kernel/smp-cps.c

162

core_entry_reg = CKSEG1ADDR(cps_vec_pa) &

arch/mips/kvm/vz.c

3213

vcpu->arch.pc = CKSEG1ADDR(0x1fc00000);

arch/mips/lib/uncached.c

48

usp = CKSEG1ADDR(sp);

arch/mips/lib/uncached.c

60

ufunc = CKSEG1ADDR(lfunc);

arch/mips/loongson64/smp.c

767

(void *)CKSEG1ADDR((unsigned long)loongson3_type3_play_dead);

arch/mips/loongson64/smp.c

775

(void *)CKSEG1ADDR((unsigned long)loongson3_type1_play_dead);

arch/mips/loongson64/smp.c

780

(void *)CKSEG1ADDR((unsigned long)loongson3_type2_play_dead);

arch/mips/loongson64/smp.c

787

(void *)CKSEG1ADDR((unsigned long)loongson3_type3_play_dead);

arch/mips/mm/ioremap.c

73

return (void __iomem *) CKSEG1ADDR(phys_addr);

arch/mips/mti-malta/malta-dtshim.c

194

config = readl((void __iomem *)CKSEG1ADDR(ROCIT_CONFIG_GEN1));

arch/mips/mti-malta/malta-setup.c

119

cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0));

arch/mips/n64/init.c

53

#define REG_BASE ((u32 *) CKSEG1ADDR(0x4400000))

arch/mips/pci/ops-bonito64.c

19

#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset))

arch/mips/pci/ops-loongson2.c

27

(void *)CKSEG1ADDR(LOONGSON_PCICFG_BASE | (offset))

arch/mips/pci/pci-ip32.c

121

.io_map_base = CKSEG1ADDR(MACEPCI_LOW_IO),

arch/mips/sgi-ip22/ip22-gio.c

275

ptr32 = (void *)CKSEG1ADDR(addr);

arch/mips/sgi-ip22/ip22-gio.c

285

ptr8 = (void *)CKSEG1ADDR(addr + 3);

arch/mips/sgi-ip22/ip22-gio.c

296

ptr16 = (void *)CKSEG1ADDR(addr + 2);

arch/mips/sgi-ip22/ip22-gio.c

317

ptr = (void *)CKSEG1ADDR(addr + HQ2_MYSTERY_OFFS);

arch/mips/sni/rm200.c

415

#define SNI_RM200_INT_STAT_REG CKSEG1ADDR(0xbc000000)

arch/mips/sni/rm200.c

416

#define SNI_RM200_INT_ENA_REG CKSEG1ADDR(0xbc080000)

drivers/bus/mips_cdmm.c

435

bus->regs = (void __iomem *)CKSEG1ADDR(bus->phys);

drivers/mtd/devices/ms02-nv.c

277

csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);

drivers/mtd/devices/ms02-nv.c

283

csr = (volatile u32 *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR);

drivers/mtd/devices/ms02-nv.c

88

ms02nv_diagp = (ms02nv_uint *)(CKSEG1ADDR(addr + MS02NV_DIAG));

drivers/mtd/devices/ms02-nv.c

89

ms02nv_magicp = (ms02nv_uint *)(CKSEG1ADDR(addr + MS02NV_MAGIC));

drivers/net/ethernet/amd/declance.c

1070

dev->base_addr = CKSEG1ADDR(dec_kn_slot_base + IOASIC_LANCE);

drivers/net/ethernet/amd/declance.c

1076

dev->mem_start = CKSEG1ADDR(0x00020000);

drivers/net/ethernet/amd/declance.c

1079

esar_base = CKSEG1ADDR(dec_kn_slot_base + IOASIC_ESAR);

drivers/net/ethernet/amd/declance.c

1126

dev->mem_start = CKSEG1ADDR(start);

drivers/net/ethernet/amd/declance.c

1155

dev->base_addr = CKSEG1ADDR(KN01_SLOT_BASE + KN01_LANCE);

drivers/net/ethernet/amd/declance.c

1156

dev->mem_start = CKSEG1ADDR(KN01_SLOT_BASE + KN01_LANCE_MEM);

drivers/net/ethernet/amd/declance.c

1158

esar_base = CKSEG1ADDR(KN01_SLOT_BASE + KN01_ESAR + 1);