get_msr
KVM_X86_OP(get_msr)
KVM_X86_PMU_OP(get_msr)
int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr);
ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
if (ctxt->ops->get_msr(ctxt, MSR_EFER, &efer))
if (ctxt->ops->get_msr(ctxt, MSR_IA32_X_CET, &cet))
if (ctxt->ops->get_msr(ctxt, MSR_KVM_INTERNAL_GUEST_SSP, &ssp))
ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
ops->get_msr(ctxt, MSR_EFER, &efer);
ops->get_msr(ctxt, MSR_STAR, &msr_data);
ops->get_msr(ctxt,
ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
ops->get_msr(ctxt, MSR_STAR, &msr_data);
ops->get_msr(ctxt, MSR_EFER, &efer);
ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
ctxt->ops->get_msr(ctxt, MSR_TSC_AUX, &tsc_aux);
ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
ctxt->ops->get_msr(ctxt, MSR_MISC_FEATURES_ENABLES, &msr);
ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
if ((u_cet && ctxt->ops->get_msr(ctxt, MSR_IA32_U_CET, &u_cet)) ||
(s_cet && ctxt->ops->get_msr(ctxt, MSR_IA32_S_CET, &s_cet)))
ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
int (*get_msr)(struct x86_emulate_ctxt *ctxt, u32 msr_index, u64 *pdata);
return kvm_pmu_call(get_msr)(vcpu, msr_info);
int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
.get_msr = amd_pmu_get_msr,
.get_msr = svm_get_msr,
.get_msr = vt_op(get_msr),
.get_msr = intel_pmu_get_msr,
ret = kvm_x86_call(get_msr)(vcpu, &msr);
.get_msr = emulator_get_msr,
if (get_msr(cpu, mp->msr_num, counterp))
get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr);
if (get_msr(cpu, rci->msr[i], &rci->data[i]))
if (get_msr(cpu, cci->msr[i], &cci->data[i]))
if (get_msr(cpu, mci->msr[i], &mci->data[i]))
if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us))
if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0))
if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0))
if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0))
if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0))
if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
get_msr(master_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
get_msr(master_cpu, MSR_PLATFORM_INFO, &msr);
get_msr(master_cpu, MSR_IA32_POWER_CTL, &msr);
get_msr(master_cpu, MSR_TURBO_RATIO_LIMIT2, &msr);
get_msr(master_cpu, MSR_TURBO_RATIO_LIMIT1, &msr);
get_msr(master_cpu, trl_msr_offset, &msr);
get_msr(master_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts);
get_msr(master_cpu, MSR_ATOM_CORE_RATIOS, &msr);
get_msr(master_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr);
get_msr(master_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
get_msr(master_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
get_msr(master_cpu, MSR_CONFIG_TDP_NOMINAL, &msr);
get_msr(master_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr);
int get_msr(int cpu, off_t offset, unsigned long long *msr);
get_msr(master_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr);
get_msr(master_cpu, MSR_CONFIG_TDP_CONTROL, &msr);
get_msr(master_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr);
get_msr(master_cpu, MSR_PKGC3_IRTL, &msr);
get_msr(master_cpu, MSR_PKGC6_IRTL, &msr);
get_msr(master_cpu, MSR_PKGC7_IRTL, &msr);
get_msr(master_cpu, MSR_PKGC8_IRTL, &msr);
get_msr(master_cpu, MSR_PKGC9_IRTL, &msr);
get_msr(master_cpu, MSR_PKGC10_IRTL, &msr);
if (get_msr(master_cpu, MSR_FSB_FREQ, &msr))
ret = get_msr(cpu, offset, &msr_cur);
ret = get_msr(cpu, offset, &msr_cur);
get_msr(master_cpu, MSR_PLATFORM_INFO, &msr);
if (get_msr(cpu, MSR_PM_ENABLE, &msr))
if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr))
if (get_msr(cpu, MSR_HWP_REQUEST, &msr))
if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr))
if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr))
if (get_msr(cpu, MSR_HWP_STATUS, &msr))
get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr);
get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr);
get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr);
if (!get_msr(master_cpu, MSR_PKG_POWER_INFO, &msr))
if (get_msr(master_cpu, MSR_RAPL_POWER_UNIT, &msr))
if (get_msr(master_cpu, MSR_RAPL_PWR_UNIT, &msr))
if (get_msr(cpu, MSR_RAPL_PWR_UNIT, &msr))
if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr))
if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr))
if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr))
if (get_msr(cpu, MSR_VR_CURRENT_CONFIG, &msr))
if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr))
if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr))
if (get_msr(cpu, MSR_PP0_POLICY, &msr))
if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr))
if (get_msr(cpu, MSR_PP1_POLICY, &msr))
if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr))
ret = get_msr(master_cpu, offset, &msr_value);
if (get_msr(master_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr))
if (bits && !get_msr(master_cpu, MSR_PLATFORM_INFO, &enabled))
if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr))
if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr))
if (!get_msr(master_cpu, MSR_IA32_FEAT_CTL, &msr))
if (!get_msr(master_cpu, MSR_IA32_MISC_ENABLE, &msr))
if (!get_msr(master_cpu, MSR_MISC_FEATURE_CONTROL, &msr))
if (!get_msr(master_cpu, MSR_MISC_PWR_MGMT, &msr))
if (!get_msr(master_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr))
if (!get_msr(master_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr))
if (get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch))
get_msr(cpu, MSR_PM_ENABLE, &old_msr);
get_msr(cpu, MSR_IA32_MISC_ENABLE, &msr);
get_msr(cpu_num, MSR_PM_ENABLE, &msr);
get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
get_msr(cpu, msr_offset, &msr);
get_msr(cpu, msr_offset, &msr);
get_msr(first_cpu_in_pkg[pkg], MSR_HWP_INTERRUPT, &msr);
get_msr(first_cpu_in_pkg[pkg], MSR_HWP_STATUS, &msr);