field_get
priority = field_get(GENMASK(pri_bit + 4, pri_bit), priorityr);
gck->parent_id = field_get(gck->layout->gckcss_mask, tmp);
periph->div = field_get(periph->layout->div_mask, status);
hw_index = field_get(clock->src_mask, readl(clock->reg));
unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg));
unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg));
field_get(table[i].field_mask,
field_get(cfg->reg_eccerrlog_rank_mask, log),
field_get(cfg->reg_eccerrlog_syndrome_mask, log),
field_get(cfg->reg_eccerrlog_rank_mask, log),
dd->size = field_get(cfg->reg_mad_dimm_size_mask[dimm], addr_decode) * cfg->reg_mad_dimm_size_granularity;
dd->ranks = field_get(cfg->reg_mad_dimm_rank_mask[dimm], addr_decode) + 1;
dd->dtype = field_get(cfg->reg_mad_dimm_width_mask[dimm], addr_decode) + DEV_X8;
return field_get(res_cfg->reg_eccerrlog_addr_mask, ecclog);
mtype = field_get(res_cfg->reg_mem_config_ddr_type_mask, val);
width = field_get(res_cfg->reg_mad_intra_width_mask[dimm], val);
return field_get(res_cfg->reg_mad_inter_size_mask[chan], val) *
u32 ranks = 1 << field_get(res_cfg->reg_mad_intra_rank_mask[dimm], val);
u64 density = field_get(res_cfg->reg_mad_intra_density_mask[dimm], val) * 4;
return field_get(mask, ioread32(addr));
return field_get(mask, ioread32(addr));
val = field_get(LTC4283_PGIO_CFG_MASK(off), val);
if (!field_get(NXP_SAR_ADC_EOC_CH(chan), ceocfr))
*val = !field_get(AD3552R_MASK_CH_DAC_POWERDOWN(ch), tmp_val);
reg_val = field_get(attr->mask, reg_val);
idx = field_get(chip_info->iir_config_mask, ret) -
tssr_cur = field_get(ICU_TSSR_TSSEL_MASK(tssel_n, priv->info->field_width), tssr);
titsr_cur = field_get(ICU_TITSR_TITSEL_MASK(titsel_n), titsr);
dev_dbg(sec_pmic->dev, "Revision: 0x%x\n", field_get(mask, val));
pattern_found = field_get(NFC_ECC_PAT_FOUND_MSK(nfc), pattern_found);
pattern_found = field_get(NFC_ECC_PAT_FOUND_MSK(nfc), pattern_found);
*frame_type = field_get(RTL8365MB_VLAN_ACCEPT_FRAME_TYPE_MASK(port),
rgsmii = field_get(spcs->rgsmii_status_mask,
*value = field_get(mask, *value);
pmac->cnt_cck_crc32_ok = field_get(regs->cck_crc32_ok_mask, val);
pmac->cnt_cck_crc32_error = field_get(regs->cck_crc32_fail_mask, val);
pmac->ofdm_phy_txon = field_get(regs->ofdm_txon_mask, val);
pmac->ofdm_mac_txen = field_get(regs->ofdm_txen_mask, val);
pmac->cnt_ofdm_crc32_ok = field_get(regs->l_crc_ok_mask, val);
pmac->cnt_ofdm_crc32_error = field_get(regs->l_crc_err_mask, val);
pmac->cnt_ht_crc32_ok = field_get(regs->ht_crc_ok_mask, val);
pmac->cnt_ht_crc32_error = field_get(regs->ht_crc_err_mask, val);
pmac->cnt_vht_crc32_ok = field_get(regs->vht_crc_ok_mask, val);
pmac->cnt_vht_crc32_error = field_get(regs->vht_crc_err_mask, val);
pmac->cnt_he_crc32_ok = field_get(regs->he_crc_ok_mask, val);
pmac->cnt_he_crc32_error = field_get(regs->he_crc_err_mask, val);
pmac->cnt_eht_crc32_ok = field_get(regs->eht_crc_ok_mask, val);
pmac->cnt_eht_crc32_error = field_get(regs->eht_crc_err_mask, val);
pmac->cnt_ampdu_crc_ok = field_get(regs->ampdu_crc_ok_mask, val);
pmac->cnt_ampdu_crc_error = field_get(regs->ampdu_crc_err_mask, val);
return field_get(MA35_GP_MODE_MASK(gpio), regval);
pull_sel = field_get(MA35_GP_PUSEL_MASK(port), regval);
ds_val = field_get(MA35_GP_DS_MASK(port), regval);
return field_get(MA35_GP_SLEWCTL_MASK(port), regval);
val = field_get(mask, val);
field_get(PFC_PIN_MASK(pin), reg64) == func)
arg = field_get(DRCTL_SR_PIN_MASK(port_pin), drctl);
arg = field_get(DRCTL_PUD_PIN_MASK(port_pin), drctl);
arg = field_get(DRCTL_SMT_PIN_MASK(port_pin), drctl);
arg = field_get(DRCTL_DRV_PIN_MASK(port_pin), drctl);
*conf = field_get(mask, readl_relaxed(pctrl->base + reg_offset));
if (soc->id && field_get(id->mask, product) != soc->id) {
revision = field_get(soc_data->revision_mask, val);
specific_id = field_get(soc_data->specific_id_mask, val);
return field_get(mask, val);