arch/mips/ath25/ar2315.c

207

unsigned int pllc_out, refdiv, fdiv, divby2;

arch/mips/ath25/ar2315.c

213

fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV);

arch/mips/ath25/ar2315.c

215

pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv;

arch/powerpc/include/asm/kvm_fpu.h

60

FPD_TWO_IN(fdiv)

arch/powerpc/math-emu/math.c

287

case FDIV: func = fdiv; type = AB; break;

arch/powerpc/math-emu/math.c

34

FLOATFUNC(fdiv);

arch/sh/math-emu/math.c

399

fadd, fsub, fmul, fdiv, fcmp_eq, fcmp_gt, fmov_idx_reg, fmov_reg_idx,

drivers/clk/bcm/clk-bcm2835.c

549

u32 *ndiv, u32 *fdiv)

drivers/clk/bcm/clk-bcm2835.c

557

*fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);

drivers/clk/bcm/clk-bcm2835.c

561

u32 ndiv, u32 fdiv, u32 pdiv)

drivers/clk/bcm/clk-bcm2835.c

568

rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv);

drivers/clk/bcm/clk-bcm2835.c

578

u32 ndiv, fdiv;

drivers/clk/bcm/clk-bcm2835.c

583

&ndiv, &fdiv);

drivers/clk/bcm/clk-bcm2835.c

586

ndiv, fdiv,

drivers/clk/bcm/clk-bcm2835.c

599

u32 ndiv, pdiv, fdiv;

drivers/clk/bcm/clk-bcm2835.c

605

fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK;

drivers/clk/bcm/clk-bcm2835.c

613

fdiv *= 2;

drivers/clk/bcm/clk-bcm2835.c

616

return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);

drivers/clk/bcm/clk-bcm2835.c

694

u32 ndiv, fdiv, a2w_ctl;

drivers/clk/bcm/clk-bcm2835.c

705

bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv);

drivers/clk/bcm/clk-bcm2835.c

740

cprman_write(cprman, data->frac_reg, fdiv);

drivers/clk/samsung/clk-pll.c

1288

u32 pdiv, sdiv, fdiv, pll_con0, pll_con8;

drivers/clk/samsung/clk-pll.c

1296

fdiv = (pll_con8 & PLL531X_FDIV_MASK);

drivers/clk/samsung/clk-pll.c

1298

if (fdiv >> 31)

drivers/clk/samsung/clk-pll.c

1301

fout *= (mdiv << 24) + (fdiv >> 8);

drivers/clk/socfpga/clk-pll-s10.c

44

unsigned long fdiv, reg, rdiv, qdiv;

drivers/clk/socfpga/clk-pll-s10.c

49

fdiv = (reg & SOCFPGA_N5X_PLLDIV_FDIV_MASK) >> SOCFPGA_N5X_PLLDIV_FDIV_SHIFT;

drivers/clk/socfpga/clk-pll-s10.c

58

return ((parent_rate * 2 * (fdiv + 1)) / ((rdiv + 1) * power));

drivers/clk/st/clk-flexgen.c

144

struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;

drivers/clk/st/clk-flexgen.c

160

struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;

drivers/clk/st/clk-flexgen.c

254

fgxbar->fdiv.lock = lock;

drivers/clk/st/clk-flexgen.c

255

fgxbar->fdiv.reg = fdiv_reg;

drivers/clk/st/clk-flexgen.c

256

fgxbar->fdiv.width = 6;

drivers/clk/st/clk-flexgen.c

43

struct clk_divider fdiv;

drivers/media/tuners/it913x.c

20

u8 fdiv;

drivers/media/tuners/it913x.c

274

t_cal_freq = (c->frequency / 1000) * n_div * dev->fdiv;

drivers/media/tuners/it913x.c

53

dev->fdiv = 3;

drivers/media/tuners/it913x.c

60

dev->fdiv = 1;

drivers/media/tuners/it913x.c

95

dev->fn_min /= (dev->fdiv * nv_val);

drivers/spi/spi-xlp.c

138

u32 fdiv, cfg;

drivers/spi/spi-xlp.c

146

fdiv = DIV_ROUND_UP(xspi->spi_clk, spi->max_speed_hz);

drivers/spi/spi-xlp.c

147

if (fdiv > XLP_SPI_FDIV_MAX)

drivers/spi/spi-xlp.c

148

fdiv = XLP_SPI_FDIV_MAX;

drivers/spi/spi-xlp.c

149

else if (fdiv < XLP_SPI_FDIV_MIN)

drivers/spi/spi-xlp.c

150

fdiv = XLP_SPI_FDIV_MIN;

drivers/spi/spi-xlp.c

152

xlp_spi_reg_write(xspi, cs, XLP_SPI_FDIV, fdiv);

drivers/spi/spi-xlp.c

173

if (fdiv == 4)

drivers/tty/serial/max310x.c

566

unsigned long fdiv, fmul, bestfreq = freq;

drivers/tty/serial/max310x.c

573

fdiv = DIV_ROUND_CLOSEST(freq, div);

drivers/tty/serial/max310x.c

576

fmul = fdiv * 6;

drivers/tty/serial/max310x.c

577

if ((fdiv >= 500000) && (fdiv <= 800000))

drivers/tty/serial/max310x.c

583

fmul = fdiv * 48;

drivers/tty/serial/max310x.c

584

if ((fdiv >= 850000) && (fdiv <= 1200000))

drivers/tty/serial/max310x.c

590

fmul = fdiv * 96;

drivers/tty/serial/max310x.c

591

if ((fdiv >= 425000) && (fdiv <= 1000000))

drivers/tty/serial/max310x.c

597

fmul = fdiv * 144;

drivers/tty/serial/max310x.c

598

if ((fdiv >= 390000) && (fdiv <= 667000))