ehci_readl
saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
temp = ehci_readl(ehci, portsc_reg);
temp = ehci_readl(ehci, portsc_reg);
temp = ehci_readl(ehci, &ehci->regs->status);
temp = ehci_readl(ehci, status_reg);
temp = ehci_readl(ehci, status_reg);
u32 portsc = ehci_readl(ehci, reg);
tmp = ehci_readl(ehci, &ehci->regs->command);
tmp = ehci_readl(ehci, reg);
len = HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
u32 frame_idx = ehci_readl(ehci, &ehci->regs->frame_index);
(ehci_readl(ehci, status_reg) & PORT_RESUME)) {
u32 params = ehci_readl(ehci, &ehci->caps->hcs_params);
u32 params = ehci_readl(ehci, &ehci->caps->hcc_params);
i = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
offset = HCC_EXT_CAPS(ehci_readl(ehci,
i = ehci_readl(ehci, &ehci->caps->hcs_params);
i = ehci_readl(ehci, &ehci->caps->hcc_params);
ehci_readl(ehci, &ehci->regs->status));
ehci_readl(ehci, &ehci->regs->command));
ehci_readl(ehci, &ehci->regs->intr_enable));
ehci_readl(ehci,
ehci_readl(ehci,
portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */
tmp = ehci_readl(ehci, &ehci->regs->command);
pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
pdata->pm_status = ehci_readl(ehci, &ehci->regs->status);
pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable);
pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index);
pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment);
pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list);
pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next);
ehci_readl(ehci, &ehci->regs->configured_flag);
pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
pdata->pm_usbgenctrl = ehci_readl(ehci,
tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
tmp = ehci_readl(ehci, &ehci->regs->command);
hc_capbase = ehci_readl(ehci, &ehci->caps->hc_capbase);
u32 t1 = ehci_readl(ehci, reg);
t1 = ehci_readl(ehci, reg);
ehci_readl(ehci, reg);
t1 = ehci_readl(ehci, reg);
ehci_readl(ehci, reg);
(void) ehci_readl(ehci, &ehci->regs->intr_enable);
uf = ehci_readl(ehci, &ehci->regs->frame_index);
uf = ehci_readl(ehci, &ehci->regs->frame_index);
if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
ehci_readl(ehci, &ehci->regs->intr_enable);
ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
return ehci_readl(ehci, &ehci->regs->frame_index);
result = ehci_readl(ehci, ptr);
tmp = ehci_readl(ehci, &ehci->regs->usbmode);
temp = ehci_readl(ehci, &ehci->regs->command);
tmp = ehci_readl(ehci, &ehci->regs->usbmode);
u32 command = ehci_readl(ehci, &ehci->regs->command);
ehci_readl(ehci, &ehci->regs->configured_flag);
ehci_readl(ehci, &ehci->regs->status));
hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
current_status = ehci_readl(ehci, &ehci->regs->status);
current_status = ehci_readl(ehci, &ehci->regs->status);
cmd = ehci_readl(ehci, &ehci->regs->command);
pstatus = ehci_readl(ehci,
temp = ehci_readl(ehci, status_reg);
temp1 = ehci_readl(ehci, hostpc_reg);
temp1 = ehci_readl(ehci, hostpc_reg);
status = ehci_readl(ehci, reg) & ~PORT_RWC_BITS;
temp = ehci_readl(ehci, sreg) & ~PORT_RWC_BITS;
temp = ehci_readl(ehci, status_reg);
ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
return ehci_readl(ehci, reg) & PORT_OWNER;
u32 temp = ehci_readl(ehci, status_reg) & ~PORT_RWC_BITS;
if (ehci_readl(ehci, &ehci->regs->status) & STS_PCD)
if (ehci_readl(ehci, &ehci->regs->port_status[i]) & PORT_CSC)
temp = ehci_readl(ehci, hostpc_reg);
u32 t1 = ehci_readl(ehci, reg) & ~PORT_RWC_BITS;
temp = ehci_readl(ehci, hostpc_reg);
u32 t1 = ehci_readl(ehci, reg) & ~PORT_RWC_BITS;
t3 = ehci_readl(ehci, hostpc_reg);
t3 = ehci_readl(ehci, hostpc_reg);
ehci_readl(ehci, &ehci->regs->intr_enable);
power_okay = ehci_readl(ehci, &ehci->regs->intr_enable);
temp = ehci_readl(ehci, &ehci->regs->port_status[i]);
temp = ehci_readl(ehci, hostpc_reg);
temp = ehci_readl(ehci, &ehci->regs->port_status [i]);
temp = ehci_readl(ehci, &ehci->regs->port_status [i]);
(void) ehci_readl(ehci, &ehci->regs->intr_enable);
port_status = ehci_readl(ehci, status_reg);
status = ehci_readl(ehci, reg) & ~PORT_RWC_BITS;
ppcd = ehci_readl(ehci, &ehci->regs->status) >> 16;
temp = ehci_readl(ehci, &ehci->regs->port_status[i]);
status = ehci_readl(ehci, reg) & ~PORT_RWC_BITS;
temp = ehci_readl(ehci, status_reg);
temp1 = ehci_readl(ehci, hostpc_reg);
ehci_readl(ehci, &ehci->regs->command); /* unblock posted write */
temp = ehci_readl(ehci, status_reg);
temp = ehci_readl(ehci, status_reg);
temp = ehci_readl(ehci, status_reg);
ehci_readl(ehci, status_reg));
temp = ehci_readl(ehci, status_reg);
temp1 = ehci_readl(ehci, hostpc_reg);
status = ehci_readl(ehci, &ehci->regs->port_status[0]);
status = ehci_readl(ehci, &ehci->regs->port_status[0]);
u32 hcs_params = ehci_readl(ehci,
temp = ehci_readl(ehci, &ehci->debug->control);
u32 port_status = ehci_readl(ehci, &ehci->regs->port_status[0]);
ehci_readl(ehci, &ehci->regs->command);
actual = ehci_readl(ehci, &ehci->regs->status) & STS_ASS;
actual = ehci_readl(ehci, &ehci->regs->status) & STS_PSS;
ehci_readl(ehci, &ehci->regs->command);
if (!(ehci_readl(ehci, &ehci->regs->status) & STS_HALT)) {
ehci_readl(ehci, &ehci->regs->command);
cmd = ehci_readl(ehci, &ehci->regs->command);
status = ehci_readl(ehci, &ehci->regs->status);