dwmac4_addrs
.dwmac4_addrs = {
.dwmac4_addrs = {
plat_dat->dwmac4_addrs = &data->dwmac4_addrs;
struct dwmac4_addrs dwmac4_addrs;
static inline u32 mtl_chanx_base_addr(const struct dwmac4_addrs *addrs,
static inline u32 mtl_etsx_ctrl_base_addr(const struct dwmac4_addrs *addrs,
static inline u32 mtl_txqx_weight_base_addr(const struct dwmac4_addrs *addrs,
static inline u32 mtl_send_slp_credx_base_addr(const struct dwmac4_addrs *addrs,
static inline u32 mtl_high_credx_base_addr(const struct dwmac4_addrs *addrs,
static inline u32 mtl_low_credx_base_addr(const struct dwmac4_addrs *addrs,
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
u32 value = readl(ioaddr + mtl_txqx_weight_base_addr(dwmac4_addrs,
writel(value, ioaddr + mtl_txqx_weight_base_addr(dwmac4_addrs, queue));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
value = readl(ioaddr + mtl_etsx_ctrl_base_addr(dwmac4_addrs, queue));
writel(value, ioaddr + mtl_etsx_ctrl_base_addr(dwmac4_addrs, queue));
value = readl(ioaddr + mtl_send_slp_credx_base_addr(dwmac4_addrs,
writel(value, ioaddr + mtl_send_slp_credx_base_addr(dwmac4_addrs,
value = readl(ioaddr + mtl_high_credx_base_addr(dwmac4_addrs, queue));
writel(value, ioaddr + mtl_high_credx_base_addr(dwmac4_addrs, queue));
value = readl(ioaddr + mtl_low_credx_base_addr(dwmac4_addrs, queue));
writel(value, ioaddr + mtl_low_credx_base_addr(dwmac4_addrs, queue));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(dwmac4_addrs,
ioaddr + MTL_CHAN_INT_CTRL(dwmac4_addrs, chan));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
value = readl(ioaddr + MTL_CHAN_TX_DEBUG(dwmac4_addrs, queue));
value = readl(ioaddr + MTL_CHAN_RX_DEBUG(dwmac4_addrs, queue));
writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
const struct dwmac4_addrs *default_addrs = NULL;
readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, channel));
readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, channel));
readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, channel));
readl(ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(dwmac4_addrs, channel));
readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(dwmac4_addrs, channel));
readl(ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(dwmac4_addrs, channel));
readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(dwmac4_addrs, channel));
readl(ioaddr + DMA_CHAN_TX_END_ADDR(dwmac4_addrs, channel));
readl(ioaddr + DMA_CHAN_RX_END_ADDR(dwmac4_addrs, channel));
readl(ioaddr + DMA_CHAN_TX_RING_LEN(dwmac4_addrs, channel));
readl(ioaddr + DMA_CHAN_RX_RING_LEN(dwmac4_addrs, channel));
readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, channel));
readl(ioaddr + DMA_CHAN_RX_WATCHDOG(dwmac4_addrs, channel));
readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(dwmac4_addrs, channel));
readl(ioaddr + DMA_CHAN_CUR_TX_DESC(dwmac4_addrs, channel));
readl(ioaddr + DMA_CHAN_CUR_RX_DESC(dwmac4_addrs, channel));
readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR_HI(dwmac4_addrs, channel));
readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(dwmac4_addrs, channel));
readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR_HI(dwmac4_addrs, channel));
readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(dwmac4_addrs, channel));
readl(ioaddr + DMA_CHAN_STATUS(dwmac4_addrs, channel));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(dwmac4_addrs, queue));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(dwmac4_addrs, channel));
writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(dwmac4_addrs, channel));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs,
writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs, channel));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs,
writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs, channel));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs,
value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(dwmac4_addrs, chan));
ioaddr + DMA_CHAN_RX_BASE_ADDR(dwmac4_addrs, chan));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(dwmac4_addrs, chan));
ioaddr + DMA_CHAN_TX_BASE_ADDR(dwmac4_addrs, chan));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
writel(len, ioaddr + DMA_CHAN_TX_RING_LEN(dwmac4_addrs, chan));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
writel(len, ioaddr + DMA_CHAN_RX_RING_LEN(dwmac4_addrs, chan));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
u32 intr_status = readl(ioaddr + DMA_CHAN_STATUS(dwmac4_addrs, chan));
u32 intr_en = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
ioaddr + DMA_CHAN_STATUS(dwmac4_addrs, chan));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
writel(tail_ptr, ioaddr + DMA_CHAN_RX_END_ADDR(dwmac4_addrs, chan));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
writel(tail_ptr, ioaddr + DMA_CHAN_TX_END_ADDR(dwmac4_addrs, chan));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
const struct dwmac4_addrs *dwmac4_addrs;