A2
STS_BIT(regs, A2), STS_BIT(regs, A1),
int A2[3];
rq[A2] = create_rewinder(ce, NULL, slot, Y);
if (IS_ERR(rq[A2]))
err = wait_for_submit(engine, rq[A2], HZ / 2);
while (i915_request_is_active(rq[A2])) { /* semaphore yield! */
GEM_BUG_ON(i915_request_is_active(rq[A2]));
func(A2) \
func(A2) \
u16 A1, u16 A2, u16 A3, u16 A4,
adv7511_wr_and_or(sd, 0x1A, 0xe0, A2>>8);
adv7511_wr(sd, 0x1B, A2);
sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
sdp_io_write(sd, 0xe3, c->A2);
IWL_MLD_ENC_EHT_RU(1_2_1, A2);
IWL_MVM_ENC_EHT_RU(1_2_1, A2);
SIG_EXPR_LIST_DECL_SINGLE(A2, SD1DAT0, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A2, SCL11, I2C11, I2C11_DESC);
PIN_DECL_2(A2, GPIOC2, SD1DAT0, SCL11);
FUNC_GROUP_DECL(I2C11, A2, E5);
ASPEED_PINCTRL_PIN(A2),
FUNC_GROUP_DECL(SD1, C4, B3, A2, E5, D4, C3, B2, A1);
SIG_EXPR_LIST_DECL_SINGLE(A2, GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8));
SIG_EXPR_LIST_DECL_SINGLE(A2, RMII2TXD0, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(A2, RGMII2TXD0, RGMII2);
PIN_DECL_(A2, SIG_EXPR_LIST_PTR(A2, GPIOU0), SIG_EXPR_LIST_PTR(A2, RMII2TXD0),
SIG_EXPR_LIST_PTR(A2, RGMII2TXD0));
FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6);
FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6);
ASPEED_PINCTRL_PIN(A2),
SIG_EXPR_LIST_DECL_SESG(A2, RGMII1RXCTL, RGMII1, SIG_DESC_SET(SCU400, 7),
PIN_DECL_1(A2, GPIO18A7, RGMII1RXCTL);
FUNC_GROUP_DECL(RGMII1, C6, D6, D5, A3, C5, E6, B3, A2, B2, B1, C4, E5);
ASPEED_PINCTRL_PIN(A2),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C6, A2, SCU40C, 0),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C6, A2, SCU40C, 0),
PINMUX_IPSR_GPSR(IP4_15_12, A2),
PINMUX_SINGLE(A2),
PINMUX_IPSR_GPSR(IP2_2_0, A2),
PINMUX_IPSR_GPSR(IP0_22_21, A2),
PINMUX_SINGLE(A2),
PINMUX_SINGLE(A2),
#define GPSR1_2 F_(A2, IP2_7_4)
#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP2_7_4, A2),
#define GPSR1_2 F_(A2, IP2_7_4)
#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP2_7_4, A2),
#define GPSR1_2 F_(A2, IP2_7_4)
#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP2_7_4, A2),
#define IP0_11_8 FM(DU_DR4) FM(HCTS0_N) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP0_11_8, A2),
#define IP0_11_8 FM(DU_DR4) FM(TX4) FM(GETHER_RMII_RXD0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP0_11_8, A2),
#define GPSR1_2 F_(A2, IP3_7_4)
#define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP3_7_4, A2),
#define IP0SR1_11_8 FM(HSCK0) FM(SCK0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
PINMUX_IPSR_GPSR(IP0SR1_11_8, A2),
GPIO_FN(A2),
GPIO_FN(A2),
GPIO_FN(A2), GPIO_FN(ST0_SYC), GPIO_FN(LCD_DATA2_A),
PINMUX_IPSR_GPSR(IP0_5_4, A2),
GPIO_FN(A2),
u16 A2;