Symbol: drm_dbg_dp
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
716
drm_dbg_dp(aux->drm_dev, "success = %d\n", success);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
729
drm_dbg_dp(aux->drm_dev, "Start\n");
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
787
drm_dbg_dp(aux->drm_dev, "Done\n");
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
800
drm_dbg_dp(aux->drm_dev,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
864
drm_dbg_dp(dev,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
871
drm_dbg_dp(dev,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
879
drm_dbg_dp(dev,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
889
drm_dbg_dp(dev,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
899
drm_dbg_dp(dev,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
904
drm_dbg_dp(dev,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
111
drm_dbg_dp(adev_to_drm(adev), "AUX partially written\n");
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
137
drm_dbg_dp(adev_to_drm(adev), "DP AUX transfer fail:%d\n", operation_result);
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
141
drm_dbg_dp(adev_to_drm(adev), "AUX reply command not ACK: 0x%02x.",
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1818
drm_dbg_dp(aux->drm_dev, "MST_DSC downlink setting: %d, 0x%x x %d\n",
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
217
drm_dbg_dp(connector->dev,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
355
drm_dbg_dp(port->aux.drm_dev, "MST branch oui 0x%x detected at %s\n",
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
402
drm_dbg_dp(connector->dev,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
443
drm_dbg_dp(connector->dev,
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
564
drm_dbg_dp(connector->dev,
drivers/gpu/drm/amd/display/include/logger_types.h
41
#define DC_LOG_HW_HPD_IRQ(...) drm_dbg_dp((DC_LOGGER)->dev, __VA_ARGS__)
drivers/gpu/drm/amd/display/include/logger_types.h
42
#define DC_LOG_MST(...) drm_dbg_dp((DC_LOGGER)->dev, __VA_ARGS__)
drivers/gpu/drm/amd/display/include/logger_types.h
48
#define DC_LOG_BACKLIGHT(...) drm_dbg_dp((DC_LOGGER)->dev, __VA_ARGS__)
drivers/gpu/drm/amd/display/include/logger_types.h
50
#define DC_LOG_DETECTION_DP_CAPS(...) drm_dbg_dp((DC_LOGGER)->dev, __VA_ARGS__)
drivers/gpu/drm/amd/display/include/logger_types.h
55
drm_dbg_dp((DC_LOGGER)->dev, __VA_ARGS__)
drivers/gpu/drm/amd/display/include/logger_types.h
56
#define DC_LOG_EVENT_LINK_LOSS(...) drm_dbg_dp((DC_LOGGER)->dev, __VA_ARGS__)
drivers/gpu/drm/amd/display/include/logger_types.h
63
#define DC_LOG_DSC(...) drm_dbg_dp((DC_LOGGER)->dev, __VA_ARGS__)
drivers/gpu/drm/amd/display/include/logger_types.h
66
#define DC_LOG_DP2(...) drm_dbg_dp((DC_LOGGER)->dev, __VA_ARGS__)
drivers/gpu/drm/display/drm_dp_helper.c
3534
drm_dbg_dp(aux->drm_dev,
drivers/gpu/drm/display/drm_dp_helper.c
3558
drm_dbg_dp(aux->drm_dev, "failed to read DP_DPRX_FEATURE_ENUMERATION_LIST\n");
drivers/gpu/drm/display/drm_dp_helper.c
571
drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
drivers/gpu/drm/display/drm_dp_helper.c
574
drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n",
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
309
drm_dbg_dp(dp->drm_dev, "r:%x g:%x b:%x\n", raw_data.r_value,
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
334
drm_dbg_dp(dp->drm_dev, "wait hpd status timeout");
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
39
drm_dbg_dp(dp->dev, "tu value: %u.%u value: %u\n",
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
68
drm_dbg_dp(dp->dev, "h_active %u v_active %u htotal_size %u hblank_size %u",
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
70
drm_dbg_dp(dp->dev, "flink_clock %u pixel_clock %d", fclk, mode->clock / 1000);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
101
drm_dbg_dp(dp->dev, "dp aux write training pattern set failed\n");
drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
131
drm_dbg_dp(dp->dev, "dp aux write training lane set failed\n");
drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
186
drm_dbg_dp(dp->dev, "dp link training reduce to 1 lane\n");
drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
222
drm_dbg_dp(dp->dev, "dp link training cr done\n");
drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
228
drm_dbg_dp(dp->dev, "same voltage tries 5 times\n");
drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
242
drm_dbg_dp(dp->dev, "Update link training failed\n");
drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
275
drm_dbg_dp(dp->dev, "clock recovery check failed\n");
drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
276
drm_dbg_dp(dp->dev, "cannot continue channel equalization\n");
drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
283
drm_dbg_dp(dp->dev, "dp link training eq done\n");
drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
296
drm_dbg_dp(dp->dev, "Update link training failed\n");
drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
47
drm_dbg_dp(dp->dev, "dp aux write link rate and lanes failed, ret: %d\n", ret);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
56
drm_dbg_dp(dp->dev, "dp aux write 8b/10b and downspread failed, ret: %d\n", ret);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_serdes.c
35
drm_dbg_dp(dp->dev, "dp serdes cfg failed\n");
drivers/gpu/drm/hisilicon/hibmc/dp/dp_serdes.c
50
drm_dbg_dp(dp->dev, "dp serdes rate switching failed\n");
drivers/gpu/drm/hisilicon/hibmc/dp/dp_serdes.c
55
drm_dbg_dp(dp->dev, "reducing serdes rate to :%d\n",
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c
185
drm_dbg_dp(&priv->dev, "HPD IN isr occur!\n");
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c
189
drm_dbg_dp(&priv->dev, "HPD OUT isr occur!\n");
drivers/gpu/drm/msm/dp/dp_audio.c
147
drm_dbg_dp(audio->drm_dev, "sdp_cfg = 0x%x\n", sdp_cfg);
drivers/gpu/drm/msm/dp/dp_audio.c
157
drm_dbg_dp(audio->drm_dev, "sdp_cfg2 = 0x%x\n", sdp_cfg2);
drivers/gpu/drm/msm/dp/dp_audio.c
191
drm_dbg_dp(audio->drm_dev, "Unknown link rate\n");
drivers/gpu/drm/msm/dp/dp_audio.c
198
drm_dbg_dp(audio->drm_dev, "select: %#x, acr_ctrl: %#x\n",
drivers/gpu/drm/msm/dp/dp_audio.c
220
drm_dbg_dp(audio->drm_dev,
drivers/gpu/drm/msm/dp/dp_audio.c
230
drm_dbg_dp(audio->drm_dev,
drivers/gpu/drm/msm/dp/dp_audio.c
248
drm_dbg_dp(audio->drm_dev, "dp_audio_cfg = 0x%x\n", audio_ctrl);
drivers/gpu/drm/msm/dp/dp_ctrl.c
1026
drm_dbg_dp(ctrl->drm_dev,
drivers/gpu/drm/msm/dp/dp_ctrl.c
1221
drm_dbg_dp(ctrl->drm_dev, "TU: valid_boundary_link: %d\n",
drivers/gpu/drm/msm/dp/dp_ctrl.c
1223
drm_dbg_dp(ctrl->drm_dev, "TU: delay_start_link: %d\n",
drivers/gpu/drm/msm/dp/dp_ctrl.c
1225
drm_dbg_dp(ctrl->drm_dev, "TU: boundary_moderation_en: %d\n",
drivers/gpu/drm/msm/dp/dp_ctrl.c
1227
drm_dbg_dp(ctrl->drm_dev, "TU: valid_lower_boundary_link: %d\n",
drivers/gpu/drm/msm/dp/dp_ctrl.c
1229
drm_dbg_dp(ctrl->drm_dev, "TU: upper_boundary_count: %d\n",
drivers/gpu/drm/msm/dp/dp_ctrl.c
1231
drm_dbg_dp(ctrl->drm_dev, "TU: lower_boundary_count: %d\n",
drivers/gpu/drm/msm/dp/dp_ctrl.c
1233
drm_dbg_dp(ctrl->drm_dev, "TU: tu_size_minus1: %d\n",
drivers/gpu/drm/msm/dp/dp_ctrl.c
1329
drm_dbg_dp(ctrl->drm_dev,
drivers/gpu/drm/msm/dp/dp_ctrl.c
1339
drm_dbg_dp(ctrl->drm_dev,
drivers/gpu/drm/msm/dp/dp_ctrl.c
1346
drm_dbg_dp(ctrl->drm_dev,
drivers/gpu/drm/msm/dp/dp_ctrl.c
1359
drm_dbg_dp(ctrl->drm_dev, "sink: p|v=0x%x\n",
drivers/gpu/drm/msm/dp/dp_ctrl.c
1381
drm_dbg_dp(ctrl->drm_dev, "sink: pattern=%x\n", pattern);
drivers/gpu/drm/msm/dp/dp_ctrl.c
1404
drm_dbg_dp(ctrl->drm_dev, "hw: bit=%d train=%d\n", bit, state_bit);
drivers/gpu/drm/msm/dp/dp_ctrl.c
1509
drm_dbg_dp(ctrl->drm_dev, "new rate=0x%x\n",
drivers/gpu/drm/msm/dp/dp_ctrl.c
1609
drm_dbg_dp(ctrl->drm_dev, "link training #1 on phy %d successful\n", dp_phy);
drivers/gpu/drm/msm/dp/dp_ctrl.c
1616
drm_dbg_dp(ctrl->drm_dev, "link training #2 on phy %d successful\n", dp_phy);
drivers/gpu/drm/msm/dp/dp_ctrl.c
1707
drm_dbg_dp(ctrl->drm_dev, "core clks already enabled\n");
drivers/gpu/drm/msm/dp/dp_ctrl.c
1717
drm_dbg_dp(ctrl->drm_dev, "enable core clocks \n");
drivers/gpu/drm/msm/dp/dp_ctrl.c
1718
drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n",
drivers/gpu/drm/msm/dp/dp_ctrl.c
1736
drm_dbg_dp(ctrl->drm_dev, "disable core clocks \n");
drivers/gpu/drm/msm/dp/dp_ctrl.c
1737
drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n",
drivers/gpu/drm/msm/dp/dp_ctrl.c
1751
drm_dbg_dp(ctrl->drm_dev, "links clks already enabled\n");
drivers/gpu/drm/msm/dp/dp_ctrl.c
1756
drm_dbg_dp(ctrl->drm_dev, "Enable core clks before link clks\n");
drivers/gpu/drm/msm/dp/dp_ctrl.c
1767
drm_dbg_dp(ctrl->drm_dev, "enable link clocks\n");
drivers/gpu/drm/msm/dp/dp_ctrl.c
1768
drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n",
drivers/gpu/drm/msm/dp/dp_ctrl.c
1786
drm_dbg_dp(ctrl->drm_dev, "disabled link clocks\n");
drivers/gpu/drm/msm/dp/dp_ctrl.c
1787
drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n",
drivers/gpu/drm/msm/dp/dp_ctrl.c
1811
drm_dbg_dp(ctrl->drm_dev, "link rate=%d\n", ctrl->link->link_params.rate);
drivers/gpu/drm/msm/dp/dp_ctrl.c
1932
drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
drivers/gpu/drm/msm/dp/dp_ctrl.c
1946
drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
drivers/gpu/drm/msm/dp/dp_ctrl.c
1999
drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
drivers/gpu/drm/msm/dp/dp_ctrl.c
2037
drm_dbg_dp(ctrl->drm_dev, "pattern: %#x\n", pattern);
drivers/gpu/drm/msm/dp/dp_ctrl.c
2104
drm_dbg_dp(ctrl->drm_dev,
drivers/gpu/drm/msm/dp/dp_ctrl.c
2116
drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n", pattern_requested);
drivers/gpu/drm/msm/dp/dp_ctrl.c
2157
drm_dbg_dp(ctrl->drm_dev, "%s: test->0x%x\n",
drivers/gpu/drm/msm/dp/dp_ctrl.c
2168
drm_dbg_dp(ctrl->drm_dev,
drivers/gpu/drm/msm/dp/dp_ctrl.c
2194
drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n");
drivers/gpu/drm/msm/dp/dp_ctrl.c
2223
drm_dbg_dp(ctrl->drm_dev, "PHY_TEST_PATTERN request\n");
drivers/gpu/drm/msm/dp/dp_ctrl.c
2297
drm_dbg_dp(ctrl->drm_dev,
drivers/gpu/drm/msm/dp/dp_ctrl.c
2309
drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n",
drivers/gpu/drm/msm/dp/dp_ctrl.c
2470
drm_dbg_dp(ctrl->drm_dev, "mvid=0x%x, nvid=0x%x\n", mvid, nvid);
drivers/gpu/drm/msm/dp/dp_ctrl.c
2493
drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n",
drivers/gpu/drm/msm/dp/dp_ctrl.c
2497
drm_dbg_dp(ctrl->drm_dev,
drivers/gpu/drm/msm/dp/dp_ctrl.c
2516
drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n");
drivers/gpu/drm/msm/dp/dp_ctrl.c
2556
drm_dbg_dp(ctrl->drm_dev,
drivers/gpu/drm/msm/dp/dp_ctrl.c
2592
drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
drivers/gpu/drm/msm/dp/dp_ctrl.c
2641
drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
drivers/gpu/drm/msm/dp/dp_ctrl.c
2663
drm_dbg_dp(ctrl->drm_dev, "PSR exit done\n");
drivers/gpu/drm/msm/dp/dp_ctrl.c
2666
drm_dbg_dp(ctrl->drm_dev, "PSR frame update done\n");
drivers/gpu/drm/msm/dp/dp_ctrl.c
2669
drm_dbg_dp(ctrl->drm_dev, "PSR frame capture done\n");
drivers/gpu/drm/msm/dp/dp_ctrl.c
2675
drm_dbg_dp(ctrl->drm_dev, "dp_video_ready\n");
drivers/gpu/drm/msm/dp/dp_ctrl.c
2681
drm_dbg_dp(ctrl->drm_dev, "idle_patterns_sent\n");
drivers/gpu/drm/msm/dp/dp_ctrl.c
314
drm_dbg_dp(ctrl->drm_dev, "enable\n");
drivers/gpu/drm/msm/dp/dp_ctrl.c
337
drm_dbg_dp(ctrl->drm_dev, "disable\n");
drivers/gpu/drm/msm/dp/dp_ctrl.c
388
drm_dbg_dp(ctrl->drm_dev, "mainlink off\n");
drivers/gpu/drm/msm/dp/dp_ctrl.c
427
drm_dbg_dp(ctrl->drm_dev, "DP_CONFIGURATION_CTRL=0x%x\n", config);
drivers/gpu/drm/msm/dp/dp_ctrl.c
467
drm_dbg_dp(ctrl->drm_dev, "misc settings = 0x%x\n", misc_val);
drivers/gpu/drm/msm/dp/dp_ctrl.c
990
drm_dbg_dp(ctrl->drm_dev,
drivers/gpu/drm/msm/dp/dp_display.c
1168
drm_dbg_dp(dp->drm_dev, "type=%d isr=0x%x\n",
drivers/gpu/drm/msm/dp/dp_display.c
1649
drm_dbg_dp(dp->drm_dev, "type=%d Done\n", dp->connector_type);
drivers/gpu/drm/msm/dp/dp_display.c
1682
drm_dbg_dp(dp->drm_dev, "type=%d wrong hpd_state=%d\n",
drivers/gpu/drm/msm/dp/dp_display.c
1695
drm_dbg_dp(dp->drm_dev, "type=%d Done\n", dp->connector_type);
drivers/gpu/drm/msm/dp/dp_display.c
362
drm_dbg_dp(dp->drm_dev, "HPD already %s\n", str_on_off(hpd));
drivers/gpu/drm/msm/dp/dp_display.c
378
drm_dbg_dp(dp->drm_dev, "type=%d hpd=%d\n",
drivers/gpu/drm/msm/dp/dp_display.c
453
drm_dbg_dp(dp->drm_dev, "type=%d core_init=%d phy_init=%d\n",
drivers/gpu/drm/msm/dp/dp_display.c
465
drm_dbg_dp(dp->drm_dev, "type=%d core_init=%d phy_init=%d\n",
drivers/gpu/drm/msm/dp/dp_display.c
477
drm_dbg_dp(dp->drm_dev, "type=%d core_init=%d phy_init=%d\n",
drivers/gpu/drm/msm/dp/dp_display.c
490
drm_dbg_dp(dp->drm_dev, "type=%d core_init=%d phy_init=%d\n",
drivers/gpu/drm/msm/dp/dp_display.c
532
drm_dbg_dp(dp->drm_dev, "sink count is zero, nothing to do\n");
drivers/gpu/drm/msm/dp/dp_display.c
553
drm_dbg_dp(dp->drm_dev, "%d\n", sink_request);
drivers/gpu/drm/msm/dp/dp_display.c
556
drm_dbg_dp(dp->drm_dev, "Disconnected sink_request: %d\n",
drivers/gpu/drm/msm/dp/dp_display.c
581
drm_dbg_dp(dp->drm_dev, "hpd_state=%d sink_request=%d\n",
drivers/gpu/drm/msm/dp/dp_display.c
603
drm_dbg_dp(dp->drm_dev, "Before, type=%d hpd_state=%d\n",
drivers/gpu/drm/msm/dp/dp_display.c
638
drm_dbg_dp(dp->drm_dev, "After, type=%d hpd_state=%d\n",
drivers/gpu/drm/msm/dp/dp_display.c
671
drm_dbg_dp(dp->drm_dev, "Before, type=%d hpd_state=%d\n",
drivers/gpu/drm/msm/dp/dp_display.c
713
drm_dbg_dp(dp->drm_dev, "After, type=%d hpd_state=%d\n",
drivers/gpu/drm/msm/dp/dp_display.c
730
drm_dbg_dp(dp->drm_dev, "Before, type=%d hpd_state=%d\n",
drivers/gpu/drm/msm/dp/dp_display.c
747
drm_dbg_dp(dp->drm_dev, "After, type=%d hpd_state=%d\n",
drivers/gpu/drm/msm/dp/dp_display.c
849
drm_dbg_dp(dp->drm_dev, "sink_count=%d\n", dp->link->sink_count);
drivers/gpu/drm/msm/dp/dp_display.c
851
drm_dbg_dp(dp->drm_dev, "Link already setup, return\n");
drivers/gpu/drm/msm/dp/dp_display.c
920
drm_dbg_dp(dp->drm_dev, "sink count: %d\n", dp->link->sink_count);
drivers/gpu/drm/msm/dp/dp_drm.c
31
drm_dbg_dp(dp->drm_dev, "link_ready = %s\n",
drivers/gpu/drm/msm/dp/dp_drm.c
47
drm_dbg_dp(dp->drm_dev, "link_ready = %s\n",
drivers/gpu/drm/msm/dp/dp_drm.c
92
drm_dbg_dp(connector->dev, "No sink connected\n");
drivers/gpu/drm/msm/dp/dp_link.c
1062
drm_dbg_dp(link->drm_dev, "PSR Capability changed\n");
drivers/gpu/drm/msm/dp/dp_link.c
1079
drm_dbg_dp(link->drm_dev, "sink request=%#x\n",
drivers/gpu/drm/msm/dp/dp_link.c
1128
drm_dbg_dp(link->drm_dev,
drivers/gpu/drm/msm/dp/dp_link.c
1145
drm_dbg_dp(link->drm_dev,
drivers/gpu/drm/msm/dp/dp_link.c
1153
drm_dbg_dp(link->drm_dev,
drivers/gpu/drm/msm/dp/dp_link.c
1162
drm_dbg_dp(link->drm_dev,
drivers/gpu/drm/msm/dp/dp_link.c
1169
drm_dbg_dp(link->drm_dev, "adjusted: v_level=%d, p_level=%d\n",
drivers/gpu/drm/msm/dp/dp_link.c
1204
drm_dbg_dp(link->drm_dev, "bpp=%d not supported, use bpc=8\n",
drivers/gpu/drm/msm/dp/dp_link.c
138
drm_dbg_dp(link->drm_dev, "test_audio_period_ch_1 = 0x%x\n", ret);
drivers/gpu/drm/msm/dp/dp_link.c
145
drm_dbg_dp(link->drm_dev, "test_audio_period_ch_2 = 0x%x\n", ret);
drivers/gpu/drm/msm/dp/dp_link.c
153
drm_dbg_dp(link->drm_dev, "test_audio_period_ch_3 = 0x%x\n", ret);
drivers/gpu/drm/msm/dp/dp_link.c
160
drm_dbg_dp(link->drm_dev, "test_audio_period_ch_4 = 0x%x\n", ret);
drivers/gpu/drm/msm/dp/dp_link.c
167
drm_dbg_dp(link->drm_dev, "test_audio_period_ch_5 = 0x%x\n", ret);
drivers/gpu/drm/msm/dp/dp_link.c
174
drm_dbg_dp(link->drm_dev, "test_audio_period_ch_6 = 0x%x\n", ret);
drivers/gpu/drm/msm/dp/dp_link.c
181
drm_dbg_dp(link->drm_dev, "test_audio_period_ch_7 = 0x%x\n", ret);
drivers/gpu/drm/msm/dp/dp_link.c
188
drm_dbg_dp(link->drm_dev, "test_audio_period_ch_8 = 0x%x\n", ret);
drivers/gpu/drm/msm/dp/dp_link.c
215
drm_dbg_dp(link->drm_dev, "audio pattern type = 0x%x\n", data);
drivers/gpu/drm/msm/dp/dp_link.c
256
drm_dbg_dp(link->drm_dev,
drivers/gpu/drm/msm/dp/dp_link.c
497
drm_dbg_dp(link->drm_dev,
drivers/gpu/drm/msm/dp/dp_link.c
555
drm_dbg_dp(link->drm_dev, "link rate = 0x%x\n",
drivers/gpu/drm/msm/dp/dp_link.c
571
drm_dbg_dp(link->drm_dev, "lane count = 0x%x\n",
drivers/gpu/drm/msm/dp/dp_link.c
597
drm_dbg_dp(link->drm_dev, "phy_test_pattern_sel = 0x%x\n", data);
drivers/gpu/drm/msm/dp/dp_link.c
653
drm_dbg_dp(link->drm_dev, "device service irq vector = 0x%x\n", data);
drivers/gpu/drm/msm/dp/dp_link.c
656
drm_dbg_dp(link->drm_dev, "no test requested\n");
drivers/gpu/drm/msm/dp/dp_link.c
671
drm_dbg_dp(link->drm_dev, "link 0x%x not supported\n", data);
drivers/gpu/drm/msm/dp/dp_link.c
675
drm_dbg_dp(link->drm_dev, "Test:(0x%x) requested\n", data);
drivers/gpu/drm/msm/dp/dp_link.c
756
drm_dbg_dp(link->drm_dev,
drivers/gpu/drm/msm/dp/dp_link.c
833
drm_dbg_dp(link->drm_dev, "vx: 0=%d, 1=%d, 2=%d, 3=%d\n",
drivers/gpu/drm/msm/dp/dp_link.c
839
drm_dbg_dp(link->drm_dev, "px: 0=%d, 1=%d, 2=%d, 3=%d\n",
drivers/gpu/drm/msm/dp/dp_link.c
849
drm_dbg_dp(link->drm_dev,
drivers/gpu/drm/msm/dp/dp_link.c
860
drm_dbg_dp(link->drm_dev,
drivers/gpu/drm/msm/dp/dp_link.c
878
drm_dbg_dp(link->drm_dev, "no phy test\n");
drivers/gpu/drm/msm/dp/dp_link.c
890
drm_dbg_dp(link->drm_dev,
drivers/gpu/drm/msm/dp/dp_link.c
895
drm_dbg_dp(link->drm_dev,
drivers/gpu/drm/msm/dp/dp_link.c
934
drm_dbg_dp(link->drm_dev, "PSR Capability Change\n");
drivers/gpu/drm/msm/dp/dp_link.c
965
drm_dbg_dp(link->drm_dev,
drivers/gpu/drm/msm/dp/dp_panel.c
109
drm_dbg_dp(panel->drm_dev, "max_lanes=%d max_link_rate=%d\n",
drivers/gpu/drm/msm/dp/dp_panel.c
123
drm_dbg_dp(panel->drm_dev, "edp_rev=0x%x\n", edp_rev);
drivers/gpu/drm/msm/dp/dp_panel.c
152
drm_dbg_dp(panel->drm_dev,
drivers/gpu/drm/msm/dp/dp_panel.c
200
drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor);
drivers/gpu/drm/msm/dp/dp_panel.c
201
drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate);
drivers/gpu/drm/msm/dp/dp_panel.c
202
drm_dbg_dp(panel->drm_dev, "link_rate_set=%d\n", link_info->rate_set);
drivers/gpu/drm/msm/dp/dp_panel.c
203
drm_dbg_dp(panel->drm_dev, "use_rate_set=%d\n", link_info->use_rate_set);
drivers/gpu/drm/msm/dp/dp_panel.c
204
drm_dbg_dp(panel->drm_dev, "lane_count=%d\n", link_info->num_lanes);
drivers/gpu/drm/msm/dp/dp_panel.c
430
drm_dbg_dp(panel->drm_dev, "%s: enabled tpg\n", __func__);
drivers/gpu/drm/msm/dp/dp_panel.c
455
drm_dbg_dp(panel->drm_dev,
drivers/gpu/drm/msm/dp/dp_panel.c
465
drm_dbg_dp(panel->drm_dev, "calling panel's tpg_enable\n");
drivers/gpu/drm/msm/dp/dp_panel.c
527
drm_dbg_dp(panel->drm_dev, "vsc sdp enable=1\n");
drivers/gpu/drm/msm/dp/dp_panel.c
554
drm_dbg_dp(panel->drm_dev, "vsc sdp enable=0\n");
drivers/gpu/drm/msm/dp/dp_panel.c
619
drm_dbg_dp(panel->drm_dev, "width=%d hporch= %d %d %d\n",
drivers/gpu/drm/msm/dp/dp_panel.c
624
drm_dbg_dp(panel->drm_dev, "height=%d vporch= %d %d %d\n",
drivers/gpu/drm/msm/dp/dp_panel.c
670
drm_dbg_dp(panel->drm_dev, "wide_bus_en=%d reg=%#x\n", wide_bus_en, reg);
drivers/gpu/drm/msm/dp/dp_panel.c
695
drm_dbg_dp(panel->drm_dev, "SET NEW RESOLUTION:\n");
drivers/gpu/drm/msm/dp/dp_panel.c
696
drm_dbg_dp(panel->drm_dev, "%dx%d@%dfps\n",
drivers/gpu/drm/msm/dp/dp_panel.c
698
drm_dbg_dp(panel->drm_dev,
drivers/gpu/drm/msm/dp/dp_panel.c
703
drm_dbg_dp(panel->drm_dev,
drivers/gpu/drm/msm/dp/dp_panel.c
708
drm_dbg_dp(panel->drm_dev, "pixel clock (KHz)=(%d)\n",
drivers/gpu/drm/msm/dp/dp_panel.c
710
drm_dbg_dp(panel->drm_dev, "bpp = %d\n", msm_dp_panel->msm_dp_mode.bpp);
drivers/gpu/drm/msm/dp/dp_panel.c
715
drm_dbg_dp(panel->drm_dev, "updated bpp = %d\n",
drivers/gpu/drm/msm/dp/dp_panel.c
79
drm_dbg_dp(panel->drm_dev,