dma_regs
static void __iomem *dma_regs;
dma_regs = map_onedev(dma_pdev, 0);
return in_le32(dma_regs+reg);
out_le32(dma_regs+reg, val);
void __iomem *dma_regs = NULL;
dma_regs = devm_ioremap(priv->dev, dmaregs,
if (dma_regs == NULL)
priv->tfregs, dma_regs);
if (priv->pdev && dma_regs)
struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
if (dma_regs) {
writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma_regs->control);
while (--timeout && (readl(&dma_regs->status) & RUN))
struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
writel(priv->dma_table_dma, &dma_regs->cmdptr);
struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
writel((RUN << 16) | RUN, &dma_regs->control);
(void)readl(&dma_regs->control);
struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
writel (((RUN|WAKE|DEAD) << 16), &dma_regs->control);
while (--timeout && (readl(&dma_regs->status) & RUN))
struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
dstat = readl(&dma_regs->status);
writel((FLUSH << 16) | FLUSH, &dma_regs->control);
dstat = readl(&dma_regs->status);
struct dma_regs *dma_reg;
struct dma_regs *dma_reg = chan->device->dma_reg;
struct dma_regs *dma_reg;
struct dma_regs *dma_reg;
struct dma_regs __iomem *dma_reg;
DBDMA_DO_STOP(rm->dma_regs);
out_le32(&rm->dma_regs->cmdptr_hi, 0);
out_le32(&rm->dma_regs->cmdptr, rm->dma_buf_p);
out_le32(&rm->dma_regs->control, (RUN << 16) | RUN);
DBDMA_DO_RESET(rm->dma_regs);
(void)in_le32(&rm->dma_regs->status);
DBDMA_DO_RESET(rm->dma_regs);
rm->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x100);
rm->dma_regs = ioremap(rdma.start, 0x100);
if (rm->dma_regs == NULL) {
DBDMA_DO_RESET(rm->dma_regs);
iounmap(rm->dma_regs);
DBDMA_DO_RESET(rm->dma_regs);
iounmap(rm->dma_regs);
DBDMA_DO_RESET(rm->dma_regs);
struct dbdma_regs __iomem *dma_regs;
ioread32((_channel)->dma_regs + _reg)
iowrite32((_val), (_channel)->dma_regs + _reg)
channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
channel->name, channel->dma_regs, channel->dma_irq,
void __iomem *dma_regs;
struct fman_dma_regs __iomem *dma_rg = fman->dma_regs;
fman->dma_regs = base_addr + DMA_OFFSET;
liodn_base = ioread32be(&fman->dma_regs->fmdmplr[i / 2]);
tmp = ioread32be(&fman->dma_regs->fmdmplr[port_id / 2]);
iowrite32be(tmp, &fman->dma_regs->fmdmplr[port_id / 2]);
struct fman_dma_regs __iomem *dma_rg = fman->dma_regs;
tmp = ioread32be(&fman->dma_regs->fmdmmr);
iowrite32be(tmp, &fman->dma_regs->fmdmmr);
tmp = ioread32be(&fman->dma_regs->fmdmmr);
iowrite32be(tmp, &fman->dma_regs->fmdmmr);
struct fman_dma_regs __iomem *dma_regs;
priv->dma_regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
priv->dma_regs = devm_platform_ioremap_resource_byname(pdev, "dma");
if (IS_ERR(priv->dma_regs)) {
return PTR_ERR(priv->dma_regs);
priv->ctrl_regs = priv->dma_regs + NIXGE_REG_CTRL_OFFSET;
void __iomem *dma_regs;
writel(val, priv->dma_regs + offset);
writel(lower_32_bits(addr), priv->dma_regs + offset);
writel(upper_32_bits(addr), priv->dma_regs + offset + 4);
return readl(priv->dma_regs + offset);
readl_poll_timeout((priv)->dma_regs + (addr), (val), (cond), \
channel->dma_regs = pdata->mac_regs + DMA_CH_BASE +
channel->name, channel->dma_regs,
#define XLGMAC_DMA_REG(channel, reg) ((channel)->dma_regs + (reg))
void __iomem *dma_regs;
void __iomem *dma_regs;
iowrite32(value, lp->dma_regs + reg);
iowrite64(value, lp->dma_regs + reg);
return ioread32(lp->dma_regs + reg);
lp->dma_regs = devm_ioremap_resource(&pdev->dev,
lp->dma_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
if (IS_ERR(lp->dma_regs)) {
return PTR_ERR(lp->dma_regs);
void __iomem *desc = lp->dma_regs + XAXIDMA_TX_CDESC_OFFSET + 4;
esp->dma_regs = esp->regs;
esp->host->unique_id, esp->regs, esp->dma_regs,
void __iomem *dma_regs;
esp->dma_regs = (void __iomem *)res->start;
vdma_disable ((int)esp->dma_regs);
vdma_disable ((int)esp->dma_regs);
vdma_disable ((int)esp->dma_regs);
vdma_set_mode ((int)esp->dma_regs, DMA_MODE_READ);
vdma_set_mode ((int)esp->dma_regs, DMA_MODE_WRITE);
vdma_set_addr ((int)esp->dma_regs, addr);
vdma_set_count ((int)esp->dma_regs, dma_count);
vdma_enable ((int)esp->dma_regs);
u32 enable = vdma_get_enable((int)esp->dma_regs);
esp->dma_regs = ioremap(res->start, 0x10);
iounmap(esp->dma_regs);
readl(esp->dma_regs + (REG))
writel((VAL), esp->dma_regs + (REG))
*(volatile u32 *)(esp->dma_regs + (REG))
do { *(volatile u32 *)(esp->dma_regs + (REG)) = (VAL); } while (0)
sbus_readl(esp->dma_regs + (REG))
sbus_writel((VAL), esp->dma_regs + (REG))
esp->dma_regs = of_ioremap(&dma_of->resource[0], 0,
if (!esp->dma_regs)
of_iounmap(&dma_of->resource[0], esp->dma_regs,
struct cyber_dma_registers __iomem *dregs = esp->dma_regs;
struct fastlane_dma_registers __iomem *dregs = esp->dma_regs;
struct fastlane_dma_registers __iomem *dregs = esp->dma_regs;
struct blz1230_dma_registers __iomem *dregs = esp->dma_regs;
struct blz1230II_dma_registers __iomem *dregs = esp->dma_regs;
struct blz2060_dma_registers __iomem *dregs = esp->dma_regs;
struct cyber_dma_registers __iomem *dregs = esp->dma_regs;
struct cyberII_dma_registers __iomem *dregs = esp->dma_regs;
struct fastlane_dma_registers __iomem *dregs = esp->dma_regs;
esp->dma_regs = ioremap(dmaaddr,
esp->dma_regs = ZTWO_VADDR(dmaaddr);
if (!esp->dma_regs) {
iounmap(esp->dma_regs);
iounmap(esp->dma_regs);
ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
readl_relaxed((ep)->dma_regs + USBA_DMA_##reg)
writel_relaxed((value), (ep)->dma_regs + USBA_DMA_##reg)
void __iomem *dma_regs;
epn->dma_regs + USBF_REG_DMA_EPN_DCR1,
ret = epn->dma_regs ?
usbf_ep_xfer = ep->dma_regs ?
usbf_ep_xfer = ep->dma_regs ?
if (ep->dma_regs) {
if (ep->dma_regs) {
void __iomem *dma_regs;
ep->dma_regs = ep->udc->regs +
return readl(ep->dma_regs + offset);
writel(val, ep->dma_regs + offset);