dma_flags
enum dma_ctrl_flags dma_flags = 0;
dma_flags |= DMA_PREP_PQ_DISABLE_P;
dma_flags |= DMA_PREP_PQ_DISABLE_Q;
tx = do_async_gen_syndrome(chan, coefs, j, unmap, dma_flags, submit);
enum dma_ctrl_flags dma_flags = submit->cb_fn ? DMA_PREP_INTERRUPT : 0;
dma_flags |= DMA_PREP_PQ_DISABLE_P;
dma_flags |= DMA_PREP_PQ_DISABLE_Q;
dma_flags |= DMA_PREP_FENCE;
dma_flags);
enum dma_ctrl_flags dma_flags,
pq_src_cnt = min(src_cnt, dma_maxpq(dma, dma_flags));
dma_flags |= DMA_PREP_INTERRUPT;
dma_flags |= DMA_PREP_FENCE;
dma_flags);
dma_flags |= DMA_PREP_CONTINUE;
enum dma_ctrl_flags dma_flags = DMA_PREP_PQ_DISABLE_P;
dma_flags |= DMA_PREP_FENCE;
1, &coef, len, dma_flags);
enum dma_ctrl_flags dma_flags = DMA_PREP_PQ_DISABLE_P;
dma_flags |= DMA_PREP_FENCE;
len, dma_flags);
enum dma_ctrl_flags dma_flags = 0;
dma_flags |= DMA_PREP_INTERRUPT;
dma_flags |= DMA_PREP_FENCE;
dma_flags);
dma_flags);
enum dma_transfer_direction dir, unsigned long dma_flags,
desc->async_tx.flags = dma_flags;
unsigned long dma_flags, void *context)
return vchan_tx_prep(&uchan->vc, &desc->vd, dma_flags);
unsigned int sg_len, unsigned long dma_flags)
desc->txd.flags = dma_flags;
enum dma_transfer_direction direction, unsigned long dma_flags)
desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
unsigned long dma_flags)
DMA_MEM_TO_MEM, dma_flags);
unsigned long dma_flags, void *context)
return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
unsigned long dma_flags;
dma_flags = claim_dma_lock();
release_dma_lock(dma_flags);
dma_flags = claim_dma_lock();
release_dma_lock(dma_flags);
static int uc_fw_xfer(struct intel_uc_fw *uc_fw, u32 dst_offset, u32 dma_flags)
_MASKED_BIT_ENABLE(dma_flags | START_DMA));
intel_uncore_write_fw(uncore, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags));
int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, u32 dst_offset, u32 dma_flags)
err = uc_fw_xfer(uc_fw, dst_offset, dma_flags);
int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, u32 offset, u32 dma_flags);
static int uc_fw_xfer(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags)
_MASKED_BIT_ENABLE(dma_flags | START_DMA));
xe_mmio_write32(mmio, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags));
int xe_uc_fw_upload(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags)
err = uc_fw_xfer(uc_fw, offset, dma_flags);
int xe_uc_fw_upload(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags);
unsigned short dma_flags;
dma_flags = EF4_TX_BUF_MAP_SINGLE;
buffer->flags = EF4_TX_BUF_CONT | dma_flags;
buffer->flags = EF4_TX_BUF_SKB | dma_flags;
dma_flags = 0;
unsigned short dma_flags;
dma_flags = EFX_TX_BUF_MAP_SINGLE;
buffer->flags = EFX_TX_BUF_CONT | dma_flags;
buffer->flags = EFX_TX_BUF_SKB | dma_flags;
dma_flags = 0;
unsigned short dma_flags;
dma_flags = EFX_TX_BUF_MAP_SINGLE;
buffer->flags = EFX_TX_BUF_CONT | dma_flags;
buffer->flags = EFX_TX_BUF_SKB | dma_flags;
dma_flags = 0;
u32 dma_flags;
dma_flags = MT_TXD_PKT_INFO_80211;
dma_flags |= MT_TXD_PKT_INFO_WIV;
ret = mt7601u_dma_skb_wrap_pkt(skb, ep2dmaq(ep), dma_flags);
u8 dma_flags;
tcb->dma_flags = APPLE_ANS_TCB_DMA_TO_DEVICE;
tcb->dma_flags = APPLE_ANS_TCB_DMA_FROM_DEVICE;
flags = dma_flags(dev, dma->type, dma->bus_master,
flags = dma_flags(dev, p->type, p->bus_master, p->transfer);
int dma_flags;
int dma_flags);
args.coherent = !!(map->dma_flags & GNTDEV_DMA_FLAG_COHERENT);
int dma_flags)
add->dma_flags = dma_flags;
if (dma_flags & (GNTDEV_DMA_FLAG_WC | GNTDEV_DMA_FLAG_COHERENT)) {
args.coherent = !!(dma_flags & GNTDEV_DMA_FLAG_COHERENT);
unsigned int dma_flags;
return sg->dma_flags & SG_DMA_BUS_ADDRESS;
sg->dma_flags |= SG_DMA_BUS_ADDRESS;
sg->dma_flags &= ~SG_DMA_BUS_ADDRESS;
return sg->dma_flags & SG_DMA_SWIOTLB;
sg->dma_flags |= SG_DMA_SWIOTLB;
unsigned int dma_flags;
gus->gf1.dma_flags &= ~SNDRV_GF1_DMA_TRIGGER;
if (!(gus->gf1.dma_flags & SNDRV_GF1_DMA_TRIGGER)) {
gus->gf1.dma_flags |= SNDRV_GF1_DMA_TRIGGER;