dma_fence_wait_timeout
dma_fence_wait_timeout(fence, false, msecs_to_jiffies(2000));
dma_fence_wait_timeout(out_fence, false, MAX_SCHEDULE_TIMEOUT);
EXPORT_SYMBOL(dma_fence_wait_timeout);
ret = dma_fence_wait_timeout(fence, intr, timeout);
if (dma_fence_wait_timeout(f, false, 0) != 0) {
if (dma_fence_wait_timeout(f, false, 0) != 1) {
if (dma_fence_wait_timeout(wt.f, false, 1) != 0) {
if (dma_fence_wait_timeout(wt.f, false, HZ) == 0) {
r = dma_fence_wait_timeout(fence, true, timeout);
r = dma_fence_wait_timeout(fence, true, timeout);
r = dma_fence_wait_timeout(fence, false, timeout);
if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout))
ret = dma_fence_wait_timeout(f, true, msecs_to_jiffies(100));
ret = dma_fence_wait_timeout(f, true, MAX_SCHEDULE_TIMEOUT);
r = dma_fence_wait_timeout(fence, false, timeout);
r = dma_fence_wait_timeout(fence, false, timeout);
r = dma_fence_wait_timeout(fence, false, timeout);
r = dma_fence_wait_timeout(fence, false, timeout);
r = dma_fence_wait_timeout(fence, false, timeout);
r = dma_fence_wait_timeout(fence, false, timeout);
ret = dma_fence_wait_timeout(f, false, timeout);
r = dma_fence_wait_timeout(f, false, timeout);
r = dma_fence_wait_timeout(f, false, timeout);
r = dma_fence_wait_timeout(f, false, timeout);
r = dma_fence_wait_timeout(f, false, timeout);
r = dma_fence_wait_timeout(f, false, timeout);
r = dma_fence_wait_timeout(f, false, timeout);
r = dma_fence_wait_timeout(f, false, timeout);
r = dma_fence_wait_timeout(f, false, timeout);
r = dma_fence_wait_timeout(f, false, timeout);
r = dma_fence_wait_timeout(f, false, timeout);
r = dma_fence_wait_timeout(f, false, timeout);
r = dma_fence_wait_timeout(f, false, timeout);
r = dma_fence_wait_timeout(f, false, timeout);
r = dma_fence_wait_timeout(f, false, timeout);
r = dma_fence_wait_timeout(f, false, timeout);
r = dma_fence_wait_timeout(f, false, timeout);
r = dma_fence_wait_timeout(f, false, timeout);
r = dma_fence_wait_timeout(f, false, timeout);
r = dma_fence_wait_timeout(f, false, timeout);
r = dma_fence_wait_timeout(f, false, timeout);
r = dma_fence_wait_timeout(fence, false, timeout);
r = dma_fence_wait_timeout(fence, false, timeout);
ret = dma_fence_wait_timeout(fence, true, remaining);
ret = dma_fence_wait_timeout(new_plane_state->fence, false,
return dma_fence_wait_timeout(fence,
timeout = dma_fence_wait_timeout(fence,
timeout = dma_fence_wait_timeout(fence, true, HZ / 2);
if (dma_fence_wait_timeout(&request->fence, false, T) != -ETIME) {
if (dma_fence_wait_timeout(&request->fence, false, T / 2) != -ETIME) {
if (dma_fence_wait_timeout(&request->fence, false, T) <= 0) {
if (dma_fence_wait_timeout(&request->fence, false, T) <= 0) {
ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout));
ret = dma_fence_wait_timeout(&fence->base, intr, 15 * HZ);
WARN_ON(dma_fence_wait_timeout(fence, false, 2 * HZ) <= 0);
return dma_fence_wait_timeout(&job->base.s_fence->scheduled,
err = dma_fence_wait_timeout(fence, true, msecs_to_jiffies(10000));
dma_fence_wait_timeout(man->eviction_fences[0], false, MAX_SCHEDULE_TIMEOUT);
dma_fence_wait_timeout(&vgplane_st->fence->f, true,
long ret = dma_fence_wait_timeout(&fence->base, interruptible, timeout);
if (dma_fence_wait_timeout(fence, false, 5 * HZ) <= 0) {
ret = dma_fence_wait_timeout(fence, false, 5 * HZ);
timeout = dma_fence_wait_timeout(fence, false, HZ);
timeout = dma_fence_wait_timeout(fence, false, HZ);
timeout = dma_fence_wait_timeout(fence, false, timeout_jiffies);
long ret = dma_fence_wait_timeout(fence, false, timeout);
ret = dma_fence_wait_timeout(fence, false, PF_VRAM_SAVE_RESTORE_TIMEOUT);
ret = dma_fence_wait_timeout(fence, false, PF_VRAM_SAVE_RESTORE_TIMEOUT);
timeout = dma_fence_wait_timeout(fence, false, HZ);
timeout = dma_fence_wait_timeout(fence, false, HZ);
timeout = dma_fence_wait_timeout(fence, false, HZ);
timeout = dma_fence_wait_timeout(q->lr.pfence, false,
wait_err = dma_fence_wait_timeout(fence, true, timeout);
signed long dma_fence_wait_timeout(struct dma_fence *,
ret = dma_fence_wait_timeout(fence, intr, MAX_SCHEDULE_TIMEOUT);