arch/m68k/coldfire/m53xx.c
585
int divider;
arch/m68k/coldfire/m53xx.c
589
divider = readw(MCF_CCM_CDR) & MCF_CCM_CDR_LPDIV(0xF);
arch/m68k/coldfire/m53xx.c
590
return (FREF/(2 << divider));
arch/mips/include/asm/sgi/mc.h
57
volatile u32 divider; /* Divider reg for RPSS */
arch/mips/sgi-ip22/ip22-mc.c
138
sgimc->divider = 0x101;
arch/sh/boards/mach-ecovec24/setup.c
514
.divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
arch/sh/boards/mach-ecovec24/setup.c
519
.divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
arch/x86/kernel/tsc_msr.c
197
if (md->divider) {
arch/x86/kernel/tsc_msr.c
199
freq = DIV_ROUND_CLOSEST(tscref, md->divider);
arch/x86/kernel/tsc_msr.c
204
res = DIV_ROUND_CLOSEST(tscref * ratio, md->divider);
arch/x86/kernel/tsc_msr.c
40
u32 divider;
drivers/clk/aspeed/clk-ast2700.c
984
const struct ast2700_clk_div_data *divider = &clk->data.div;
drivers/clk/aspeed/clk-ast2700.c
986
reg = clk_ctrl->base + divider->reg;
drivers/clk/aspeed/clk-ast2700.c
987
phw = hws[divider->parent_id];
drivers/clk/aspeed/clk-ast2700.c
991
divider->bit_shift,
drivers/clk/aspeed/clk-ast2700.c
992
divider->bit_width, 0,
drivers/clk/aspeed/clk-ast2700.c
993
divider->div_table,
drivers/clk/baikal-t1/ccu-div.c
211
unsigned long divider;
drivers/clk/baikal-t1/ccu-div.c
215
divider = ccu_div_get(div->mask, val);
drivers/clk/baikal-t1/ccu-div.c
217
return ccu_div_calc_freq(parent_rate, divider);
drivers/clk/baikal-t1/ccu-div.c
224
unsigned long divider;
drivers/clk/baikal-t1/ccu-div.c
226
divider = parent_rate / rate;
drivers/clk/baikal-t1/ccu-div.c
227
return clamp_t(unsigned long, divider, CCU_DIV_CLKDIV_MIN,
drivers/clk/baikal-t1/ccu-div.c
235
unsigned long divider;
drivers/clk/baikal-t1/ccu-div.c
237
divider = ccu_div_var_calc_divider(req->rate, req->best_parent_rate,
drivers/clk/baikal-t1/ccu-div.c
240
req->rate = ccu_div_calc_freq(req->best_parent_rate, divider);
drivers/clk/baikal-t1/ccu-div.c
254
unsigned long flags, divider;
drivers/clk/baikal-t1/ccu-div.c
258
divider = ccu_div_var_calc_divider(rate, parent_rate, div->mask);
drivers/clk/baikal-t1/ccu-div.c
259
if (divider == 1 && div->features & CCU_DIV_SKIP_ONE) {
drivers/clk/baikal-t1/ccu-div.c
260
divider = 0;
drivers/clk/baikal-t1/ccu-div.c
262
if (divider == 1 || divider == 2)
drivers/clk/baikal-t1/ccu-div.c
263
divider = 0;
drivers/clk/baikal-t1/ccu-div.c
264
else if (divider == 3)
drivers/clk/baikal-t1/ccu-div.c
265
divider = 4;
drivers/clk/baikal-t1/ccu-div.c
268
val = ccu_div_prep(div->mask, divider);
drivers/clk/baikal-t1/ccu-div.c
272
ret = ccu_div_var_update_clkdiv(div, parent_rate, divider);
drivers/clk/baikal-t1/ccu-div.c
288
unsigned long flags, divider;
drivers/clk/baikal-t1/ccu-div.c
291
divider = ccu_div_var_calc_divider(rate, parent_rate, div->mask);
drivers/clk/baikal-t1/ccu-div.c
292
val = ccu_div_prep(div->mask, divider);
drivers/clk/baikal-t1/ccu-div.c
311
return ccu_div_calc_freq(parent_rate, div->divider);
drivers/clk/baikal-t1/ccu-div.c
319
req->rate = ccu_div_calc_freq(req->best_parent_rate, div->divider);
drivers/clk/baikal-t1/ccu-div.c
433
*val = div->divider;
drivers/clk/baikal-t1/ccu-div.c
616
div->divider = div_init->divider;
drivers/clk/baikal-t1/ccu-div.c
621
div->divider = div_init->divider;
drivers/clk/baikal-t1/ccu-div.c
78
unsigned long divider)
drivers/clk/baikal-t1/ccu-div.c
85
nd = ccu_div_lock_delay_ns(parent_rate, divider);
drivers/clk/baikal-t1/ccu-div.h
105
unsigned int divider;
drivers/clk/baikal-t1/ccu-div.h
79
unsigned int divider;
drivers/clk/baikal-t1/clk-ccu-div.c
106
unsigned int divider;
drivers/clk/baikal-t1/clk-ccu-div.c
374
init.divider = info->divider;
drivers/clk/baikal-t1/clk-ccu-div.c
379
init.divider = info->divider;
drivers/clk/baikal-t1/clk-ccu-div.c
76
.divider = _divider \
drivers/clk/baikal-t1/clk-ccu-div.c
95
.divider = _divider \
drivers/clk/bcm/clk-bcm2835.c
1381
struct bcm2835_pll_divider *divider;
drivers/clk/bcm/clk-bcm2835.c
1403
divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
drivers/clk/bcm/clk-bcm2835.c
1404
if (!divider)
drivers/clk/bcm/clk-bcm2835.c
1407
divider->div.reg = cprman->regs + divider_data->a2w_reg;
drivers/clk/bcm/clk-bcm2835.c
1408
divider->div.shift = A2W_PLL_DIV_SHIFT;
drivers/clk/bcm/clk-bcm2835.c
1409
divider->div.width = A2W_PLL_DIV_BITS;
drivers/clk/bcm/clk-bcm2835.c
1410
divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
drivers/clk/bcm/clk-bcm2835.c
1411
divider->div.lock = &cprman->regs_lock;
drivers/clk/bcm/clk-bcm2835.c
1412
divider->div.hw.init = &init;
drivers/clk/bcm/clk-bcm2835.c
1413
divider->div.table = NULL;
drivers/clk/bcm/clk-bcm2835.c
1415
divider->cprman = cprman;
drivers/clk/bcm/clk-bcm2835.c
1416
divider->data = divider_data;
drivers/clk/bcm/clk-bcm2835.c
1418
ret = devm_clk_hw_register(cprman->dev, ÷r->div.hw);
drivers/clk/bcm/clk-bcm2835.c
1435
return ÷r->div.hw;
drivers/clk/bcm/clk-bcm2835.c
809
struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
drivers/clk/bcm/clk-bcm2835.c
810
struct bcm2835_cprman *cprman = divider->cprman;
drivers/clk/bcm/clk-bcm2835.c
811
const struct bcm2835_pll_divider_data *data = divider->data;
drivers/clk/bcm/clk-bcm2835.c
830
struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
drivers/clk/bcm/clk-bcm2835.c
831
struct bcm2835_cprman *cprman = divider->cprman;
drivers/clk/bcm/clk-bcm2835.c
832
const struct bcm2835_pll_divider_data *data = divider->data;
drivers/clk/bcm/clk-bcm2835.c
846
struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
drivers/clk/bcm/clk-bcm2835.c
847
struct bcm2835_cprman *cprman = divider->cprman;
drivers/clk/bcm/clk-bcm2835.c
848
const struct bcm2835_pll_divider_data *data = divider->data;
drivers/clk/bcm/clk-bcm2835.c
866
struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
drivers/clk/bcm/clk-bcm2835.c
867
struct bcm2835_cprman *cprman = divider->cprman;
drivers/clk/bcm/clk-bcm2835.c
868
const struct bcm2835_pll_divider_data *data = divider->data;
drivers/clk/bcm/clk-bcm2835.c
888
struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
drivers/clk/bcm/clk-bcm2835.c
889
struct bcm2835_cprman *cprman = divider->cprman;
drivers/clk/bcm/clk-bcm2835.c
890
const struct bcm2835_pll_divider_data *data = divider->data;
drivers/clk/bcm/clk-kona.c
591
reg_div = divider(div, div->u.s.scaled_div);
drivers/clk/berlin/berlin2-avpll.c
255
u32 reg, div_av2, div_av3, divider = 1;
drivers/clk/berlin/berlin2-avpll.c
271
divider = reg & VCO_SYNC1_MASK;
drivers/clk/berlin/berlin2-avpll.c
287
divider *= div_hdmi[reg & 0x3];
drivers/clk/berlin/berlin2-avpll.c
301
divider *= div_av1[reg & 0x3];
drivers/clk/berlin/berlin2-avpll.c
318
divider *= div_av2;
drivers/clk/berlin/berlin2-avpll.c
336
do_div(freq, divider);
drivers/clk/berlin/berlin2-div.c
181
u32 divsw, div3sw, divider = 1;
drivers/clk/berlin/berlin2-div.c
193
divider = 3;
drivers/clk/berlin/berlin2-div.c
196
divider = 1;
drivers/clk/berlin/berlin2-div.c
203
divider = clk_div[reg];
drivers/clk/berlin/berlin2-div.c
209
return parent_rate / divider;
drivers/clk/clk-axi-clkgen.c
201
static void axi_clkgen_calc_clk_params(unsigned int divider,
drivers/clk/clk-axi-clkgen.c
207
if (divider == 1) {
drivers/clk/clk-axi-clkgen.c
213
params->high = divider / 2;
drivers/clk/clk-axi-clkgen.c
214
params->edge = divider % 2;
drivers/clk/clk-axi-clkgen.c
215
params->low = divider - params->high;
drivers/clk/clk-axi-clkgen.c
220
params->high = divider / 2;
drivers/clk/clk-axi-clkgen.c
221
params->edge = divider % 2;
drivers/clk/clk-axi-clkgen.c
232
(divider == 2 && frac_divider == 1))
drivers/clk/clk-cdce706.c
569
for (i = 0; i < ARRAY_SIZE(cdce->divider); ++i) {
drivers/clk/clk-cdce706.c
575
cdce->divider[i].parent =
drivers/clk/clk-cdce706.c
582
cdce->divider[i].div = val & CDCE706_DIVIDER_DIVIDER_MASK;
drivers/clk/clk-cdce706.c
585
cdce->divider[i].parent, cdce->divider[i].div);
drivers/clk/clk-cdce706.c
588
ret = cdce706_register_hw(cdce, cdce->divider,
drivers/clk/clk-cdce706.c
589
ARRAY_SIZE(cdce->divider),
drivers/clk/clk-cdce706.c
84
struct cdce706_hw_data divider[6];
drivers/clk/clk-cdce925.c
368
unsigned long divider;
drivers/clk/clk-cdce925.c
375
divider = DIV_ROUND_CLOSEST(parent_rate, rate);
drivers/clk/clk-cdce925.c
376
if (divider > 0x7F)
drivers/clk/clk-cdce925.c
377
divider = 0x7F;
drivers/clk/clk-cdce925.c
379
return (u16)divider;
drivers/clk/clk-cdce925.c
429
u16 divider = cdce925_calc_divider(req->rate, l_parent_rate);
drivers/clk/clk-cdce925.c
431
if (l_parent_rate / divider != req->rate) {
drivers/clk/clk-cdce925.c
433
divider = cdce925_calc_divider(req->rate, l_parent_rate);
drivers/clk/clk-cdce925.c
437
if (divider)
drivers/clk/clk-cdce925.c
438
req->rate = (long)(l_parent_rate / divider);
drivers/clk/clk-cdce925.c
467
unsigned long divider;
drivers/clk/clk-cdce925.c
474
divider = DIV_ROUND_CLOSEST(parent_rate, rate);
drivers/clk/clk-cdce925.c
475
if (divider > 0x3FF) /* Y1 has 10-bit divider */
drivers/clk/clk-cdce925.c
476
divider = 0x3FF;
drivers/clk/clk-cdce925.c
478
return (u16)divider;
drivers/clk/clk-cdce925.c
485
u16 divider = cdce925_y1_calc_divider(req->rate, l_parent_rate);
drivers/clk/clk-cdce925.c
487
if (divider)
drivers/clk/clk-cdce925.c
488
req->rate = (long)(l_parent_rate / divider);
drivers/clk/clk-divider.c
158
struct clk_divider *divider = to_clk_divider(hw);
drivers/clk/clk-divider.c
161
val = clk_div_readl(divider) >> divider->shift;
drivers/clk/clk-divider.c
162
val &= clk_div_mask(divider->width);
drivers/clk/clk-divider.c
164
return divider_recalc_rate(hw, parent_rate, val, divider->table,
drivers/clk/clk-divider.c
165
divider->flags, divider->width);
drivers/clk/clk-divider.c
29
static inline u32 clk_div_readl(struct clk_divider *divider)
drivers/clk/clk-divider.c
31
if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
drivers/clk/clk-divider.c
32
return ioread32be(divider->reg);
drivers/clk/clk-divider.c
34
return readl(divider->reg);
drivers/clk/clk-divider.c
37
static inline void clk_div_writel(struct clk_divider *divider, u32 val)
drivers/clk/clk-divider.c
39
if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
drivers/clk/clk-divider.c
40
iowrite32be(val, divider->reg);
drivers/clk/clk-divider.c
42
writel(val, divider->reg);
drivers/clk/clk-divider.c
437
struct clk_divider *divider = to_clk_divider(hw);
drivers/clk/clk-divider.c
440
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
drivers/clk/clk-divider.c
443
val = clk_div_readl(divider) >> divider->shift;
drivers/clk/clk-divider.c
444
val &= clk_div_mask(divider->width);
drivers/clk/clk-divider.c
446
return divider_ro_determine_rate(hw, req, divider->table,
drivers/clk/clk-divider.c
447
divider->width,
drivers/clk/clk-divider.c
448
divider->flags, val);
drivers/clk/clk-divider.c
451
return divider_determine_rate(hw, req, divider->table, divider->width,
drivers/clk/clk-divider.c
452
divider->flags);
drivers/clk/clk-divider.c
475
struct clk_divider *divider = to_clk_divider(hw);
drivers/clk/clk-divider.c
480
value = divider_get_val(rate, parent_rate, divider->table,
drivers/clk/clk-divider.c
481
divider->width, divider->flags);
drivers/clk/clk-divider.c
485
if (divider->lock)
drivers/clk/clk-divider.c
486
spin_lock_irqsave(divider->lock, flags);
drivers/clk/clk-divider.c
488
__acquire(divider->lock);
drivers/clk/clk-divider.c
490
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
drivers/clk/clk-divider.c
491
val = clk_div_mask(divider->width) << (divider->shift + 16);
drivers/clk/clk-divider.c
493
val = clk_div_readl(divider);
drivers/clk/clk-divider.c
494
val &= ~(clk_div_mask(divider->width) << divider->shift);
drivers/clk/clk-divider.c
496
val |= (u32)value << divider->shift;
drivers/clk/clk-divider.c
497
clk_div_writel(divider, val);
drivers/clk/clk-divider.c
499
if (divider->lock)
drivers/clk/clk-divider.c
500
spin_unlock_irqrestore(divider->lock, flags);
drivers/clk/clk-divider.c
502
__release(divider->lock);
drivers/clk/clk-milbeaut.c
379
struct m10v_clk_divider *divider = to_m10v_div(hw);
drivers/clk/clk-milbeaut.c
382
val = readl(divider->reg) >> divider->shift;
drivers/clk/clk-milbeaut.c
383
val &= clk_div_mask(divider->width);
drivers/clk/clk-milbeaut.c
385
return divider_recalc_rate(hw, parent_rate, val, divider->table,
drivers/clk/clk-milbeaut.c
386
divider->flags, divider->width);
drivers/clk/clk-milbeaut.c
392
struct m10v_clk_divider *divider = to_m10v_div(hw);
drivers/clk/clk-milbeaut.c
395
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
drivers/clk/clk-milbeaut.c
398
val = readl(divider->reg) >> divider->shift;
drivers/clk/clk-milbeaut.c
399
val &= clk_div_mask(divider->width);
drivers/clk/clk-milbeaut.c
401
return divider_ro_determine_rate(hw, req, divider->table,
drivers/clk/clk-milbeaut.c
402
divider->width, divider->flags,
drivers/clk/clk-milbeaut.c
406
return divider_determine_rate(hw, req, divider->table, divider->width, divider->flags);
drivers/clk/clk-milbeaut.c
412
struct m10v_clk_divider *divider = to_m10v_div(hw);
drivers/clk/clk-milbeaut.c
416
u32 write_en = BIT(divider->width - 1);
drivers/clk/clk-milbeaut.c
418
value = divider_get_val(rate, parent_rate, divider->table,
drivers/clk/clk-milbeaut.c
419
divider->width, divider->flags);
drivers/clk/clk-milbeaut.c
423
if (divider->lock)
drivers/clk/clk-milbeaut.c
424
spin_lock_irqsave(divider->lock, flags);
drivers/clk/clk-milbeaut.c
426
__acquire(divider->lock);
drivers/clk/clk-milbeaut.c
428
val = readl(divider->reg);
drivers/clk/clk-milbeaut.c
429
val &= ~(clk_div_mask(divider->width) << divider->shift);
drivers/clk/clk-milbeaut.c
431
val |= ((u32)value | write_en) << divider->shift;
drivers/clk/clk-milbeaut.c
432
writel(val, divider->reg);
drivers/clk/clk-milbeaut.c
434
if (divider->write_valid_reg) {
drivers/clk/clk-milbeaut.c
435
writel(M10V_DCHREQ, divider->write_valid_reg);
drivers/clk/clk-milbeaut.c
436
if (readl_poll_timeout(divider->write_valid_reg, val,
drivers/clk/clk-milbeaut.c
442
if (divider->lock)
drivers/clk/clk-milbeaut.c
443
spin_unlock_irqrestore(divider->lock, flags);
drivers/clk/clk-milbeaut.c
445
__release(divider->lock);
drivers/clk/clk-rp1.c
698
struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw);
drivers/clk/clk-rp1.c
699
struct rp1_clockman *clockman = divider->clockman;
drivers/clk/clk-rp1.c
700
const struct rp1_pll_data *data = divider->data;
drivers/clk/clk-rp1.c
707
struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw);
drivers/clk/clk-rp1.c
708
struct rp1_clockman *clockman = divider->clockman;
drivers/clk/clk-rp1.c
709
const struct rp1_pll_data *data = divider->data;
drivers/clk/clk-rp1.c
723
struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw);
drivers/clk/clk-rp1.c
724
struct rp1_clockman *clockman = divider->clockman;
drivers/clk/clk-rp1.c
725
const struct rp1_pll_data *data = divider->data;
drivers/clk/clk-rp1.c
737
struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw);
drivers/clk/clk-rp1.c
738
struct rp1_clockman *clockman = divider->clockman;
drivers/clk/clk-rp1.c
739
const struct rp1_pll_data *data = divider->data;
drivers/clk/clk-versaclock7.c
762
u32 *divider)
drivers/clk/clk-versaclock7.c
764
*divider = DIV_ROUND_UP(parent_rate, rate);
drivers/clk/clk-versaclock7.c
765
if (*divider < VC7_IOD_MIN_DIVISOR)
drivers/clk/clk-versaclock7.c
766
*divider = VC7_IOD_MIN_DIVISOR;
drivers/clk/clk-versaclock7.c
767
if (*divider > VC7_IOD_MAX_DIVISOR)
drivers/clk/clk-versaclock7.c
768
*divider = VC7_IOD_MAX_DIVISOR;
drivers/clk/clk-xgene.c
567
u32 divider;
drivers/clk/clk-xgene.c
577
divider_save = divider = parent_rate / rate; /* Rounded down */
drivers/clk/clk-xgene.c
578
divider &= (1 << pclk->param.reg_divider_width) - 1;
drivers/clk/clk-xgene.c
579
divider <<= pclk->param.reg_divider_shift;
drivers/clk/clk-xgene.c
586
data |= divider;
drivers/clk/clk-xgene.c
606
u32 divider;
drivers/clk/clk-xgene.c
612
divider = parent_rate / req->rate; /* Rounded down */
drivers/clk/clk-xgene.c
614
divider = 1;
drivers/clk/clk-xgene.c
617
req->rate = parent_rate / divider;
drivers/clk/davinci/pll.c
242
struct clk_divider *divider;
drivers/clk/davinci/pll.c
253
divider = kzalloc_obj(*divider);
drivers/clk/davinci/pll.c
254
if (!divider) {
drivers/clk/davinci/pll.c
259
divider->reg = reg;
drivers/clk/davinci/pll.c
260
divider->shift = DIV_RATIO_SHIFT;
drivers/clk/davinci/pll.c
261
divider->width = DIV_RATIO_WIDTH;
drivers/clk/davinci/pll.c
264
divider->flags |= CLK_DIVIDER_READ_ONLY;
drivers/clk/davinci/pll.c
269
NULL, NULL, ÷r->hw, divider_ops,
drivers/clk/davinci/pll.c
279
kfree(divider);
drivers/clk/davinci/pll.c
577
struct clk_divider *divider;
drivers/clk/davinci/pll.c
599
divider = kzalloc_obj(*divider);
drivers/clk/davinci/pll.c
600
if (!divider) {
drivers/clk/davinci/pll.c
605
divider->reg = base + OSCDIV;
drivers/clk/davinci/pll.c
606
divider->shift = DIV_RATIO_SHIFT;
drivers/clk/davinci/pll.c
607
divider->width = DIV_RATIO_WIDTH;
drivers/clk/davinci/pll.c
617
÷r->hw, &clk_divider_ops,
drivers/clk/davinci/pll.c
628
kfree(divider);
drivers/clk/davinci/pll.c
681
struct clk_divider *divider;
drivers/clk/davinci/pll.c
700
divider = kzalloc_obj(*divider);
drivers/clk/davinci/pll.c
701
if (!divider) {
drivers/clk/davinci/pll.c
706
divider->reg = base + reg;
drivers/clk/davinci/pll.c
707
divider->shift = DIV_RATIO_SHIFT;
drivers/clk/davinci/pll.c
708
divider->width = info->ratio_width;
drivers/clk/davinci/pll.c
709
divider->flags = 0;
drivers/clk/davinci/pll.c
712
divider->flags |= CLK_DIVIDER_READ_ONLY;
drivers/clk/davinci/pll.c
724
NULL, NULL, ÷r->hw, divider_ops,
drivers/clk/davinci/pll.c
736
kfree(divider);
drivers/clk/hisilicon/clk.h
154
hisi_clk_unregister(divider)
drivers/clk/imx/clk-composite-8m.c
102
writel(val, divider->reg);
drivers/clk/imx/clk-composite-8m.c
104
spin_unlock_irqrestore(divider->lock, flags);
drivers/clk/imx/clk-composite-8m.c
112
struct clk_divider *divider = to_clk_divider(hw);
drivers/clk/imx/clk-composite-8m.c
117
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
drivers/clk/imx/clk-composite-8m.c
120
val = readl(divider->reg);
drivers/clk/imx/clk-composite-8m.c
121
prediv_value = val >> divider->shift;
drivers/clk/imx/clk-composite-8m.c
122
prediv_value &= clk_div_mask(divider->width);
drivers/clk/imx/clk-composite-8m.c
129
return divider_ro_determine_rate(hw, req, divider->table,
drivers/clk/imx/clk-composite-8m.c
131
divider->flags, prediv_value * div_value);
drivers/clk/imx/clk-composite-8m.c
134
return divider_determine_rate(hw, req, divider->table,
drivers/clk/imx/clk-composite-8m.c
136
divider->flags);
drivers/clk/imx/clk-composite-8m.c
31
struct clk_divider *divider = to_clk_divider(hw);
drivers/clk/imx/clk-composite-8m.c
36
prediv_value = readl(divider->reg) >> divider->shift;
drivers/clk/imx/clk-composite-8m.c
37
prediv_value &= clk_div_mask(divider->width);
drivers/clk/imx/clk-composite-8m.c
40
NULL, divider->flags,
drivers/clk/imx/clk-composite-8m.c
41
divider->width);
drivers/clk/imx/clk-composite-8m.c
43
div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
drivers/clk/imx/clk-composite-8m.c
47
divider->flags, PCG_DIV_WIDTH);
drivers/clk/imx/clk-composite-8m.c
80
struct clk_divider *divider = to_clk_divider(hw);
drivers/clk/imx/clk-composite-8m.c
92
spin_lock_irqsave(divider->lock, flags);
drivers/clk/imx/clk-composite-8m.c
94
orig = readl(divider->reg);
drivers/clk/imx/clk-composite-8m.c
95
val = orig & ~((clk_div_mask(divider->width) << divider->shift) |
drivers/clk/imx/clk-composite-8m.c
98
val |= (u32)(prediv_value - 1) << divider->shift;
drivers/clk/imx/clk-composite-93.c
110
struct clk_divider *divider = to_clk_divider(hw);
drivers/clk/imx/clk-composite-93.c
116
value = divider_get_val(rate, parent_rate, divider->table, divider->width, divider->flags);
drivers/clk/imx/clk-composite-93.c
120
if (divider->lock)
drivers/clk/imx/clk-composite-93.c
121
spin_lock_irqsave(divider->lock, flags);
drivers/clk/imx/clk-composite-93.c
123
val = readl(divider->reg);
drivers/clk/imx/clk-composite-93.c
124
val &= ~(clk_div_mask(divider->width) << divider->shift);
drivers/clk/imx/clk-composite-93.c
125
val |= (u32)value << divider->shift;
drivers/clk/imx/clk-composite-93.c
126
writel(val, divider->reg);
drivers/clk/imx/clk-composite-93.c
128
ret = imx93_clk_composite_wait_ready(hw, divider->reg);
drivers/clk/imx/clk-composite-93.c
130
if (divider->lock)
drivers/clk/imx/clk-composite-93.c
131
spin_unlock_irqrestore(divider->lock, flags);
drivers/clk/imx/clk-divider-gate.c
15
struct clk_divider divider;
drivers/clk/imx/clk-divider-gate.c
201
div_gate->divider.reg = reg;
drivers/clk/imx/clk-divider-gate.c
202
div_gate->divider.shift = shift;
drivers/clk/imx/clk-divider-gate.c
203
div_gate->divider.width = width;
drivers/clk/imx/clk-divider-gate.c
204
div_gate->divider.lock = lock;
drivers/clk/imx/clk-divider-gate.c
205
div_gate->divider.table = table;
drivers/clk/imx/clk-divider-gate.c
206
div_gate->divider.hw.init = &init;
drivers/clk/imx/clk-divider-gate.c
207
div_gate->divider.flags = CLK_DIVIDER_ONE_BASED | clk_divider_flags;
drivers/clk/imx/clk-divider-gate.c
213
hw = &div_gate->divider.hw;
drivers/clk/imx/clk-divider-gate.c
23
return container_of(div, struct clk_divider_gate, divider);
drivers/clk/imx/clk-fixup-div.c
110
fixup_div->divider.reg = reg;
drivers/clk/imx/clk-fixup-div.c
111
fixup_div->divider.shift = shift;
drivers/clk/imx/clk-fixup-div.c
112
fixup_div->divider.width = width;
drivers/clk/imx/clk-fixup-div.c
113
fixup_div->divider.lock = &imx_ccm_lock;
drivers/clk/imx/clk-fixup-div.c
114
fixup_div->divider.hw.init = &init;
drivers/clk/imx/clk-fixup-div.c
118
hw = &fixup_div->divider.hw;
drivers/clk/imx/clk-fixup-div.c
24
struct clk_divider divider;
drivers/clk/imx/clk-fixup-div.c
31
struct clk_divider *divider = to_clk_divider(hw);
drivers/clk/imx/clk-fixup-div.c
33
return container_of(divider, struct clk_fixup_div, divider);
drivers/clk/imx/clk-fixup-div.c
41
return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate);
drivers/clk/imx/clk-fixup-div.c
49
return fixup_div->ops->determine_rate(&fixup_div->divider.hw, req);
drivers/clk/imx/clk-fixup-div.c
57
unsigned int divider, value;
drivers/clk/imx/clk-fixup-div.c
61
divider = parent_rate / rate;
drivers/clk/imx/clk-fixup-div.c
64
value = divider - 1;
drivers/clk/meson/vid-pll-div.c
29
unsigned int divider;
drivers/clk/meson/vid-pll-div.c
37
.divider = (_ft), \
drivers/clk/meson/vid-pll-div.c
84
if (!div || !div->divider) {
drivers/clk/meson/vid-pll-div.c
89
return DIV_ROUND_UP_ULL(parent_rate * div->multiplier, div->divider);
drivers/clk/microchip/clk-mpfs-ccc.c
118
struct clk_divider divider;
drivers/clk/microchip/clk-mpfs-ccc.c
126
.divider.shift = _shift, \
drivers/clk/microchip/clk-mpfs-ccc.c
127
.divider.width = _width, \
drivers/clk/microchip/clk-mpfs-ccc.c
129
.divider.flags = _flags, \
drivers/clk/microchip/clk-mpfs-ccc.c
130
.divider.lock = &mpfs_ccc_lock, \
drivers/clk/microchip/clk-mpfs-ccc.c
172
out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0);
drivers/clk/microchip/clk-mpfs-ccc.c
173
out_hw->divider.reg = data->pll_base[i / MPFS_CCC_OUTPUTS_PER_PLL] +
drivers/clk/microchip/clk-mpfs-ccc.c
176
ret = devm_clk_hw_register(dev, &out_hw->divider.hw);
drivers/clk/microchip/clk-mpfs-ccc.c
181
data->hw_data.hws[out_hw->id] = &out_hw->divider.hw;
drivers/clk/mvebu/ap-cpu-clk.c
163
int ret, reg, divider = parent_rate / rate;
drivers/clk/mvebu/ap-cpu-clk.c
175
reg |= (divider << clk->pll_regs->divider_offset);
drivers/clk/mvebu/ap-cpu-clk.c
183
reg |= ((divider * clk->pll_regs->divider_ratio) <<
drivers/clk/mvebu/ap-cpu-clk.c
216
int divider = req->best_parent_rate / req->rate;
drivers/clk/mvebu/ap-cpu-clk.c
218
divider = min(divider, APN806_MAX_DIVIDER);
drivers/clk/mvebu/ap-cpu-clk.c
220
req->rate = req->best_parent_rate / divider;
drivers/clk/mvebu/dove-divider.c
102
unsigned int divider = dove_get_divider(dc);
drivers/clk/mvebu/dove-divider.c
103
unsigned long rate = DIV_ROUND_CLOSEST(parent, divider);
drivers/clk/mvebu/dove-divider.c
106
__func__, dc->name, divider, parent, rate);
drivers/clk/mvebu/dove-divider.c
116
int divider;
drivers/clk/mvebu/dove-divider.c
118
divider = dove_calc_divider(dc, req->rate, parent_rate, false);
drivers/clk/mvebu/dove-divider.c
119
if (divider < 0)
drivers/clk/mvebu/dove-divider.c
120
return divider;
drivers/clk/mvebu/dove-divider.c
122
req->rate = DIV_ROUND_CLOSEST(parent_rate, divider);
drivers/clk/mvebu/dove-divider.c
125
__func__, dc->name, divider, parent_rate, req->rate);
drivers/clk/mvebu/dove-divider.c
135
int divider;
drivers/clk/mvebu/dove-divider.c
137
divider = dove_calc_divider(dc, rate, parent_rate, true);
drivers/clk/mvebu/dove-divider.c
138
if (divider < 0)
drivers/clk/mvebu/dove-divider.c
139
return divider;
drivers/clk/mvebu/dove-divider.c
142
__func__, dc->name, divider, parent_rate, rate);
drivers/clk/mvebu/dove-divider.c
144
div = (u32)divider << dc->div_bit_start;
drivers/clk/mvebu/dove-divider.c
53
unsigned int divider;
drivers/clk/mvebu/dove-divider.c
59
divider = val & ~(~0 << dc->div_bit_size);
drivers/clk/mvebu/dove-divider.c
62
divider = dc->divider_table[divider];
drivers/clk/mvebu/dove-divider.c
64
return divider;
drivers/clk/mvebu/dove-divider.c
70
unsigned int divider, max;
drivers/clk/mvebu/dove-divider.c
72
divider = DIV_ROUND_CLOSEST(parent_rate, rate);
drivers/clk/mvebu/dove-divider.c
78
if (divider == dc->divider_table[i]) {
drivers/clk/mvebu/dove-divider.c
79
divider = i;
drivers/clk/mvebu/dove-divider.c
88
if (set && (divider == 0 || divider >= max))
drivers/clk/mvebu/dove-divider.c
90
if (divider >= max)
drivers/clk/mvebu/dove-divider.c
91
divider = max - 1;
drivers/clk/mvebu/dove-divider.c
92
else if (divider == 0)
drivers/clk/mvebu/dove-divider.c
93
divider = 1;
drivers/clk/mvebu/dove-divider.c
96
return divider;
drivers/clk/mxs/clk-div.c
22
struct clk_divider divider;
drivers/clk/mxs/clk-div.c
30
struct clk_divider *divider = to_clk_divider(hw);
drivers/clk/mxs/clk-div.c
32
return container_of(divider, struct clk_div, divider);
drivers/clk/mxs/clk-div.c
40
return div->ops->recalc_rate(&div->divider.hw, parent_rate);
drivers/clk/mxs/clk-div.c
48
return div->ops->determine_rate(&div->divider.hw, req);
drivers/clk/mxs/clk-div.c
57
ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate);
drivers/clk/mxs/clk-div.c
90
div->divider.reg = reg;
drivers/clk/mxs/clk-div.c
91
div->divider.shift = shift;
drivers/clk/mxs/clk-div.c
92
div->divider.width = width;
drivers/clk/mxs/clk-div.c
93
div->divider.flags = CLK_DIVIDER_ONE_BASED;
drivers/clk/mxs/clk-div.c
94
div->divider.lock = &mxs_lock;
drivers/clk/mxs/clk-div.c
95
div->divider.hw.init = &init;
drivers/clk/mxs/clk-div.c
98
clk = clk_register(NULL, &div->divider.hw);
drivers/clk/nxp/clk-lpc32xx.c
948
struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw);
drivers/clk/nxp/clk-lpc32xx.c
951
regmap_read(clk_regmap, divider->reg, &val);
drivers/clk/nxp/clk-lpc32xx.c
953
val >>= divider->shift;
drivers/clk/nxp/clk-lpc32xx.c
954
val &= div_mask(divider->width);
drivers/clk/nxp/clk-lpc32xx.c
956
return divider_recalc_rate(hw, parent_rate, val, divider->table,
drivers/clk/nxp/clk-lpc32xx.c
957
divider->flags, divider->width);
drivers/clk/nxp/clk-lpc32xx.c
963
struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw);
drivers/clk/nxp/clk-lpc32xx.c
967
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
drivers/clk/nxp/clk-lpc32xx.c
968
regmap_read(clk_regmap, divider->reg, &bestdiv);
drivers/clk/nxp/clk-lpc32xx.c
969
bestdiv >>= divider->shift;
drivers/clk/nxp/clk-lpc32xx.c
970
bestdiv &= div_mask(divider->width);
drivers/clk/nxp/clk-lpc32xx.c
971
bestdiv = _get_div(divider->table, bestdiv, divider->flags,
drivers/clk/nxp/clk-lpc32xx.c
972
divider->width);
drivers/clk/nxp/clk-lpc32xx.c
978
return divider_determine_rate(hw, req, divider->table, divider->width,
drivers/clk/nxp/clk-lpc32xx.c
979
divider->flags);
drivers/clk/nxp/clk-lpc32xx.c
985
struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw);
drivers/clk/nxp/clk-lpc32xx.c
988
value = divider_get_val(rate, parent_rate, divider->table,
drivers/clk/nxp/clk-lpc32xx.c
989
divider->width, divider->flags);
drivers/clk/nxp/clk-lpc32xx.c
991
return regmap_update_bits(clk_regmap, divider->reg,
drivers/clk/nxp/clk-lpc32xx.c
992
div_mask(divider->width) << divider->shift,
drivers/clk/nxp/clk-lpc32xx.c
993
value << divider->shift);
drivers/clk/qcom/clk-regmap-divider.c
21
struct clk_regmap_div *divider = to_clk_regmap_div(hw);
drivers/clk/qcom/clk-regmap-divider.c
22
struct clk_regmap *clkr = ÷r->clkr;
drivers/clk/qcom/clk-regmap-divider.c
25
regmap_read(clkr->regmap, divider->reg, &val);
drivers/clk/qcom/clk-regmap-divider.c
26
val >>= divider->shift;
drivers/clk/qcom/clk-regmap-divider.c
27
val &= BIT(divider->width) - 1;
drivers/clk/qcom/clk-regmap-divider.c
29
return divider_ro_determine_rate(hw, req, NULL, divider->width,
drivers/clk/qcom/clk-regmap-divider.c
35
struct clk_regmap_div *divider = to_clk_regmap_div(hw);
drivers/clk/qcom/clk-regmap-divider.c
37
return divider_determine_rate(hw, req, NULL, divider->width,
drivers/clk/qcom/clk-regmap-divider.c
44
struct clk_regmap_div *divider = to_clk_regmap_div(hw);
drivers/clk/qcom/clk-regmap-divider.c
45
struct clk_regmap *clkr = ÷r->clkr;
drivers/clk/qcom/clk-regmap-divider.c
48
div = divider_get_val(rate, parent_rate, NULL, divider->width,
drivers/clk/qcom/clk-regmap-divider.c
51
return regmap_update_bits(clkr->regmap, divider->reg,
drivers/clk/qcom/clk-regmap-divider.c
52
(BIT(divider->width) - 1) << divider->shift,
drivers/clk/qcom/clk-regmap-divider.c
53
div << divider->shift);
drivers/clk/qcom/clk-regmap-divider.c
59
struct clk_regmap_div *divider = to_clk_regmap_div(hw);
drivers/clk/qcom/clk-regmap-divider.c
60
struct clk_regmap *clkr = ÷r->clkr;
drivers/clk/qcom/clk-regmap-divider.c
63
regmap_read(clkr->regmap, divider->reg, &div);
drivers/clk/qcom/clk-regmap-divider.c
64
div >>= divider->shift;
drivers/clk/qcom/clk-regmap-divider.c
65
div &= BIT(divider->width) - 1;
drivers/clk/qcom/clk-regmap-divider.c
68
CLK_DIVIDER_ROUND_CLOSEST, divider->width);
drivers/clk/renesas/r9a09g077-cpg.c
363
struct clk_divider *divider = to_clk_divider(hw);
drivers/clk/renesas/r9a09g077-cpg.c
377
for (clkt = divider->table; clkt->div; clkt++) {
drivers/clk/renesas/rzg2l-cpg.c
752
void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target)
drivers/clk/renesas/rzg2l-cpg.c
754
dsi_div_ab_desired = divider;
drivers/clk/renesas/rzv2h-cpg.c
253
u16 divider;
drivers/clk/renesas/rzv2h-cpg.c
255
for (divider = 1 << limits->s.min, p.s = limits->s.min;
drivers/clk/renesas/rzv2h-cpg.c
256
p.s <= limits->s.max; p.s++, divider <<= 1) {
drivers/clk/renesas/rzv2h-cpg.c
290
divider);
drivers/clk/renesas/rzv2h-cpg.c
293
2 * divider);
drivers/clk/renesas/rzv2h-cpg.c
315
pll_k = div_s64(output_k * 65536ULL * divider,
drivers/clk/renesas/rzv2h-cpg.c
338
output = DIV_U64_ROUND_CLOSEST(output, 65536 * p.p * divider);
drivers/clk/renesas/rzv2h-cpg.c
779
struct clk_divider *divider = to_clk_divider(hw);
drivers/clk/renesas/rzv2h-cpg.c
782
val = readl(divider->reg) >> divider->shift;
drivers/clk/renesas/rzv2h-cpg.c
783
val &= clk_div_mask(divider->width);
drivers/clk/renesas/rzv2h-cpg.c
785
return divider_recalc_rate(hw, parent_rate, val, divider->table,
drivers/clk/renesas/rzv2h-cpg.c
786
divider->flags, divider->width);
drivers/clk/renesas/rzv2h-cpg.c
792
struct clk_divider *divider = to_clk_divider(hw);
drivers/clk/renesas/rzv2h-cpg.c
794
return divider_determine_rate(hw, req, divider->table, divider->width,
drivers/clk/renesas/rzv2h-cpg.c
795
divider->flags);
drivers/clk/renesas/rzv2h-cpg.c
812
struct clk_divider *divider = to_clk_divider(hw);
drivers/clk/renesas/rzv2h-cpg.c
813
struct ddiv_clk *ddiv = to_ddiv_clock(divider);
drivers/clk/renesas/rzv2h-cpg.c
820
value = divider_get_val(rate, parent_rate, divider->table,
drivers/clk/renesas/rzv2h-cpg.c
821
divider->width, divider->flags);
drivers/clk/renesas/rzv2h-cpg.c
825
spin_lock_irqsave(divider->lock, flags);
drivers/clk/renesas/rzv2h-cpg.c
831
val = readl(divider->reg) | DDIV_DIVCTL_WEN(divider->shift);
drivers/clk/renesas/rzv2h-cpg.c
832
val &= ~(clk_div_mask(divider->width) << divider->shift);
drivers/clk/renesas/rzv2h-cpg.c
833
val |= (u32)value << divider->shift;
drivers/clk/renesas/rzv2h-cpg.c
834
writel(val, divider->reg);
drivers/clk/renesas/rzv2h-cpg.c
839
spin_unlock_irqrestore(divider->lock, flags);
drivers/clk/rockchip/clk-half-divider.c
102
divider->width,
drivers/clk/rockchip/clk-half-divider.c
103
divider->flags);
drivers/clk/rockchip/clk-half-divider.c
113
struct clk_divider *divider = to_clk_divider(hw);
drivers/clk/rockchip/clk-half-divider.c
120
value = min_t(unsigned int, value, div_mask(divider->width));
drivers/clk/rockchip/clk-half-divider.c
122
if (divider->lock)
drivers/clk/rockchip/clk-half-divider.c
123
spin_lock_irqsave(divider->lock, flags);
drivers/clk/rockchip/clk-half-divider.c
125
__acquire(divider->lock);
drivers/clk/rockchip/clk-half-divider.c
127
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
drivers/clk/rockchip/clk-half-divider.c
128
val = div_mask(divider->width) << (divider->shift + 16);
drivers/clk/rockchip/clk-half-divider.c
130
val = readl(divider->reg);
drivers/clk/rockchip/clk-half-divider.c
131
val &= ~(div_mask(divider->width) << divider->shift);
drivers/clk/rockchip/clk-half-divider.c
133
val |= value << divider->shift;
drivers/clk/rockchip/clk-half-divider.c
134
writel(val, divider->reg);
drivers/clk/rockchip/clk-half-divider.c
136
if (divider->lock)
drivers/clk/rockchip/clk-half-divider.c
137
spin_unlock_irqrestore(divider->lock, flags);
drivers/clk/rockchip/clk-half-divider.c
139
__release(divider->lock);
drivers/clk/rockchip/clk-half-divider.c
25
struct clk_divider *divider = to_clk_divider(hw);
drivers/clk/rockchip/clk-half-divider.c
28
val = readl(divider->reg) >> divider->shift;
drivers/clk/rockchip/clk-half-divider.c
29
val &= div_mask(divider->width);
drivers/clk/rockchip/clk-half-divider.c
98
struct clk_divider *divider = to_clk_divider(hw);
drivers/clk/sophgo/clk-sg2042-clkgen.c
160
struct sg2042_divider_clock *divider = to_sg2042_clk_divider(hw);
drivers/clk/sophgo/clk-sg2042-clkgen.c
164
if (!(readl(divider->reg) & BIT(SHIFT_DIV_FACTOR_SEL))) {
drivers/clk/sophgo/clk-sg2042-clkgen.c
165
val = divider->initval;
drivers/clk/sophgo/clk-sg2042-clkgen.c
167
val = readl(divider->reg) >> divider->shift;
drivers/clk/sophgo/clk-sg2042-clkgen.c
168
val &= clk_div_mask(divider->width);
drivers/clk/sophgo/clk-sg2042-clkgen.c
172
divider->div_flags, divider->width);
drivers/clk/sophgo/clk-sg2042-clkgen.c
182
struct sg2042_divider_clock *divider = to_sg2042_clk_divider(hw);
drivers/clk/sophgo/clk-sg2042-clkgen.c
186
if (divider->div_flags & CLK_DIVIDER_READ_ONLY) {
drivers/clk/sophgo/clk-sg2042-clkgen.c
187
if (!(readl(divider->reg) & BIT(SHIFT_DIV_FACTOR_SEL))) {
drivers/clk/sophgo/clk-sg2042-clkgen.c
188
bestdiv = divider->initval;
drivers/clk/sophgo/clk-sg2042-clkgen.c
190
bestdiv = readl(divider->reg) >> divider->shift;
drivers/clk/sophgo/clk-sg2042-clkgen.c
191
bestdiv &= clk_div_mask(divider->width);
drivers/clk/sophgo/clk-sg2042-clkgen.c
198
return divider_determine_rate(hw, req, NULL, divider->width,
drivers/clk/sophgo/clk-sg2042-clkgen.c
199
divider->div_flags);
drivers/clk/sophgo/clk-sg2042-clkgen.c
206
struct sg2042_divider_clock *divider = to_sg2042_clk_divider(hw);
drivers/clk/sophgo/clk-sg2042-clkgen.c
211
divider->width, divider->div_flags);
drivers/clk/sophgo/clk-sg2042-clkgen.c
213
if (divider->lock)
drivers/clk/sophgo/clk-sg2042-clkgen.c
214
spin_lock_irqsave(divider->lock, flags);
drivers/clk/sophgo/clk-sg2042-clkgen.c
216
__acquire(divider->lock);
drivers/clk/sophgo/clk-sg2042-clkgen.c
224
val = readl(divider->reg);
drivers/clk/sophgo/clk-sg2042-clkgen.c
228
writel(val, divider->reg);
drivers/clk/sophgo/clk-sg2042-clkgen.c
230
if (divider->div_flags & CLK_DIVIDER_HIWORD_MASK) {
drivers/clk/sophgo/clk-sg2042-clkgen.c
231
val = clk_div_mask(divider->width) << (divider->shift + 16);
drivers/clk/sophgo/clk-sg2042-clkgen.c
233
val = readl(divider->reg);
drivers/clk/sophgo/clk-sg2042-clkgen.c
234
val &= ~(clk_div_mask(divider->width) << divider->shift);
drivers/clk/sophgo/clk-sg2042-clkgen.c
236
val |= value << divider->shift;
drivers/clk/sophgo/clk-sg2042-clkgen.c
238
writel(val, divider->reg);
drivers/clk/sophgo/clk-sg2042-clkgen.c
243
writel(val, divider->reg);
drivers/clk/sophgo/clk-sg2042-clkgen.c
245
if (divider->lock)
drivers/clk/sophgo/clk-sg2042-clkgen.c
246
spin_unlock_irqrestore(divider->lock, flags);
drivers/clk/sophgo/clk-sg2042-clkgen.c
248
__release(divider->lock);
drivers/clk/stm32/clk-stm32-core.c
212
const struct stm32_div_cfg *divider = &data->dividers[div_id];
drivers/clk/stm32/clk-stm32-core.c
216
val = readl(base + divider->offset) >> divider->shift;
drivers/clk/stm32/clk-stm32-core.c
217
val &= clk_div_mask(divider->width);
drivers/clk/stm32/clk-stm32-core.c
218
div = _get_div(divider->table, val, divider->flags, divider->width);
drivers/clk/stm32/clk-stm32-core.c
221
WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
drivers/clk/stm32/clk-stm32-core.c
235
const struct stm32_div_cfg *divider = &data->dividers[div_id];
drivers/clk/stm32/clk-stm32-core.c
239
value = divider_get_val(rate, parent_rate, divider->table,
drivers/clk/stm32/clk-stm32-core.c
240
divider->width, divider->flags);
drivers/clk/stm32/clk-stm32-core.c
244
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
drivers/clk/stm32/clk-stm32-core.c
245
val = clk_div_mask(divider->width) << (divider->shift + 16);
drivers/clk/stm32/clk-stm32-core.c
247
val = readl(base + divider->offset);
drivers/clk/stm32/clk-stm32-core.c
248
val &= ~(clk_div_mask(divider->width) << divider->shift);
drivers/clk/stm32/clk-stm32-core.c
251
val |= (u32)value << divider->shift;
drivers/clk/stm32/clk-stm32-core.c
253
writel(val, base + divider->offset);
drivers/clk/stm32/clk-stm32-core.c
358
const struct stm32_div_cfg *divider;
drivers/clk/stm32/clk-stm32-core.c
363
divider = &div->clock_data->dividers[div->div_id];
drivers/clk/stm32/clk-stm32-core.c
366
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
drivers/clk/stm32/clk-stm32-core.c
369
val = readl(div->base + divider->offset) >> divider->shift;
drivers/clk/stm32/clk-stm32-core.c
370
val &= clk_div_mask(divider->width);
drivers/clk/stm32/clk-stm32-core.c
373
divider->table,
drivers/clk/stm32/clk-stm32-core.c
374
divider->width,
drivers/clk/stm32/clk-stm32-core.c
375
divider->flags, val);
drivers/clk/stm32/clk-stm32-core.c
378
return divider_determine_rate(hw, req, divider->table, divider->width,
drivers/clk/stm32/clk-stm32-core.c
379
divider->flags);
drivers/clk/stm32/clk-stm32-core.c
435
const struct stm32_div_cfg *divider;
drivers/clk/stm32/clk-stm32-core.c
440
divider = &composite->clock_data->dividers[composite->div_id];
drivers/clk/stm32/clk-stm32-core.c
443
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
drivers/clk/stm32/clk-stm32-core.c
446
val = readl(composite->base + divider->offset) >> divider->shift;
drivers/clk/stm32/clk-stm32-core.c
447
val &= clk_div_mask(divider->width);
drivers/clk/stm32/clk-stm32-core.c
449
return divider_ro_determine_rate(hw, req, divider->table,
drivers/clk/stm32/clk-stm32-core.c
450
divider->width, divider->flags,
drivers/clk/stm32/clk-stm32-core.c
454
return divider_determine_rate(hw, req, divider->table, divider->width,
drivers/clk/stm32/clk-stm32-core.c
455
divider->flags);
drivers/clk/sunxi/clk-sunxi.c
1048
divider = kzalloc_obj(*divider);
drivers/clk/sunxi/clk-sunxi.c
1049
if (!divider)
drivers/clk/sunxi/clk-sunxi.c
1054
divider->reg = reg;
drivers/clk/sunxi/clk-sunxi.c
1055
divider->shift = data->div[i].shift;
drivers/clk/sunxi/clk-sunxi.c
1056
divider->width = SUNXI_DIVISOR_WIDTH;
drivers/clk/sunxi/clk-sunxi.c
1057
divider->flags = flags;
drivers/clk/sunxi/clk-sunxi.c
1058
divider->lock = &clk_lock;
drivers/clk/sunxi/clk-sunxi.c
1059
divider->table = data->div[i].table;
drivers/clk/sunxi/clk-sunxi.c
1061
rate_hw = ÷r->hw;
drivers/clk/sunxi/clk-sunxi.c
943
struct clk_divider *divider;
drivers/clk/tegra/clk-divider.c
100
if (divider->lock)
drivers/clk/tegra/clk-divider.c
101
spin_lock_irqsave(divider->lock, flags);
drivers/clk/tegra/clk-divider.c
103
val = readl_relaxed(divider->reg);
drivers/clk/tegra/clk-divider.c
104
val &= ~(div_mask(divider) << divider->shift);
drivers/clk/tegra/clk-divider.c
105
val |= div << divider->shift;
drivers/clk/tegra/clk-divider.c
107
if (divider->flags & TEGRA_DIVIDER_UART) {
drivers/clk/tegra/clk-divider.c
114
if (divider->flags & TEGRA_DIVIDER_FIXED)
drivers/clk/tegra/clk-divider.c
115
val |= pll_out_override(divider);
drivers/clk/tegra/clk-divider.c
117
writel_relaxed(val, divider->reg);
drivers/clk/tegra/clk-divider.c
119
if (divider->lock)
drivers/clk/tegra/clk-divider.c
120
spin_unlock_irqrestore(divider->lock, flags);
drivers/clk/tegra/clk-divider.c
147
struct tegra_clk_frac_div *divider;
drivers/clk/tegra/clk-divider.c
151
divider = kzalloc_obj(*divider);
drivers/clk/tegra/clk-divider.c
152
if (!divider) {
drivers/clk/tegra/clk-divider.c
164
divider->reg = reg;
drivers/clk/tegra/clk-divider.c
165
divider->shift = shift;
drivers/clk/tegra/clk-divider.c
166
divider->width = width;
drivers/clk/tegra/clk-divider.c
167
divider->frac_width = frac_width;
drivers/clk/tegra/clk-divider.c
168
divider->lock = lock;
drivers/clk/tegra/clk-divider.c
169
divider->flags = clk_divider_flags;
drivers/clk/tegra/clk-divider.c
172
divider->hw.init = &init;
drivers/clk/tegra/clk-divider.c
174
clk = clk_register(NULL, ÷r->hw);
drivers/clk/tegra/clk-divider.c
176
kfree(divider);
drivers/clk/tegra/clk-divider.c
21
static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate,
drivers/clk/tegra/clk-divider.c
26
div = div_frac_get(rate, parent_rate, divider->width,
drivers/clk/tegra/clk-divider.c
27
divider->frac_width, divider->flags);
drivers/clk/tegra/clk-divider.c
38
struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
drivers/clk/tegra/clk-divider.c
43
reg = readl_relaxed(divider->reg);
drivers/clk/tegra/clk-divider.c
45
if ((divider->flags & TEGRA_DIVIDER_UART) &&
drivers/clk/tegra/clk-divider.c
49
div = (reg >> divider->shift) & div_mask(divider);
drivers/clk/tegra/clk-divider.c
51
mul = get_mul(divider);
drivers/clk/tegra/clk-divider.c
64
struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
drivers/clk/tegra/clk-divider.c
74
div = get_div(divider, req->rate, output_rate);
drivers/clk/tegra/clk-divider.c
81
mul = get_mul(divider);
drivers/clk/tegra/clk-divider.c
91
struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
drivers/clk/tegra/clk-divider.c
96
div = get_div(divider, rate, parent_rate);
drivers/clk/tegra/clk-periph.c
116
struct clk_hw *div_hw = &periph->divider.hw;
drivers/clk/tegra/clk-periph.c
194
periph->divider.reg = div ? (clk_base + offset) : NULL;
drivers/clk/tegra/clk-periph.c
204
periph->divider.hw.clk = div ? clk : NULL;
drivers/clk/tegra/clk-periph.c
41
struct clk_hw *div_hw = &periph->divider.hw;
drivers/clk/tegra/clk-periph.c
53
struct clk_hw *div_hw = &periph->divider.hw;
drivers/clk/tegra/clk-periph.c
65
struct clk_hw *div_hw = &periph->divider.hw;
drivers/clk/tegra/clk-tegra-periph.c
930
data->flags, data->periph.divider.flags,
drivers/clk/tegra/clk-tegra-periph.c
931
data->periph.divider.shift,
drivers/clk/tegra/clk-tegra-periph.c
932
data->periph.divider.width,
drivers/clk/tegra/clk-tegra-periph.c
933
data->periph.divider.frac_width,
drivers/clk/tegra/clk-tegra-periph.c
934
data->periph.divider.lock);
drivers/clk/tegra/clk.h
620
struct tegra_clk_frac_div divider;
drivers/clk/tegra/clk.h
653
.divider = { \
drivers/clk/ti/adpll.c
442
u32 frac_m, divider, v;
drivers/clk/ti/adpll.c
455
divider = (readw_relaxed(d->regs + ADPLL_M2NDIV_OFFSET) + 1) << 18;
drivers/clk/ti/adpll.c
458
do_div(rate, divider);
drivers/clk/ti/clk-dra7-atl.c
120
return parent_rate / cdesc->divider;
drivers/clk/ti/clk-dra7-atl.c
126
unsigned divider;
drivers/clk/ti/clk-dra7-atl.c
128
divider = (req->best_parent_rate + req->rate / 2) / req->rate;
drivers/clk/ti/clk-dra7-atl.c
129
if (divider > DRA7_ATL_DIVIDER_MASK + 1)
drivers/clk/ti/clk-dra7-atl.c
130
divider = DRA7_ATL_DIVIDER_MASK + 1;
drivers/clk/ti/clk-dra7-atl.c
132
req->rate = req->best_parent_rate / divider;
drivers/clk/ti/clk-dra7-atl.c
141
u32 divider;
drivers/clk/ti/clk-dra7-atl.c
147
divider = ((parent_rate + rate / 2) / rate) - 1;
drivers/clk/ti/clk-dra7-atl.c
148
if (divider > DRA7_ATL_DIVIDER_MASK)
drivers/clk/ti/clk-dra7-atl.c
149
divider = DRA7_ATL_DIVIDER_MASK;
drivers/clk/ti/clk-dra7-atl.c
151
cdesc->divider = divider + 1;
drivers/clk/ti/clk-dra7-atl.c
180
clk_hw->divider = 1;
drivers/clk/ti/clk-dra7-atl.c
49
u32 divider; /* Cached divider value */
drivers/clk/ti/clk-dra7-atl.c
85
cdesc->divider - 1);
drivers/clk/ti/divider.c
100
val &= divider->mask;
drivers/clk/ti/divider.c
102
div = _get_div(divider, val);
drivers/clk/ti/divider.c
104
WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
drivers/clk/ti/divider.c
130
static bool _is_valid_div(struct clk_omap_divider *divider, unsigned int div)
drivers/clk/ti/divider.c
132
if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
drivers/clk/ti/divider.c
134
if (divider->table)
drivers/clk/ti/divider.c
135
return _is_valid_table_div(divider->table, div);
drivers/clk/ti/divider.c
171
struct clk_omap_divider *divider = to_clk_omap_divider(hw);
drivers/clk/ti/divider.c
179
maxdiv = divider->max;
drivers/clk/ti/divider.c
183
bestdiv = _div_round(divider->table, parent_rate, rate);
drivers/clk/ti/divider.c
196
if (!_is_valid_div(divider, i))
drivers/clk/ti/divider.c
218
bestdiv = divider->max;
drivers/clk/ti/divider.c
240
struct clk_omap_divider *divider;
drivers/clk/ti/divider.c
247
divider = to_clk_omap_divider(hw);
drivers/clk/ti/divider.c
251
if (div > divider->max)
drivers/clk/ti/divider.c
252
div = divider->max;
drivers/clk/ti/divider.c
253
if (div < divider->min)
drivers/clk/ti/divider.c
254
div = divider->min;
drivers/clk/ti/divider.c
256
value = _get_val(divider, div);
drivers/clk/ti/divider.c
258
val = ti_clk_ll_ops->clk_readl(÷r->reg);
drivers/clk/ti/divider.c
259
val &= ~(divider->mask << divider->shift);
drivers/clk/ti/divider.c
260
val |= value << divider->shift;
drivers/clk/ti/divider.c
261
ti_clk_ll_ops->clk_writel(val, ÷r->reg);
drivers/clk/ti/divider.c
263
ti_clk_latch(÷r->reg, divider->latch);
drivers/clk/ti/divider.c
276
struct clk_omap_divider *divider = to_clk_omap_divider(hw);
drivers/clk/ti/divider.c
279
val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift;
drivers/clk/ti/divider.c
280
divider->context = val & divider->mask;
drivers/clk/ti/divider.c
293
struct clk_omap_divider *divider = to_clk_omap_divider(hw);
drivers/clk/ti/divider.c
296
val = ti_clk_ll_ops->clk_readl(÷r->reg);
drivers/clk/ti/divider.c
297
val &= ~(divider->mask << divider->shift);
drivers/clk/ti/divider.c
298
val |= divider->context << divider->shift;
drivers/clk/ti/divider.c
299
ti_clk_ll_ops->clk_writel(val, ÷r->reg);
drivers/clk/ti/divider.c
32
static void _setup_mask(struct clk_omap_divider *divider)
drivers/clk/ti/divider.c
334
u8 flags, struct clk_omap_divider *divider)
drivers/clk/ti/divider.c
342
divider->min = 1;
drivers/clk/ti/divider.c
343
divider->max = max_div;
drivers/clk/ti/divider.c
344
_setup_mask(divider);
drivers/clk/ti/divider.c
377
divider->min = min_div;
drivers/clk/ti/divider.c
378
divider->max = max_div;
drivers/clk/ti/divider.c
379
divider->table = tmp;
drivers/clk/ti/divider.c
38
if (divider->table) {
drivers/clk/ti/divider.c
380
_setup_mask(divider);
drivers/clk/ti/divider.c
41
for (clkt = divider->table; clkt->div; clkt++)
drivers/clk/ti/divider.c
437
struct clk_omap_divider *divider)
drivers/clk/ti/divider.c
444
if (!divider->table) {
drivers/clk/ti/divider.c
45
max_val = divider->max;
drivers/clk/ti/divider.c
455
for (clkt = divider->table; clkt->div; clkt++) {
drivers/clk/ti/divider.c
464
divider->min = min_div;
drivers/clk/ti/divider.c
465
divider->max = max_div;
drivers/clk/ti/divider.c
466
_setup_mask(divider);
drivers/clk/ti/divider.c
47
if (!(divider->flags & CLK_DIVIDER_ONE_BASED) &&
drivers/clk/ti/divider.c
48
!(divider->flags & CLK_DIVIDER_POWER_OF_TWO))
drivers/clk/ti/divider.c
52
if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
drivers/clk/ti/divider.c
57
divider->mask = (1 << fls(mask)) - 1;
drivers/clk/ti/divider.c
60
static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val)
drivers/clk/ti/divider.c
62
if (divider->flags & CLK_DIVIDER_ONE_BASED)
drivers/clk/ti/divider.c
64
if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
drivers/clk/ti/divider.c
66
if (divider->table)
drivers/clk/ti/divider.c
67
return _get_table_div(divider->table, val);
drivers/clk/ti/divider.c
82
static unsigned int _get_val(struct clk_omap_divider *divider, u8 div)
drivers/clk/ti/divider.c
84
if (divider->flags & CLK_DIVIDER_ONE_BASED)
drivers/clk/ti/divider.c
86
if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
drivers/clk/ti/divider.c
88
if (divider->table)
drivers/clk/ti/divider.c
89
return _get_table_val(divider->table, div);
drivers/clk/ti/divider.c
96
struct clk_omap_divider *divider = to_clk_omap_divider(hw);
drivers/clk/ti/divider.c
99
val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift;
drivers/clk/ux500/clk-prcmu.c
29
u8 divider;
drivers/clk/ux500/clk-prcmu.c
304
return prcmu_config_clkout(clk->clkout_id, clk->source, clk->divider);
drivers/clk/ux500/clk-prcmu.c
324
return (parent_rate / clk->divider);
drivers/clk/ux500/clk-prcmu.c
357
u8 source, u8 divider)
drivers/clk/ux500/clk-prcmu.c
385
clk->divider = divider;
drivers/clk/ux500/clk.h
66
u8 source, u8 divider);
drivers/clk/ux500/u8500_of_clk.c
103
if (divider == 0 || divider > 63) {
drivers/clk/ux500/u8500_of_clk.c
104
pr_err("%s: invalid divider %d\n", __func__, divider);
drivers/clk/ux500/u8500_of_clk.c
109
id + 1, source, divider);
drivers/clk/ux500/u8500_of_clk.c
114
source, divider);
drivers/clk/ux500/u8500_of_clk.c
77
u32 id, source, divider;
drivers/clk/ux500/u8500_of_clk.c
85
divider = clkspec->args[2];
drivers/clk/x86/clk-cgu.c
125
struct lgm_clk_divider *divider = to_lgm_clk_divider(hw);
drivers/clk/x86/clk-cgu.c
128
val = lgm_get_clk_val(divider->membase, divider->reg,
drivers/clk/x86/clk-cgu.c
129
divider->shift, divider->width);
drivers/clk/x86/clk-cgu.c
131
return divider_recalc_rate(hw, parent_rate, val, divider->table,
drivers/clk/x86/clk-cgu.c
132
divider->flags, divider->width);
drivers/clk/x86/clk-cgu.c
138
struct lgm_clk_divider *divider = to_lgm_clk_divider(hw);
drivers/clk/x86/clk-cgu.c
140
return divider_determine_rate(hw, req, divider->table, divider->width,
drivers/clk/x86/clk-cgu.c
141
divider->flags);
drivers/clk/x86/clk-cgu.c
148
struct lgm_clk_divider *divider = to_lgm_clk_divider(hw);
drivers/clk/x86/clk-cgu.c
151
value = divider_get_val(rate, prate, divider->table,
drivers/clk/x86/clk-cgu.c
152
divider->width, divider->flags);
drivers/clk/x86/clk-cgu.c
156
lgm_set_clk_val(divider->membase, divider->reg,
drivers/clk/x86/clk-cgu.c
157
divider->shift, divider->width, value);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
199
struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
200
void __iomem *div_addr = divider->base + divider->offset;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
224
struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
225
void __iomem *div_addr = divider->base + divider->offset;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
228
val = readl(div_addr) >> divider->shift;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
229
val &= div_mask(divider->width);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
231
return divider_recalc_rate(hw, parent_rate, val, divider->table,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
232
divider->flags, divider->width);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
238
struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
239
void __iomem *div_addr = divider->base + divider->offset;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
244
spin_lock_irqsave(divider->lock, flags);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
264
err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
272
divider->base + WZRD_DR_INIT_VERSAL_OFFSET);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
275
err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
279
spin_unlock_irqrestore(divider->lock, flags);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
286
struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
287
void __iomem *div_addr = divider->base + divider->offset;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
292
spin_lock_irqsave(divider->lock, flags);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
304
err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
312
divider->base + WZRD_DR_INIT_REG_OFFSET);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
314
divider->base + WZRD_DR_INIT_REG_OFFSET);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
317
err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
321
spin_unlock_irqrestore(divider->lock, flags);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
344
struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
372
divider->m = m;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
373
divider->d = d;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
374
divider->o = o;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
386
struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
412
divider->m = m >> 3;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
413
divider->m_frac = (m - (divider->m << 3)) * 125;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
414
divider->d = d;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
415
divider->o = o >> 3;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
416
divider->o_frac = (o - (divider->o << 3)) * 125;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
423
static int clk_wzrd_reconfig(struct clk_wzrd_divider *divider, void __iomem *div_addr)
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
429
err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
438
return readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
447
struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
455
writel(0, divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_4));
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
457
m = divider->m;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
460
regval1 = readl(divider->base + WZRD_CLK_CFG_REG(1,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
468
writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
471
writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
474
value2 = divider->d;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
478
writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
481
writel(regval1, divider->base + WZRD_CLK_CFG_REG(1, WZRD_DIVCLK));
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
483
value = divider->o;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
485
regval1 = readl(divider->base + WZRD_CLK_CFG_REG(1,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
499
writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
502
writel(regval, divider->base + WZRD_CLK_CFG_REG(1,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
504
div_addr = divider->base + WZRD_DR_INIT_VERSAL_OFFSET;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
506
return clk_wzrd_reconfig(divider, div_addr);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
512
struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
521
reg = FIELD_PREP(WZRD_CLKOUT_DIVIDE_MASK, divider->o) |
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
522
FIELD_PREP(WZRD_CLKOUT0_FRAC_MASK, divider->o_frac);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
524
writel(reg, divider->base + WZRD_CLK_CFG_REG(0, 2));
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
525
reg = FIELD_PREP(WZRD_CLKFBOUT_MULT_MASK, divider->m) |
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
526
FIELD_PREP(WZRD_CLKFBOUT_MULT_FRAC_MASK, divider->m_frac) |
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
527
FIELD_PREP(WZRD_DIVCLK_DIVIDE_MASK, divider->d);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
528
writel(reg, divider->base + WZRD_CLK_CFG_REG(0, 0));
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
529
writel(0, divider->base + WZRD_CLK_CFG_REG(0, 3));
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
530
div_addr = divider->base + WZRD_DR_INIT_REG_OFFSET;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
531
return clk_wzrd_reconfig(divider, div_addr);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
537
struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
541
spin_lock_irqsave(divider->lock, flags);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
545
spin_unlock_irqrestore(divider->lock, flags);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
553
struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
557
spin_lock_irqsave(divider->lock, flags);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
561
spin_unlock_irqrestore(divider->lock, flags);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
569
struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
573
reg = readl(divider->base + WZRD_CLK_CFG_REG(0, 0));
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
577
reg = readl(divider->base + WZRD_CLK_CFG_REG(0, 2));
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
588
struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
592
edge = !!(readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_1)) &
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
595
reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_2));
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
603
regl = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_4)) &
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
606
regl = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_3))
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
615
reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKOUT0_1));
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
620
reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKOUT0_2));
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
635
edged = !!(readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_DESKEW_2)) &
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
637
reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_DIVCLK));
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
647
return divider_recalc_rate(hw, parent_rate, div, divider->table,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
648
divider->flags, divider->width);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
654
struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
662
m = divider->m;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
663
d = divider->d;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
664
o = divider->o;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
666
req->rate = div_u64(req->best_parent_rate * (m * 1000 + divider->m_frac),
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
667
d * (o * 1000 + divider->o_frac));
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
674
struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
683
m = divider->m;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
684
d = divider->d;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
685
o = divider->o;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
689
divider->table,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
690
divider->flags, divider->width);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
729
struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
730
void __iomem *div_addr = divider->base + divider->offset;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
733
div = val & div_mask(divider->width);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
745
struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
746
void __iomem *div_addr = divider->base + divider->offset;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
763
err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
771
divider->base + WZRD_DR_INIT_REG_OFFSET);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
773
divider->base + WZRD_DR_INIT_REG_OFFSET);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
776
return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
drivers/clk/xilinx/xlnx_vcu.c
450
struct clk_hw *divider = NULL;
drivers/clk/xilinx/xlnx_vcu.c
478
divider = clk_hw_register_divider_parent_hw(dev, name_div, mux,
drivers/clk/xilinx/xlnx_vcu.c
482
if (IS_ERR(divider)) {
drivers/clk/xilinx/xlnx_vcu.c
483
err = PTR_ERR(divider);
drivers/clk/xilinx/xlnx_vcu.c
487
gate = clk_hw_register_gate_parent_hw(dev, name, divider,
drivers/clk/xilinx/xlnx_vcu.c
498
clk_hw_unregister_divider(divider);
drivers/clk/xilinx/xlnx_vcu.c
508
struct clk_hw *divider;
drivers/clk/xilinx/xlnx_vcu.c
514
divider = clk_hw_get_parent(gate);
drivers/clk/xilinx/xlnx_vcu.c
516
if (!divider)
drivers/clk/xilinx/xlnx_vcu.c
519
mux = clk_hw_get_parent(divider);
drivers/clk/xilinx/xlnx_vcu.c
521
if (!divider)
drivers/clk/xilinx/xlnx_vcu.c
524
clk_hw_unregister_divider(divider);
drivers/clk/zynqmp/divider.c
100
if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
drivers/clk/zynqmp/divider.c
104
WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
drivers/clk/zynqmp/divider.c
123
struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
drivers/clk/zynqmp/divider.c
125
u32 clk_id = divider->clk_id;
drivers/clk/zynqmp/divider.c
126
u32 div_type = divider->div_type;
drivers/clk/zynqmp/divider.c
132
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
drivers/clk/zynqmp/divider.c
143
if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
drivers/clk/zynqmp/divider.c
151
width = fls(divider->max_div);
drivers/clk/zynqmp/divider.c
153
ret = divider_determine_rate(hw, req, NULL, width, divider->flags);
drivers/clk/zynqmp/divider.c
157
if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) &&
drivers/clk/zynqmp/divider.c
175
struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
drivers/clk/zynqmp/divider.c
177
u32 clk_id = divider->clk_id;
drivers/clk/zynqmp/divider.c
178
u32 div_type = divider->div_type;
drivers/clk/zynqmp/divider.c
182
value = zynqmp_divider_get_val(parent_rate, rate, divider->flags);
drivers/clk/zynqmp/divider.c
191
if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
drivers/clk/zynqmp/divider.c
82
struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
drivers/clk/zynqmp/divider.c
84
u32 clk_id = divider->clk_id;
drivers/clk/zynqmp/divider.c
85
u32 div_type = divider->div_type;
drivers/clocksource/arm_arch_timer.c
714
static void arch_timer_evtstrm_enable(unsigned int divider)
drivers/clocksource/arm_arch_timer.c
720
if (cpus_have_final_cap(ARM64_HAS_ECV) && divider > 15) {
drivers/clocksource/arm_arch_timer.c
722
divider -= 8;
drivers/clocksource/arm_arch_timer.c
726
divider = min(divider, 15U);
drivers/clocksource/arm_arch_timer.c
729
cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
drivers/comedi/drivers/dt2811.c
325
unsigned long long divider = div * mult;
drivers/comedi/drivers/dt2811.c
335
ns = divider * DT2811_OSC_BASE;
drivers/comedi/drivers/dt282x.c
366
unsigned int prescale, base, divider;
drivers/comedi/drivers/dt282x.c
375
divider = DIV_ROUND_CLOSEST(*ns, base);
drivers/comedi/drivers/dt282x.c
378
divider = (*ns) / base;
drivers/comedi/drivers/dt282x.c
381
divider = DIV_ROUND_UP(*ns, base);
drivers/comedi/drivers/dt282x.c
384
if (divider <= DT2821_DIVIDER_MAX)
drivers/comedi/drivers/dt282x.c
387
if (divider > DT2821_DIVIDER_MAX) {
drivers/comedi/drivers/dt282x.c
389
divider = DT2821_DIVIDER_MAX;
drivers/comedi/drivers/dt282x.c
392
*ns = divider * base;
drivers/comedi/drivers/dt282x.c
394
DT2821_TMRCTR_DIVIDER(divider);
drivers/comedi/drivers/dt3000.c
344
unsigned int divider, base, prescale;
drivers/comedi/drivers/dt3000.c
354
divider = DIV_ROUND_CLOSEST(*nanosec, base);
drivers/comedi/drivers/dt3000.c
357
divider = (*nanosec) / base;
drivers/comedi/drivers/dt3000.c
360
divider = DIV_ROUND_UP(*nanosec, base);
drivers/comedi/drivers/dt3000.c
363
if (divider < 65536) {
drivers/comedi/drivers/dt3000.c
364
*nanosec = divider * base;
drivers/comedi/drivers/dt3000.c
365
return (prescale << 16) | (divider);
drivers/comedi/drivers/dt3000.c
371
divider = 65535;
drivers/comedi/drivers/dt3000.c
372
*nanosec = divider * base;
drivers/comedi/drivers/dt3000.c
373
return (prescale << 16) | (divider);
drivers/comedi/drivers/dt3000.c
457
unsigned int divider;
drivers/comedi/drivers/dt3000.c
471
divider = dt3k_ns_to_timer(50, &cmd->convert_arg, cmd->flags);
drivers/comedi/drivers/dt3000.c
472
writew((divider >> 16), dev->mmio + DPR_PARAMS(1));
drivers/comedi/drivers/dt3000.c
473
writew((divider & 0xffff), dev->mmio + DPR_PARAMS(2));
drivers/comedi/drivers/ni_mio_common.c
1945
int divider;
drivers/comedi/drivers/ni_mio_common.c
1950
divider = DIV_ROUND_CLOSEST(nanosec, devpriv->clock_ns);
drivers/comedi/drivers/ni_mio_common.c
1953
divider = (nanosec) / devpriv->clock_ns;
drivers/comedi/drivers/ni_mio_common.c
1956
divider = DIV_ROUND_UP(nanosec, devpriv->clock_ns);
drivers/comedi/drivers/ni_mio_common.c
1959
return divider - 1;
drivers/comedi/drivers/ni_pcidio.c
506
int divider, base;
drivers/comedi/drivers/ni_pcidio.c
513
divider = DIV_ROUND_CLOSEST(*nanosec, base);
drivers/comedi/drivers/ni_pcidio.c
516
divider = (*nanosec) / base;
drivers/comedi/drivers/ni_pcidio.c
519
divider = DIV_ROUND_UP(*nanosec, base);
drivers/comedi/drivers/ni_pcidio.c
523
*nanosec = base * divider;
drivers/comedi/drivers/ni_pcidio.c
524
return divider;
drivers/comedi/drivers/rtd520.c
376
int divider;
drivers/comedi/drivers/rtd520.c
381
divider = DIV_ROUND_CLOSEST(*nanosec, base);
drivers/comedi/drivers/rtd520.c
384
divider = (*nanosec) / base;
drivers/comedi/drivers/rtd520.c
387
divider = DIV_ROUND_UP(*nanosec, base);
drivers/comedi/drivers/rtd520.c
390
if (divider < 2)
drivers/comedi/drivers/rtd520.c
391
divider = 2; /* min is divide by 2 */
drivers/comedi/drivers/rtd520.c
398
*nanosec = base * divider;
drivers/comedi/drivers/rtd520.c
399
return divider - 1; /* countdown is divisor+1 */
drivers/comedi/drivers/s626.c
1628
int divider, base;
drivers/comedi/drivers/s626.c
1635
divider = DIV_ROUND_CLOSEST(*nanosec, base);
drivers/comedi/drivers/s626.c
1638
divider = (*nanosec) / base;
drivers/comedi/drivers/s626.c
1641
divider = DIV_ROUND_UP(*nanosec, base);
drivers/comedi/drivers/s626.c
1645
*nanosec = base * divider;
drivers/comedi/drivers/s626.c
1646
return divider - 1;
drivers/cpufreq/armada-37xx-cpufreq.c
100
u8 divider[LOAD_LEVEL_NR];
drivers/cpufreq/armada-37xx-cpufreq.c
105
{.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} },
drivers/cpufreq/armada-37xx-cpufreq.c
106
{.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
drivers/cpufreq/armada-37xx-cpufreq.c
107
{.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} },
drivers/cpufreq/armada-37xx-cpufreq.c
108
{.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} },
drivers/cpufreq/armada-37xx-cpufreq.c
129
struct regmap *clk_base, u8 *divider)
drivers/cpufreq/armada-37xx-cpufreq.c
165
val |= divider[load_lvl] << ARMADA_37XX_NB_TBG_DIV_OFF;
drivers/cpufreq/armada-37xx-cpufreq.c
481
armada37xx_cpufreq_dvfs_setup(nb_pm_base, nb_clk_base, dvfs->divider);
drivers/cpufreq/armada-37xx-cpufreq.c
487
freq = base_frequency / dvfs->divider[load_lvl];
drivers/cpufreq/armada-37xx-cpufreq.c
518
freq = base_frequency / dvfs->divider[load_lvl];
drivers/cpufreq/armada-37xx-cpufreq.c
541
freq = dvfs->cpu_freq_max / dvfs->divider[load_lvl];
drivers/firmware/xilinx/zynqmp.c
752
int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
drivers/firmware/xilinx/zynqmp.c
754
return zynqmp_pm_invoke_fn(PM_CLOCK_SETDIVIDER, NULL, 2, clock_id, divider);
drivers/firmware/xilinx/zynqmp.c
768
int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
drivers/firmware/xilinx/zynqmp.c
774
*divider = ret_payload[1];
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
73
uint32_t dentist_get_did_from_divider(int divider)
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
78
if (divider < DENTIST_DIVIDER_RANGE_2_START) {
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
79
if (divider < DENTIST_DIVIDER_RANGE_1_START)
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
83
+ (divider - DENTIST_DIVIDER_RANGE_1_START)
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
85
} else if (divider < DENTIST_DIVIDER_RANGE_3_START) {
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
87
+ (divider - DENTIST_DIVIDER_RANGE_2_START)
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
89
} else if (divider < DENTIST_DIVIDER_RANGE_4_START) {
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
91
+ (divider - DENTIST_DIVIDER_RANGE_3_START)
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
95
+ (divider - DENTIST_DIVIDER_RANGE_4_START)
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
46
uint32_t dentist_get_did_from_divider(int divider);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
227
unsigned int divider;
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
234
divider = (unsigned int)((int)DFS_DIVIDER_RANGE_SCALE_FACTOR * (vco_freq_khz / clock_khz));
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
237
if (divider < DFS_DIVIDER_RANGE_2_START) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
238
if (divider < DFS_DIVIDER_RANGE_1_START)
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
241
*divider_id = DFS_BASE_DID_1 + ((divider - DFS_DIVIDER_RANGE_1_START) / DFS_DIVIDER_RANGE_1_STEP);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
242
} else if (divider < DFS_DIVIDER_RANGE_3_START) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
243
*divider_id = DFS_BASE_DID_2 + ((divider - DFS_DIVIDER_RANGE_2_START) / DFS_DIVIDER_RANGE_2_STEP);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
244
} else if (divider < DFS_DIVIDER_RANGE_4_START) {
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
245
*divider_id = DFS_BASE_DID_3 + ((divider - DFS_DIVIDER_RANGE_3_START) / DFS_DIVIDER_RANGE_3_STEP);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
247
*divider_id = DFS_BASE_DID_4 + ((divider - DFS_DIVIDER_RANGE_4_START) / DFS_DIVIDER_RANGE_4_STEP);
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
252
*rounded_khz = vco_freq_khz * DFS_DIVIDER_RANGE_SCALE_FACTOR / divider;
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
270
uint32_t divider; /* (actually HW range is min/divider; divider !=0) */
drivers/gpu/drm/exynos/exynos_drm_scaler.c
342
unsigned int timer, unsigned int divider)
drivers/gpu/drm/exynos/exynos_drm_scaler.c
348
val |= SCALER_TIMEOUT_CTRL_SET_TIMER_DIV(divider);
drivers/gpu/drm/i915/display/intel_cdclk.c
1767
u32 divider;
drivers/gpu/drm/i915/display/intel_cdclk.c
1784
divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
drivers/gpu/drm/i915/display/intel_cdclk.c
1786
switch (divider) {
drivers/gpu/drm/i915/display/intel_cdclk.c
1800
MISSING_CASE(divider);
drivers/gpu/drm/i915/display/intel_cdclk.c
3802
int divider, fraction;
drivers/gpu/drm/i915/display/intel_cdclk.c
3807
divider = 24000;
drivers/gpu/drm/i915/display/intel_cdclk.c
3811
divider = 19000;
drivers/gpu/drm/i915/display/intel_cdclk.c
3815
rawclk = CNP_RAWCLK_DIV(divider / 1000);
drivers/gpu/drm/i915/display/intel_cdclk.c
3826
return divider + fraction;
drivers/gpu/drm/i915/display/intel_cdclk.c
711
u32 divider;
drivers/gpu/drm/i915/display/intel_cdclk.c
713
divider = DIV_ROUND_CLOSEST(vlv_clock_get_hpll_vco(display->drm) << 1,
drivers/gpu/drm/i915/display/intel_cdclk.c
719
val |= divider;
drivers/gpu/drm/i915/display/intel_cdclk.c
723
(val & CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1529
unsigned int divider)
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1543
ctx->p = divider;
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
1551
ctx->p = divider;
drivers/gpu/drm/i915/display/intel_lvds.c
175
pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
drivers/gpu/drm/i915/display/intel_lvds.c
207
pps->delays.backlight_off, pps->divider,
drivers/gpu/drm/i915/display/intel_lvds.c
233
REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |
drivers/gpu/drm/i915/display/intel_lvds.c
63
int divider;
drivers/gpu/drm/i915/display/vlv_clock.c
43
int divider;
drivers/gpu/drm/i915/display/vlv_clock.c
49
divider = val & CCK_FREQUENCY_VALUES;
drivers/gpu/drm/i915/display/vlv_clock.c
52
(divider << CCK_FREQUENCY_STATUS_SHIFT),
drivers/gpu/drm/i915/display/vlv_clock.c
55
return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
drivers/gpu/drm/i915/display/vlv_dsi.c
1202
static u16 txclkesc(u32 divider, unsigned int us)
drivers/gpu/drm/i915/display/vlv_dsi.c
1204
switch (divider) {
drivers/gpu/drm/kmb/kmb_dsi.c
885
.divider = 1,
drivers/gpu/drm/kmb/kmb_dsi.c
94
u32 divider;
drivers/gpu/drm/kmb/kmb_dsi.c
961
t_freq = target_freq_mhz * vco_p.divider;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
119
u64 divider;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
126
divider = fref * 2;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
129
dec_multiple = div_u64(pll_freq * multiplier, divider);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
131
u64 divider;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
138
divider = fref * 2;
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
141
dec_multiple = div_u64(pll_freq * multiplier, divider);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
93
u32 divider;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
96
divider = pll->m * clk->pl_to_div(pll->pl);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
98
return rate / divider / 2;
drivers/gpu/drm/radeon/r600_dpm.c
477
u32 index, u32 divider)
drivers/gpu/drm/radeon/r600_dpm.c
480
STEP_0_SPLL_POST_DIV(divider), ~STEP_0_SPLL_POST_DIV_MASK);
drivers/gpu/drm/radeon/r600_dpm.c
484
u32 index, u32 divider)
drivers/gpu/drm/radeon/r600_dpm.c
487
STEP_0_SPLL_REF_DIV(divider), ~STEP_0_SPLL_REF_DIV_MASK);
drivers/gpu/drm/radeon/r600_dpm.c
491
u32 index, u32 divider)
drivers/gpu/drm/radeon/r600_dpm.c
494
STEP_0_SPLL_FB_DIV(divider), ~STEP_0_SPLL_FB_DIV_MASK);
drivers/gpu/drm/radeon/r600_dpm.h
180
u32 index, u32 divider);
drivers/gpu/drm/radeon/r600_dpm.h
182
u32 index, u32 divider);
drivers/gpu/drm/radeon/r600_dpm.h
184
u32 index, u32 divider);
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
744
int divider;
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
812
for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
813
if (post_div->divider == post_divider)
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
817
if (!post_div->divider)
drivers/gpu/drm/radeon/rv6xx_dpm.c
380
u32 index, u32 divider)
drivers/gpu/drm/radeon/rv6xx_dpm.c
383
LEVEL0_MPLL_POST_DIV(divider), ~LEVEL0_MPLL_POST_DIV_MASK);
drivers/gpu/drm/radeon/rv6xx_dpm.c
387
u32 index, u32 divider)
drivers/gpu/drm/radeon/rv6xx_dpm.c
389
WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider),
drivers/gpu/drm/radeon/rv6xx_dpm.c
394
u32 index, u32 divider)
drivers/gpu/drm/radeon/rv6xx_dpm.c
397
LEVEL0_MPLL_REF_DIV(divider), ~LEVEL0_MPLL_REF_DIV_MASK);
drivers/gpu/drm/radeon/sumo_dpm.c
472
u32 index, u32 divider)
drivers/gpu/drm/radeon/sumo_dpm.c
479
SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK);
drivers/gpu/drm/radeon/sumo_dpm.c
482
SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK);
drivers/gpu/drm/radeon/sumo_dpm.c
485
SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK);
drivers/gpu/drm/radeon/sumo_dpm.c
488
SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK);
drivers/gpu/drm/radeon/sumo_dpm.c
492
u32 index, u32 divider)
drivers/gpu/drm/radeon/sumo_dpm.c
500
dpm_ctrl |= (divider << (index * 3));
drivers/gpu/drm/radeon/sumo_dpm.c
506
u32 index, u32 divider)
drivers/gpu/drm/radeon/sumo_dpm.c
514
dpm_ctrl |= (divider << (index * 3));
drivers/gpu/drm/radeon/trinity_dpm.c
1783
u32 divider;
drivers/gpu/drm/radeon/trinity_dpm.c
1786
divider = did * 25;
drivers/gpu/drm/radeon/trinity_dpm.c
1788
divider = (did - 64) * 50 + 1600;
drivers/gpu/drm/radeon/trinity_dpm.c
1790
divider = (did - 96) * 100 + 3200;
drivers/gpu/drm/radeon/trinity_dpm.c
1792
divider = 128 * 100;
drivers/gpu/drm/radeon/trinity_dpm.c
1796
return ((pi->sys_info.dentist_vco_freq * 100) + (divider - 1)) / divider;
drivers/gpu/drm/radeon/trinity_dpm.c
565
u32 index, u32 divider)
drivers/gpu/drm/radeon/trinity_dpm.c
572
value |= DS_DIV(divider);
drivers/gpu/drm/radeon/trinity_dpm.c
577
u32 index, u32 divider)
drivers/gpu/drm/radeon/trinity_dpm.c
584
value |= DS_SH_DIV(divider);
drivers/gpu/drm/vc4/vc4_dsi.c
1131
VC4_SET_FIELD(dsi->divider,
drivers/gpu/drm/vc4/vc4_dsi.c
1358
dsi->divider = 24 / dsi->lanes;
drivers/gpu/drm/vc4/vc4_dsi.c
1362
dsi->divider = 24 / dsi->lanes;
drivers/gpu/drm/vc4/vc4_dsi.c
1366
dsi->divider = 18 / dsi->lanes;
drivers/gpu/drm/vc4/vc4_dsi.c
1370
dsi->divider = 16 / dsi->lanes;
drivers/gpu/drm/vc4/vc4_dsi.c
574
u32 divider;
drivers/gpu/drm/vc4/vc4_dsi.c
846
unsigned long pll_clock = pixel_clock_hz * dsi->divider;
drivers/gpu/drm/vc4/vc4_dsi.c
847
int divider;
drivers/gpu/drm/vc4/vc4_dsi.c
852
for (divider = 1; divider < 255; divider++) {
drivers/gpu/drm/vc4/vc4_dsi.c
853
if (parent_rate / (divider + 1) < pll_clock)
drivers/gpu/drm/vc4/vc4_dsi.c
860
pll_clock = parent_rate / divider;
drivers/gpu/drm/vc4/vc4_dsi.c
861
pixel_clock_hz = pll_clock / dsi->divider;
drivers/gpu/drm/vc4/vc4_dsi.c
921
phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
drivers/hwmon/bt1-pvt.h
233
long divider;
drivers/hwmon/ltc4282.c
1322
const char *divider;
drivers/hwmon/ltc4282.c
1436
÷r);
drivers/hwmon/ltc4282.c
1439
ARRAY_SIZE(ltc4282_dividers), divider);
drivers/hwmon/ltc4282.c
1443
divider);
drivers/hwmon/ltc4282.c
1451
÷r);
drivers/hwmon/ltc4282.c
1454
ARRAY_SIZE(ltc4282_dividers), divider);
drivers/hwmon/ltc4282.c
1458
divider);
drivers/hwmon/mlxreg-fan.c
115
int divider;
drivers/hwmon/mlxreg-fan.c
168
*val = MLXREG_FAN_GET_RPM(regval, fan->divider,
drivers/hwmon/mlxreg-fan.c
454
fan->divider = regval * MLXREG_FAN_TACHO_DIV_MIN;
drivers/hwmon/mlxreg-fan.c
468
fan->divider = MLXREG_FAN_TACHO_DIV_DEF;
drivers/hwmon/mlxreg-fan.c
531
fan->divider = data->bit;
drivers/i2c/busses/i2c-bcm2835.c
100
if (divider & 1)
drivers/i2c/busses/i2c-bcm2835.c
101
divider++;
drivers/i2c/busses/i2c-bcm2835.c
102
if ((divider < BCM2835_I2C_CDIV_MIN) ||
drivers/i2c/busses/i2c-bcm2835.c
103
(divider > BCM2835_I2C_CDIV_MAX))
drivers/i2c/busses/i2c-bcm2835.c
106
return divider;
drivers/i2c/busses/i2c-bcm2835.c
114
u32 divider = clk_bcm2835_i2c_calc_divider(rate, parent_rate);
drivers/i2c/busses/i2c-bcm2835.c
116
if (divider == -EINVAL)
drivers/i2c/busses/i2c-bcm2835.c
119
bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DIV, divider);
drivers/i2c/busses/i2c-bcm2835.c
126
fedl = max(divider / 16, 1u);
drivers/i2c/busses/i2c-bcm2835.c
132
redl = max(divider / 4, 1u);
drivers/i2c/busses/i2c-bcm2835.c
143
u32 divider = clk_bcm2835_i2c_calc_divider(req->rate, req->best_parent_rate);
drivers/i2c/busses/i2c-bcm2835.c
145
req->rate = DIV_ROUND_UP(req->best_parent_rate, divider);
drivers/i2c/busses/i2c-bcm2835.c
154
u32 divider = bcm2835_i2c_readl(div->i2c_dev, BCM2835_I2C_DIV);
drivers/i2c/busses/i2c-bcm2835.c
156
return DIV_ROUND_UP(parent_rate, divider);
drivers/i2c/busses/i2c-bcm2835.c
93
u32 divider = DIV_ROUND_UP(parent_rate, rate);
drivers/i2c/busses/i2c-mpc.c
104
u16 divider;
drivers/i2c/busses/i2c-mpc.c
243
u32 divider;
drivers/i2c/busses/i2c-mpc.c
253
divider = mpc5xxx_fwnode_get_bus_frequency(fwnode) / clock;
drivers/i2c/busses/i2c-mpc.c
264
if (div->divider >= divider)
drivers/i2c/busses/i2c-mpc.c
268
*real_clk = mpc5xxx_fwnode_get_bus_frequency(fwnode) / div->divider;
drivers/i2c/busses/i2c-mpc.c
427
u32 divider;
drivers/i2c/busses/i2c-mpc.c
436
divider = fsl_get_sys_freq() / clock / prescaler;
drivers/i2c/busses/i2c-mpc.c
439
fsl_get_sys_freq(), clock, divider);
drivers/i2c/busses/i2c-mpc.c
447
if (div->divider >= divider)
drivers/i2c/busses/i2c-mpc.c
451
*real_clk = fsl_get_sys_freq() / prescaler / div->divider;
drivers/i2c/busses/i2c-mxs.c
702
uint32_t divider;
drivers/i2c/busses/i2c-mxs.c
707
divider = DIV_ROUND_UP(clk, speed);
drivers/i2c/busses/i2c-mxs.c
709
if (divider < 25) {
drivers/i2c/busses/i2c-mxs.c
714
divider = 25;
drivers/i2c/busses/i2c-mxs.c
718
clk / divider / 1000, clk / divider % 1000);
drivers/i2c/busses/i2c-mxs.c
719
} else if (divider > 1897) {
drivers/i2c/busses/i2c-mxs.c
724
divider = 1897;
drivers/i2c/busses/i2c-mxs.c
728
clk / divider / 1000, clk / divider % 1000);
drivers/i2c/busses/i2c-mxs.c
747
low_count = DIV_ROUND_CLOSEST(divider * 13, (13 + 6));
drivers/i2c/busses/i2c-mxs.c
748
high_count = DIV_ROUND_CLOSEST(divider * 6, (13 + 6));
drivers/i2c/busses/i2c-mxs.c
753
low_count = DIV_ROUND_CLOSEST(divider * 47, (47 + 40));
drivers/i2c/busses/i2c-mxs.c
754
high_count = DIV_ROUND_CLOSEST(divider * 40, (47 + 40));
drivers/i2c/busses/i2c-mxs.c
763
speed, clk / divider, divider, low_count, high_count,
drivers/iio/adc/cpcap-adc.c
178
unsigned short divider;
drivers/iio/adc/cpcap-adc.c
198
int divider;
drivers/iio/adc/cpcap-adc.c
679
if (phase_tbl[index].divider == 0)
drivers/iio/adc/cpcap-adc.c
681
req->result /= phase_tbl[index].divider;
drivers/iio/adc/cpcap-adc.c
691
if (phase_tbl[index].divider == 0)
drivers/iio/adc/cpcap-adc.c
693
req->result /= phase_tbl[index].divider;
drivers/iio/adc/cpcap-adc.c
769
if (conv_tbl[index].divider == 0)
drivers/iio/adc/cpcap-adc.c
771
req->result /= conv_tbl[index].divider;
drivers/iio/adc/stm32-dfsdm-core.c
228
unsigned long clk_freq, divider;
drivers/iio/adc/stm32-dfsdm-core.c
270
divider = div_u64_rem(clk_freq, spi_freq, &rem);
drivers/iio/adc/stm32-dfsdm-core.c
273
divider++;
drivers/iio/adc/stm32-dfsdm-core.c
276
if (divider < 2 || divider > 256) {
drivers/iio/adc/stm32-dfsdm-core.c
282
priv->spi_clk_out_div = divider - 1;
drivers/iio/chemical/sgp40.c
109
u32 factorial, divider, xmax;
drivers/iio/chemical/sgp40.c
125
divider = 0;
drivers/iio/chemical/sgp40.c
130
y += (xp >> divider) / factorial;
drivers/iio/chemical/sgp40.c
131
divider += power;
drivers/iio/chemical/sgp40.c
135
divider -= power;
drivers/iio/frequency/admv4420.c
216
return (tmp / (st->ref_block.divider * divide_by_2));
drivers/iio/frequency/admv4420.c
228
for (st->ref_block.divider = 1; st->ref_block.divider < MAX_R_DIVIDER;
drivers/iio/frequency/admv4420.c
229
st->ref_block.divider++) {
drivers/iio/frequency/admv4420.c
314
FIELD_GET(0xFF, st->ref_block.divider));
drivers/iio/frequency/admv4420.c
319
FIELD_GET(0xFF00, st->ref_block.divider));
drivers/iio/frequency/admv4420.c
97
u32 divider;
drivers/iio/imu/inv_mpu6050/inv_mpu_aux.c
52
d = st->chip_config.divider;
drivers/iio/imu/inv_mpu6050/inv_mpu_aux.c
75
regmap_write(st->map, st->reg->sample_rate_div, st->chip_config.divider);
drivers/iio/imu/inv_mpu6050/inv_mpu_core.c
113
.divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(50),
drivers/iio/imu/inv_mpu6050/inv_mpu_core.c
130
.divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(50),
drivers/iio/imu/inv_mpu6050/inv_mpu_core.c
1319
if (d == st->chip_config.divider) {
drivers/iio/imu/inv_mpu6050/inv_mpu_core.c
1338
st->chip_config.divider = d;
drivers/iio/imu/inv_mpu6050/inv_mpu_core.c
1376
fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
drivers/iio/imu/inv_mpu6050/inv_mpu_core.c
594
d = st->chip_config.divider;
drivers/iio/imu/inv_mpu6050/inv_mpu_core.c
612
NSEC_PER_SEC / INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
drivers/iio/imu/inv_mpu6050/inv_mpu_core.c
660
freq_hz = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h
133
u8 divider;
drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h
407
((st)->chip_config.divider + 1)
drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h
411
#define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider) \
drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h
412
(INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1))
drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c
103
fifo_period = NSEC_PER_SEC / INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
drivers/media/dvb-frontends/stv6110.c
226
u32 nbsteps, divider, psd2, freq;
drivers/media/dvb-frontends/stv6110.c
231
divider = (priv->regs[RSTV6110_TUNING2] & 0x0f) << 8;
drivers/media/dvb-frontends/stv6110.c
232
divider += priv->regs[RSTV6110_TUNING1];
drivers/media/dvb-frontends/stv6110.c
239
freq = divider * (priv->mclk / 1000);
drivers/media/dvb-frontends/stv6110.c
252
u32 divider, ref, p, presc, i, result_freq, vco_freq;
drivers/media/dvb-frontends/stv6110.c
300
divider = (((frequency * 1000) + (ref >> 1)) / ref);
drivers/media/dvb-frontends/stv6110.c
308
priv->regs[RSTV6110_TUNING2] |= (((divider) >> 8) & 0x0f);
drivers/media/dvb-frontends/stv6110.c
311
priv->regs[RSTV6110_TUNING1] = (divider & 0xff);
drivers/media/dvb-frontends/stv6110.c
329
vco_freq = divider * ((priv->mclk / 1000) / ((1 << (r_div_opt + 1))));
drivers/media/dvb-frontends/stv6110x.c
111
u32 rDiv, divider;
drivers/media/dvb-frontends/stv6110x.c
144
divider = (frequency * R_DIV(rDivOpt) * pVal) / REFCLOCK_kHz;
drivers/media/dvb-frontends/stv6110x.c
145
divider = (divider + 5) / 10;
drivers/media/dvb-frontends/stv6110x.c
148
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_N_DIV_11_8, MSB(divider));
drivers/media/dvb-frontends/stv6110x.c
149
STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG0], TNG0_N_DIV_7_0, LSB(divider));
drivers/media/i2c/cx25840/cx25840-ir.c
145
static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
drivers/media/i2c/cx25840/cx25840-ir.c
147
return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16);
drivers/media/i2c/cx25840/cx25840-ir.c
150
static inline unsigned int clock_divider_to_freq(unsigned int divider,
drivers/media/i2c/cx25840/cx25840-ir.c
154
(divider + 1) * rollovers);
drivers/media/i2c/cx25840/cx25840-ir.c
195
static u32 clock_divider_to_resolution(u16 divider)
drivers/media/i2c/cx25840/cx25840-ir.c
202
return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
drivers/media/i2c/cx25840/cx25840-ir.c
206
static u64 pulse_width_count_to_ns(u16 count, u16 divider)
drivers/media/i2c/cx25840/cx25840-ir.c
215
n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
drivers/media/i2c/cx25840/cx25840-ir.c
224
static u16 ns_to_pulse_width_count(u32 ns, u16 divider)
drivers/media/i2c/cx25840/cx25840-ir.c
235
d = (1 << 2) * ((u32) divider + 1) * 1000; /* millicycles/count */
drivers/media/i2c/cx25840/cx25840-ir.c
248
static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
drivers/media/i2c/cx25840/cx25840-ir.c
257
n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */
drivers/media/i2c/cx25840/cx25840-ir.c
393
u16 *divider)
drivers/media/i2c/cx25840/cx25840-ir.c
395
*divider = carrier_freq_to_clock_divider(freq);
drivers/media/i2c/cx25840/cx25840-ir.c
396
cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider);
drivers/media/i2c/cx25840/cx25840-ir.c
397
return clock_divider_to_carrier_freq(*divider);
drivers/media/i2c/cx25840/cx25840-ir.c
402
u16 *divider)
drivers/media/i2c/cx25840/cx25840-ir.c
404
*divider = carrier_freq_to_clock_divider(freq);
drivers/media/i2c/cx25840/cx25840-ir.c
405
cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider);
drivers/media/i2c/cx25840/cx25840-ir.c
406
return clock_divider_to_carrier_freq(*divider);
drivers/media/i2c/cx25840/cx25840-ir.c
410
u16 *divider)
drivers/media/i2c/cx25840/cx25840-ir.c
417
*divider = pulse_clocks_to_clock_divider(pulse_clocks);
drivers/media/i2c/cx25840/cx25840-ir.c
418
cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider);
drivers/media/i2c/cx25840/cx25840-ir.c
419
return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
drivers/media/i2c/cx25840/cx25840-ir.c
423
u16 *divider)
drivers/media/i2c/cx25840/cx25840-ir.c
430
*divider = pulse_clocks_to_clock_divider(pulse_clocks);
drivers/media/i2c/cx25840/cx25840-ir.c
431
cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider);
drivers/media/i2c/cx25840/cx25840-ir.c
432
return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
drivers/media/i2c/cx25840/cx25840-ir.c
633
u16 divider;
drivers/media/i2c/cx25840/cx25840-ir.c
642
divider = (u16) atomic_read(&ir_state->rxclk_divider);
drivers/media/i2c/cx25840/cx25840-ir.c
671
(u16)(p->hw_fifo_data & FIFO_RXTX), divider) / 1000;
drivers/media/i2c/mt9t112.c
409
priv->info->divider.m, priv->info->divider.n,
drivers/media/i2c/mt9t112.c
410
priv->info->divider.p1, priv->info->divider.p2,
drivers/media/i2c/mt9t112.c
411
priv->info->divider.p3, priv->info->divider.p4,
drivers/media/i2c/mt9t112.c
412
priv->info->divider.p5, priv->info->divider.p6,
drivers/media/i2c/mt9t112.c
413
priv->info->divider.p7);
drivers/media/i2c/ov4689.c
148
u32 divider;
drivers/media/i2c/ov4689.c
293
.divider = 1,
drivers/media/i2c/ov4689.c
301
.divider = 2,
drivers/media/i2c/ov4689.c
309
.divider = 4,
drivers/media/i2c/ov4689.c
317
.divider = 8,
drivers/media/i2c/ov4689.c
627
*result = clamp(range->offset + (logical_gain) / range->divider,
drivers/media/pci/cx23885/cx23888-ir.c
184
static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
drivers/media/pci/cx23885/cx23888-ir.c
186
return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16);
drivers/media/pci/cx23885/cx23888-ir.c
189
static inline unsigned int clock_divider_to_freq(unsigned int divider,
drivers/media/pci/cx23885/cx23888-ir.c
193
(divider + 1) * rollovers);
drivers/media/pci/cx23885/cx23888-ir.c
234
static u32 clock_divider_to_resolution(u16 divider)
drivers/media/pci/cx23885/cx23888-ir.c
241
return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
drivers/media/pci/cx23885/cx23888-ir.c
245
static u64 pulse_width_count_to_ns(u16 count, u16 divider)
drivers/media/pci/cx23885/cx23888-ir.c
254
n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
drivers/media/pci/cx23885/cx23888-ir.c
261
static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
drivers/media/pci/cx23885/cx23888-ir.c
270
n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */
drivers/media/pci/cx23885/cx23888-ir.c
413
u16 *divider)
drivers/media/pci/cx23885/cx23888-ir.c
415
*divider = carrier_freq_to_clock_divider(freq);
drivers/media/pci/cx23885/cx23888-ir.c
416
cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
drivers/media/pci/cx23885/cx23888-ir.c
417
return clock_divider_to_carrier_freq(*divider);
drivers/media/pci/cx23885/cx23888-ir.c
422
u16 *divider)
drivers/media/pci/cx23885/cx23888-ir.c
424
*divider = carrier_freq_to_clock_divider(freq);
drivers/media/pci/cx23885/cx23888-ir.c
425
cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
drivers/media/pci/cx23885/cx23888-ir.c
426
return clock_divider_to_carrier_freq(*divider);
drivers/media/pci/cx23885/cx23888-ir.c
430
u16 *divider)
drivers/media/pci/cx23885/cx23888-ir.c
437
*divider = pulse_clocks_to_clock_divider(pulse_clocks);
drivers/media/pci/cx23885/cx23888-ir.c
438
cx23888_ir_write4(dev, CX23888_IR_TXCLK_REG, *divider);
drivers/media/pci/cx23885/cx23888-ir.c
439
return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
drivers/media/pci/cx23885/cx23888-ir.c
443
u16 *divider)
drivers/media/pci/cx23885/cx23888-ir.c
450
*divider = pulse_clocks_to_clock_divider(pulse_clocks);
drivers/media/pci/cx23885/cx23888-ir.c
451
cx23888_ir_write4(dev, CX23888_IR_RXCLK_REG, *divider);
drivers/media/pci/cx23885/cx23888-ir.c
452
return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
drivers/media/pci/cx23885/cx23888-ir.c
634
u16 divider = (u16) atomic_read(&state->rxclk_divider);
drivers/media/pci/cx23885/cx23888-ir.c
666
(u16)(p->hw_fifo_data & FIFO_RXTX), divider) / 1000;
drivers/media/platform/ti/omap3isp/isp.c
159
static void isp_xclk_update(struct isp_xclk *xclk, u32 divider)
drivers/media/platform/ti/omap3isp/isp.c
165
divider << ISPTCTRL_CTRL_DIVA_SHIFT);
drivers/media/platform/ti/omap3isp/isp.c
170
divider << ISPTCTRL_CTRL_DIVB_SHIFT);
drivers/media/platform/ti/omap3isp/isp.c
197
isp_xclk_update(xclk, xclk->divider);
drivers/media/platform/ti/omap3isp/isp.c
220
return parent_rate / xclk->divider;
drivers/media/platform/ti/omap3isp/isp.c
225
u32 divider;
drivers/media/platform/ti/omap3isp/isp.c
235
divider = DIV_ROUND_CLOSEST(parent_rate, *rate);
drivers/media/platform/ti/omap3isp/isp.c
236
if (divider >= ISPTCTRL_CTRL_DIV_BYPASS)
drivers/media/platform/ti/omap3isp/isp.c
237
divider = ISPTCTRL_CTRL_DIV_BYPASS - 1;
drivers/media/platform/ti/omap3isp/isp.c
239
*rate = parent_rate / divider;
drivers/media/platform/ti/omap3isp/isp.c
240
return divider;
drivers/media/platform/ti/omap3isp/isp.c
255
u32 divider;
drivers/media/platform/ti/omap3isp/isp.c
257
divider = isp_xclk_calc_divider(&rate, parent_rate);
drivers/media/platform/ti/omap3isp/isp.c
261
xclk->divider = divider;
drivers/media/platform/ti/omap3isp/isp.c
263
isp_xclk_update(xclk, divider);
drivers/media/platform/ti/omap3isp/isp.c
268
__func__, xclk->id == ISP_XCLK_A ? 'a' : 'b', rate, divider);
drivers/media/platform/ti/omap3isp/isp.c
309
xclk->divider = 1;
drivers/media/platform/ti/omap3isp/isp.h
133
unsigned int divider;
drivers/media/rc/ir-xmp-decoder.c
103
n[i] = (n[i] - XMP_NIBBLE_PREFIX) / divider;
drivers/media/rc/ir-xmp-decoder.c
75
int divider, i;
drivers/media/rc/ir-xmp-decoder.c
93
divider = (n[3] - XMP_NIBBLE_PREFIX) / 15 - 2000;
drivers/media/rc/ir-xmp-decoder.c
94
if (divider < 50) {
drivers/media/rc/ir-xmp-decoder.c
96
divider);
drivers/media/usb/dvb-usb/dib0700_core.c
433
u16 divider;
drivers/media/usb/dvb-usb/dib0700_core.c
445
divider = (u16) (30000 / scl_kHz);
drivers/media/usb/dvb-usb/dib0700_core.c
447
st->buf[2] = (u8) (divider >> 8);
drivers/media/usb/dvb-usb/dib0700_core.c
448
st->buf[3] = (u8) (divider & 0xff);
drivers/media/usb/dvb-usb/dib0700_core.c
449
divider = (u16) (72000 / scl_kHz);
drivers/media/usb/dvb-usb/dib0700_core.c
450
st->buf[4] = (u8) (divider >> 8);
drivers/media/usb/dvb-usb/dib0700_core.c
451
st->buf[5] = (u8) (divider & 0xff);
drivers/media/usb/dvb-usb/dib0700_core.c
452
divider = (u16) (72000 / scl_kHz); /* clock: 72MHz */
drivers/media/usb/dvb-usb/dib0700_core.c
453
st->buf[6] = (u8) (divider >> 8);
drivers/media/usb/dvb-usb/dib0700_core.c
454
st->buf[7] = (u8) (divider & 0xff);
drivers/mfd/sm501.c
392
int divider;
drivers/mfd/sm501.c
411
int divider;
drivers/mfd/sm501.c
418
for (divider = 1; divider <= max_div; divider += 2) {
drivers/mfd/sm501.c
422
diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq;
drivers/mfd/sm501.c
431
clock->divider = divider;
drivers/mfd/sm501.c
476
return clock->mclk / (clock->divider << clock->shift);
drivers/mfd/sm501.c
499
return clock->mclk / (clock->divider << clock->shift);
drivers/mfd/sm501.c
537
if (to.divider == 3)
drivers/mfd/sm501.c
539
else if (to.divider == 5)
drivers/mfd/sm501.c
547
if (to.divider == 3)
drivers/mfd/sm501.c
549
else if (to.divider == 5)
drivers/mfd/sm501.c
562
if (to.divider == 3)
drivers/mfd/sm501.c
574
if (to.divider == 3)
drivers/mmc/host/mxcmmc.c
788
unsigned int divider;
drivers/mmc/host/mxcmmc.c
793
for (divider = 1; divider <= 0xF; divider++) {
drivers/mmc/host/mxcmmc.c
796
x = (clk_in / (divider + 1));
drivers/mmc/host/mxcmmc.c
804
if (divider < 0x10)
drivers/mmc/host/mxcmmc.c
813
mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE);
drivers/mmc/host/mxcmmc.c
816
prescaler, divider, clk_in, clk_ios);
drivers/net/can/sja1000/sja1000_platform.c
183
u32 divider = priv->can.clock.freq * 2 / prop;
drivers/net/can/sja1000/sja1000_platform.c
185
if (divider > 1)
drivers/net/can/sja1000/sja1000_platform.c
186
priv->cdr |= divider / 2 - 1;
drivers/net/ethernet/intel/ice/ice_tspll.c
755
static int ice_tspll_get_div_e825c(u16 link_speed, unsigned int *divider)
drivers/net/ethernet/intel/ice/ice_tspll.c
761
*divider = 10;
drivers/net/ethernet/intel/ice/ice_tspll.c
765
*divider = 4;
drivers/net/ethernet/intel/ice/ice_tspll.c
770
*divider = 2;
drivers/net/ethernet/intel/ice/ice_tspll.c
773
*divider = 1;
drivers/net/ethernet/intel/ice/ice_tspll.c
797
unsigned int divider;
drivers/net/ethernet/intel/ice/ice_tspll.c
806
err = ice_tspll_get_div_e825c(link_speed, ÷r);
drivers/net/ethernet/intel/ice/ice_tspll.c
819
val |= FIELD_PREP(ICE_CGU_R10_SYNCE_ETHDIV_M1, divider - 1);
drivers/net/ethernet/intel/ice/ice_tspll.c
828
val |= FIELD_PREP(ICE_CGU_R10_SYNCE_CLKODIV_M1, divider - 1);
drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c
350
static u32 esw_qos_calc_bw_share(u32 value, u32 divider, u32 fw_max)
drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c
352
if (!divider)
drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c
356
DIV_ROUND_UP(value, divider), MLX5_MIN_BW_SHARE));
drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c
360
u32 divider,
drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c
366
bw_share = esw_qos_calc_bw_share(node->min_rate, divider, fw_max_bw_share);
drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c
376
u32 divider = esw_qos_calculate_min_rate_divider(esw, parent);
drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c
387
esw_qos_update_sched_node_bw_share(node, divider,
drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c
616
u32 divider, fw_max_bw_share;
drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c
619
divider = esw_qos_calculate_tc_bw_divider(tc_bw);
drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c
626
bw_share = esw_qos_calc_bw_share(bw_share, divider,
drivers/power/supply/cpcap-battery.c
256
s16 offset, u32 divider)
drivers/power/supply/cpcap-battery.c
260
if (!divider)
drivers/power/supply/cpcap-battery.c
267
acc = div_s64(acc, divider);
drivers/soc/qcom/qcom-geni-se.c
721
unsigned int divider;
drivers/soc/qcom/qcom-geni-se.c
732
divider = DIV_ROUND_UP(tbl[i], req_freq);
drivers/soc/qcom/qcom-geni-se.c
733
new_delta = req_freq - tbl[i] / divider;
drivers/soundwire/cadence_master.c
1352
int divider;
drivers/soundwire/cadence_master.c
1367
divider = (prop->mclk_freq * SDW_DOUBLE_RATE_FACTOR /
drivers/soundwire/cadence_master.c
1371
CDNS_MCP_CLK_MCLKD_MASK, divider);
drivers/soundwire/cadence_master.c
1373
CDNS_MCP_CLK_MCLKD_MASK, divider);
drivers/soundwire/cadence_master.c
1492
int divider;
drivers/soundwire/cadence_master.c
1499
divider = prop->mclk_freq * SDW_DOUBLE_RATE_FACTOR /
drivers/soundwire/cadence_master.c
1501
divider--; /* divider is 1/(N+1) */
drivers/soundwire/cadence_master.c
1508
cdns_updatel(cdns, mcp_clkctrl_off, CDNS_MCP_CLK_MCLKD_MASK, divider);
drivers/spi/spi-meson-spicc.c
790
struct clk_divider *divider = to_clk_divider(hw);
drivers/spi/spi-meson-spicc.c
791
struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
drivers/spi/spi-meson-spicc.c
802
struct clk_divider *divider = to_clk_divider(hw);
drivers/spi/spi-meson-spicc.c
803
struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
drivers/spi/spi-meson-spicc.c
814
struct clk_divider *divider = to_clk_divider(hw);
drivers/spi/spi-meson-spicc.c
815
struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
drivers/spi/spi-orion.c
161
unsigned divider = DIV_ROUND_UP(tclk_hz, speed);
drivers/spi/spi-orion.c
164
if (divider < 16) {
drivers/spi/spi-orion.c
166
spr = divider;
drivers/spi/spi-orion.c
177
sppr = fls(divider) - 4;
drivers/spi/spi-orion.c
184
divider = (divider + two_pow_sppr - 1) & -two_pow_sppr;
drivers/spi/spi-orion.c
193
sppr = fls(divider) - 4;
drivers/spi/spi-orion.c
194
spr = divider >> sppr;
drivers/spi/spi-xcomm.c
120
unsigned int divider;
drivers/spi/spi-xcomm.c
122
divider = DIV_ROUND_UP(SPI_XCOMM_CLOCK, t->speed_hz);
drivers/spi/spi-xcomm.c
123
if (divider >= 64)
drivers/spi/spi-xcomm.c
125
else if (divider >= 16)
drivers/staging/media/ipu3/ipu3-css-params.c
29
unsigned int divider)
drivers/staging/media/ipu3/ipu3-css-params.c
31
int i = fls(divider) - fls(counter);
drivers/staging/media/ipu3/ipu3-css-params.c
36
if (divider >> i < counter)
drivers/video/fbdev/aty/mach64_ct.c
121
u32 multiplier, divider, ras_multiplier, ras_divider, tmp;
drivers/video/fbdev/aty/mach64_ct.c
126
divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div;
drivers/video/fbdev/aty/mach64_ct.c
132
divider = divider * (bpp >> 2);
drivers/video/fbdev/aty/mach64_ct.c
144
divider = divider * pll->xres & ~7;
drivers/video/fbdev/aty/mach64_ct.c
152
while (((multiplier | divider) & 1) == 0) {
drivers/video/fbdev/aty/mach64_ct.c
154
divider = divider >> 1;
drivers/video/fbdev/aty/mach64_ct.c
158
tmp = ((multiplier * pll->fifo_size) << vshift) / divider;
drivers/video/fbdev/aty/mach64_ct.c
171
dsp_off = ((multiplier * (pll->fifo_size - 1)) << vshift) / divider -
drivers/video/fbdev/aty/mach64_ct.c
178
dsp_on = ((multiplier << vshift) + divider) / divider;
drivers/video/fbdev/aty/mach64_ct.c
190
dsp_on = dsp_off - (multiplier << vshift) / divider;
drivers/video/fbdev/aty/mach64_ct.c
195
dsp_xclks = ((multiplier << (vshift + 5)) + divider) / divider;
drivers/video/fbdev/aty/mach64_gx.c
504
short divider = 0, tempA;
drivers/video/fbdev/aty/mach64_gx.c
521
divider = 0;
drivers/video/fbdev/aty/mach64_gx.c
524
divider += 0x20;
drivers/video/fbdev/aty/mach64_gx.c
542
divider &= ~0x1f;
drivers/video/fbdev/aty/mach64_gx.c
543
divider |= tempA;
drivers/video/fbdev/aty/mach64_gx.c
544
divider =
drivers/video/fbdev/aty/mach64_gx.c
545
(divider & 0x00ff) +
drivers/video/fbdev/aty/mach64_gx.c
553
program_bits = divider;
drivers/video/fbdev/aty/mach64_gx.c
558
pll->ics2595.post_divider = divider; /* fuer nix */
drivers/video/fbdev/aty/mach64_gx.c
743
short divider = 0, tempA;
drivers/video/fbdev/aty/mach64_gx.c
762
divider += 0x40;
drivers/video/fbdev/aty/mach64_gx.c
779
divider &= ~0x3f;
drivers/video/fbdev/aty/mach64_gx.c
780
divider |= tempA;
drivers/video/fbdev/aty/mach64_gx.c
781
divider =
drivers/video/fbdev/aty/mach64_gx.c
782
(divider & 0x00FF) +
drivers/video/fbdev/aty/mach64_gx.c
789
program_bits = divider;
drivers/video/fbdev/aty/mach64_gx.c
794
pll->ics2595.post_divider = divider; /* fuer nix */
drivers/video/fbdev/aty/radeon_base.c
1525
int divider;
drivers/video/fbdev/aty/radeon_base.c
1596
for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
drivers/video/fbdev/aty/radeon_base.c
1597
pll_output_freq = post_div->divider * freq;
drivers/video/fbdev/aty/radeon_base.c
1601
if (uses_dvo && (post_div->divider & 1))
drivers/video/fbdev/aty/radeon_base.c
1610
if ( !post_div->divider ) {
drivers/video/fbdev/aty/radeon_base.c
1612
pll_output_freq = post_div->divider * freq;
drivers/video/fbdev/aty/radeon_base.c
1620
if ( !post_div->divider ) {
drivers/video/fbdev/aty/radeon_base.c
1622
pll_output_freq = post_div->divider * freq;
drivers/video/fbdev/au1200fb.c
1248
unsigned int hi1, divider;
drivers/video/fbdev/au1200fb.c
1261
divider = (lcd->pwmdiv & 0x3FFFF) + 1;
drivers/video/fbdev/au1200fb.c
1262
hi1 = (((pdata->brightness & 0xFF)+1) * divider >> 8);
drivers/video/fbdev/au1200fb.c
1277
unsigned int hi1, divider;
drivers/video/fbdev/au1200fb.c
1288
divider = (lcd->pwmdiv & 0x3FFFF) + 1;
drivers/video/fbdev/au1200fb.c
1289
pdata->brightness = ((hi1 << 8) / divider) - 1;
drivers/video/fbdev/matrox/matroxfb_misc.c
196
unsigned int divider;
drivers/video/fbdev/matrox/matroxfb_misc.c
248
divider = minfo->curr.final_bppShift;
drivers/video/fbdev/matrox/matroxfb_misc.c
249
while (divider & 3) {
drivers/video/fbdev/matrox/matroxfb_misc.c
254
divider <<= 1;
drivers/video/fbdev/matrox/matroxfb_misc.c
256
divider = divider / 4;
drivers/video/fbdev/matrox/matroxfb_misc.c
258
while (divider > 8) {
drivers/video/fbdev/matrox/matroxfb_misc.c
263
divider >>= 1;
drivers/video/fbdev/matrox/matroxfb_misc.c
302
hw->CRTCEXT[3] = (divider - 1) | 0x80;
drivers/watchdog/nic7018_wdt.c
54
u8 divider;
drivers/watchdog/nic7018_wdt.c
96
outb(counter << 4 | config->divider,
fs/gfs2/dir.c
1005
u32 start, len, half_len, divider;
fs/gfs2/dir.c
1076
divider = (start + half_len) << (32 - dip->i_depth);
fs/gfs2/dir.c
1087
be32_to_cpu(dent->de_hash) < divider) {
include/linux/clk/renesas.h
44
void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target);
include/linux/clk/renesas.h
46
static inline void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target) { }
include/linux/firmware/xlnx-zynqmp.h
570
int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
include/linux/firmware/xlnx-zynqmp.h
571
int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
include/linux/firmware/xlnx-zynqmp.h
673
static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
include/linux/firmware/xlnx-zynqmp.h
678
static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
include/linux/mfd/db8500-prcmu.h
504
int prcmu_set_clock_divider(u8 clock, u8 divider);
include/linux/mfd/db8500-prcmu.h
613
static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
include/linux/polynomial.h
19
long divider;
include/media/i2c/mt9t112.h
24
struct mt9t112_pll_divider divider;
kernel/sched/fair.c
3885
u32 divider = get_pelt_divider(&se->avg);
kernel/sched/fair.c
3887
se->avg.load_avg = div_u64(se_weight(se) * se->avg.load_sum, divider);
kernel/sched/fair.c
4337
u32 new_sum, divider;
kernel/sched/fair.c
4347
divider = get_pelt_divider(&cfs_rq->avg);
kernel/sched/fair.c
4351
new_sum = se->avg.util_avg * divider;
kernel/sched/fair.c
4363
u32 new_sum, divider;
kernel/sched/fair.c
4373
divider = get_pelt_divider(&cfs_rq->avg);
kernel/sched/fair.c
4377
new_sum = se->avg.runnable_avg * divider;
kernel/sched/fair.c
4392
u32 divider;
kernel/sched/fair.c
4403
divider = get_pelt_divider(&cfs_rq->avg);
kernel/sched/fair.c
4411
runnable_sum = min_t(long, runnable_sum, divider);
kernel/sched/fair.c
4436
load_avg = div_u64(load_sum, divider);
kernel/sched/fair.c
4635
u32 divider = get_pelt_divider(&cfs_rq->avg);
kernel/sched/fair.c
4645
__update_sa(sa, load, -r, -r*divider);
kernel/sched/fair.c
4648
__update_sa(sa, util, -r, -r*divider);
kernel/sched/fair.c
4651
__update_sa(sa, runnable, -r, -r*divider);
kernel/sched/fair.c
4658
-(long)(removed_runnable * divider) >> SCHED_CAPACITY_SHIFT);
kernel/sched/fair.c
4684
u32 divider = get_pelt_divider(&cfs_rq->avg);
kernel/sched/fair.c
4702
se->avg.util_sum = se->avg.util_avg * divider;
kernel/sched/fair.c
4704
se->avg.runnable_sum = se->avg.runnable_avg * divider;
kernel/sched/fair.c
4706
se->avg.load_sum = se->avg.load_avg * divider;
kernel/sched/pelt.c
260
u32 divider = get_pelt_divider(sa);
kernel/sched/pelt.c
265
sa->load_avg = div_u64(load * sa->load_sum, divider);
kernel/sched/pelt.c
266
sa->runnable_avg = div_u64(sa->runnable_sum, divider);
kernel/sched/pelt.c
267
WRITE_ONCE(sa->util_avg, sa->util_sum / divider);
kernel/sched/pelt.h
140
u32 divider = ((LOAD_AVG_MAX - 1024) << SCHED_CAPACITY_SHIFT) - LOAD_AVG_MAX;
kernel/sched/pelt.h
154
if (util_sum >= divider)
lib/polynomial.c
99
tmp = mult_frac(tmp, data, term->divider);
lib/zstd/compress/zstd_compress.c
1634
U32 const divider = (minMatch==3 || useSequenceProducer) ? 3 : 4;
lib/zstd/compress/zstd_compress.c
1635
return blockSize / divider;
sound/isa/es1688/es1688_lib.c
296
unsigned int bits, divider;
sound/isa/es1688/es1688_lib.c
303
divider = 256 - 7160000*20/(8*82*runtime->rate);
sound/isa/es1688/es1688_lib.c
306
snd_es1688_write(chip, 0xa2, divider);
sound/oss/dmasound/dmasound_atari.c
1035
int divider, i, idx;
sound/oss/dmasound/dmasound_atari.c
1065
divider = 1;
sound/oss/dmasound/dmasound_atari.c
1069
divider = 1;
sound/oss/dmasound/dmasound_atari.c
1072
divider = 2;
sound/oss/dmasound/dmasound_atari.c
1075
divider = 3;
sound/oss/dmasound/dmasound_atari.c
1078
divider = 4;
sound/oss/dmasound/dmasound_atari.c
1081
divider = 5;
sound/oss/dmasound/dmasound_atari.c
1084
divider = 7;
sound/oss/dmasound/dmasound_atari.c
1087
divider = 9;
sound/oss/dmasound/dmasound_atari.c
1090
divider = 11;
sound/oss/dmasound/dmasound_atari.c
1092
tt_dmasnd.int_div = divider;
sound/soc/spear/spdif_out.c
101
ctrl |= (divider << SPDIF_DIVIDER_SHIFT) & SPDIF_DIVIDER_MASK;
sound/soc/spear/spdif_out.c
94
u32 divider, ctrl;
sound/soc/spear/spdif_out.c
97
divider = DIV_ROUND_CLOSEST(clk_get_rate(host->clk), (rate * 128));
sound/soc/stm/stm32_i2s.c
255
unsigned int divider;
sound/soc/stm/stm32_i2s.c
289
unsigned int ratio, div, divider = 1;
sound/soc/stm/stm32_i2s.c
302
divider = ((2 * div) + odd);
sound/soc/stm/stm32_i2s.c
304
div, odd, divider);
sound/soc/stm/stm32_i2s.c
313
if (input_rate % divider)
sound/soc/stm/stm32_i2s.c
316
output_rate, input_rate / divider);
sound/soc/stm/stm32_i2s.c
320
i2s->divider = divider;
sound/soc/stm/stm32_i2s.c
475
mclk->freq = req->best_parent_rate / i2s->divider;
sound/soc/ti/omap-dmic.c
125
int divider = -EINVAL;
sound/soc/ti/omap-dmic.c
133
divider = 0x6; /* Divider: 5 (192KHz sampling rate) */
sound/soc/ti/omap-dmic.c
138
return divider;
sound/soc/ti/omap-dmic.c
145
divider = 0x4; /* Divider: 16 */
sound/soc/ti/omap-dmic.c
150
divider = 0x5; /* Divider: 5 */
sound/soc/ti/omap-dmic.c
153
divider = 0x0; /* Divider: 8 */
sound/soc/ti/omap-dmic.c
156
divider = 0x2; /* Divider: 10 */
sound/soc/ti/omap-dmic.c
165
divider = 0x3; /* Divider: 8 */
sound/soc/ti/omap-dmic.c
170
divider = 0x1; /* Divider: 5 (96KHz sampling rate) */
sound/soc/ti/omap-dmic.c
178
return divider;
sound/soc/ti/omap-mcbsp.c
944
int divider = 0;
sound/soc/ti/omap-mcbsp.c
958
divider = period_words / max_thrsh;
sound/soc/ti/omap-mcbsp.c
960
divider++;
sound/soc/ti/omap-mcbsp.c
961
while (period_words % divider &&
sound/soc/ti/omap-mcbsp.c
962
divider < period_words)
sound/soc/ti/omap-mcbsp.c
963
divider++;
sound/soc/ti/omap-mcbsp.c
964
if (divider == period_words)
sound/soc/ti/omap-mcbsp.c
967
pkt_size = period_words / divider;
