drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

1608

struct i2c_adapter *ddc = NULL;

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

1684

ddc = &amdgpu_connector->ddc_bus->adapter;

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

1697

ddc);

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

1718

ddc);

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

1764

ddc);

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

1784

ddc = &amdgpu_connector->ddc_bus->adapter;

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

1789

ddc);

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

1810

ddc = &amdgpu_connector->ddc_bus->adapter;

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

1815

ddc);

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

1841

ddc = &amdgpu_connector->ddc_bus->adapter;

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

1846

ddc);

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

1898

ddc = &amdgpu_connector->ddc_bus->adapter;

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

1903

ddc);

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

1945

ddc = &amdgpu_connector->ddc_bus->adapter;

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

1954

ddc);

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

1994

ddc = &amdgpu_connector->ddc_bus->adapter;

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

2003

ddc);

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

2023

ddc = &amdgpu_connector->ddc_bus->adapter;

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

2028

ddc);

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

272

&amdgpu_connector->ddc_bus->aux.ddc);

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

281

&amdgpu_connector->ddc_bus->aux.ddc);

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

512

ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2884

try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2886

try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7908

struct i2c_adapter *ddc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7912

ddc = &aconnector->dm_dp_aux.aux.ddc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7914

ddc = &aconnector->i2c->base;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7916

drm_edid = drm_edid_read_ddc(connector, ddc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7968

struct i2c_adapter *ddc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7971

ddc = &aconnector->dm_dp_aux.aux.ddc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7973

ddc = &aconnector->i2c->base;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

7975

drm_edid = drm_edid_read_ddc(connector, ddc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9207

i2c = create_i2c(link->ddc, false);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

777

struct mod_hdcp_ddc_funcs *ddc_funcs = &config->ddc.funcs;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

792

config->ddc.handle = dc_get_link_at_index(dc, i);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1008

struct i2c_adapter *ddc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1015

ddc = &aconnector->dm_dp_aux.aux.ddc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1017

ddc = &aconnector->i2c->base;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1027

drm_edid = drm_edid_read_ddc(connector, ddc);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

65

struct ddc_service *ddc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

839

aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

95

ddc = TO_DM_AUX(aux)->ddc_service;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

96

adev = ddc->ctx->driver_context;

drivers/gpu/drm/amd/display/dc/core/dc.c

6001

if (!dc->links[link_index]->ddc->ddc_pin)

drivers/gpu/drm/amd/display/dc/core/dc.c

6151

if (!dc->links[index]->ddc->ddc_pin) {

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

180

struct ddc_service *ddc = link->ddc;

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

184

ddc->ddc_pin,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

192

struct ddc_service *ddc = dc->res_pool->oem_device;

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

194

if (ddc)

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

197

ddc->ddc_pin,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

296

int dc_link_aux_transfer_raw(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

300

const struct dc *dc = ddc->link->dc;

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

303

ddc, payload, operation_result);

drivers/gpu/drm/amd/display/dc/dc.h

1671

struct ddc_service *ddc;

drivers/gpu/drm/amd/display/dc/dc.h

2141

int dc_link_aux_transfer_raw(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/dc_ddc_types.h

185

struct ddc *ddc_pin;

drivers/gpu/drm/amd/display/dc/dc_fused_io.c

106

const uint32_t ddc_line = link->ddc->ddc_pin->pin_data->en;

drivers/gpu/drm/amd/display/dc/dc_fused_io.c

134

const uint32_t ddc_line = link->ddc->ddc_pin->pin_data->en;

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

277

EVENT_LOG_AUX_REQ(engine->ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_NATIVE,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

400

struct ddc *ddc)

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

407

result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

414

engine->ddc = ddc;

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

419

engine->ddc = ddc;

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

434

static uint32_t dce_aux_configure_timeout(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

442

struct ddc *ddc_pin = ddc->ddc_pin;

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

443

struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

516

aux_engine110->base.ddc = NULL;

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

559

int dce_aux_transfer_raw(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

563

struct ddc *ddc_pin = ddc->ddc_pin;

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

577

aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

604

EVENT_LOG_AUX_REP(aux_engine->ddc->pin_data->en,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

616

int dce_aux_transfer_dmub_raw(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

620

struct ddc *ddc_pin = ddc->ddc_pin;

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

623

struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

632

return dm_helper_dmub_aux_transfer_sync(ddc->ctx, ddc->link, payload, operation_result);

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

695

bool dce_aux_transfer_with_retries(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

703

struct ddc *ddc_pin = ddc->ddc_pin;

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

716

aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

730

ddc && ddc->link ? ddc->link->link_index : UINT_MAX,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

738

(ddc->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? true : false,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

739

ddc->link->ddc_hw_inst);

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

744

if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

745

|| ddc->ddc_pin == NULL) {

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

746

ret = dce_aux_transfer_dmub_raw(ddc, payload, &operation_result);

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

748

ret = dce_aux_transfer_raw(ddc, payload, &operation_result);

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

756

ddc && ddc->link ? ddc->link->link_index : UINT_MAX,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

767

(ddc->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? true : false,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

768

ddc->link->ddc_hw_inst);

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

83

dal_ddc_close(engine->ddc);

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

85

engine->ddc = NULL;

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

243

struct ddc *ddc;

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

301

struct ddc *ddc);

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

303

int dce_aux_transfer_raw(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

307

int dce_aux_transfer_dmub_raw(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

310

bool dce_aux_transfer_with_retries(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

315

(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c

30

struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c

34

struct dc *dc = ddc->ctx->dc;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c

56

struct ddc *ddc,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c

62

if (!ddc) {

drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c

72

dce_i2c_hw = acquire_i2c_hw_engine(pool, ddc);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c

75

return dce_i2c_submit_command_hw(pool, ddc, cmd, dce_i2c_hw);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c

77

dce_i2c_sw.ctx = ddc->ctx;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c

78

if (dce_i2c_engine_acquire_sw(&dce_i2c_sw, ddc)) {

drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c

79

return dce_i2c_submit_command_sw(pool, ddc, cmd, &dce_i2c_sw);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c.h

35

struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c.h

41

struct ddc *ddc,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

444

struct ddc *ddc)

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

450

if (!ddc)

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

453

if (ddc->hw_info.hw_supported) {

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

454

enum gpio_ddc_line line = dal_ddc_get_line(ddc);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

467

result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

483

dce_i2c_hw->ddc = ddc;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

630

struct ddc *ddc,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

658

dal_ddc_close(dce_i2c_hw->ddc);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

660

dce_i2c_hw->ddc = NULL;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

287

struct ddc *ddc;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

347

struct ddc *ddc,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

353

struct ddc *ddc);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

154

struct ddc *ddc_handle,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

214

struct ddc *ddc_handle,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

251

struct ddc *ddc_handle,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

273

struct ddc *ddc_handle,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

298

struct ddc *ddc_handle,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

356

struct ddc *ddc)

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

360

result = dal_ddc_open(ddc, GPIO_MODE_FAST_OUTPUT,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

366

engine->ddc = ddc;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

373

struct ddc *ddc_handle)

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

399

struct ddc *ddc = engine->ddc;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

40

struct ddc *ddc,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

404

bool result = start_sync_sw(engine->ctx, ddc, clock_delay_div_4);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

412

result = i2c_write_sw(engine->ctx, ddc, clock_delay_div_4,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

417

result = i2c_read_sw(engine->ctx, ddc, clock_delay_div_4,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

431

if (!stop_sync_sw(engine->ctx, ddc, clock_delay_div_4))

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

46

dal_gpio_get_value(ddc->pin_data, &value);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

468

struct ddc *ddc,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

48

dal_gpio_get_value(ddc->pin_clock, &value);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

54

struct ddc *ddc,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

61

dal_gpio_set_value(ddc->pin_data, value);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

63

dal_gpio_set_value(ddc->pin_clock, value);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

70

dal_ddc_close(dce_i2c_sw->ddc);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

71

dce_i2c_sw->ddc = NULL;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

76

struct ddc *ddc,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

85

if (read_bit_from_ddc(ddc, SCL))

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c

97

struct ddc *ddc_handle,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.h

36

struct ddc *ddc;

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.h

48

struct ddc *ddc,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.h

54

struct ddc *ddc_handle);

drivers/gpu/drm/amd/display/dc/dm_event_log.h

34

#define EVENT_LOG_AUX_REQ(ddc, type, action, address, len, data)

drivers/gpu/drm/amd/display/dc/dm_event_log.h

35

#define EVENT_LOG_AUX_REP(ddc, type, replyStatus, len, data)

drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

116

struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);

drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

120

ddc->regs = &ddc_data_regs[en];

drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

121

ddc->base.regs = &ddc_data_regs[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

124

ddc->regs = &ddc_clk_regs[en];

drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

125

ddc->base.regs = &ddc_clk_regs[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

132

ddc->shifts = &ddc_shift;

drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c

133

ddc->masks = &ddc_mask;

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

133

struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

137

ddc->regs = &ddc_data_regs[en];

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

138

ddc->base.regs = &ddc_data_regs[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

141

ddc->regs = &ddc_clk_regs[en];

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

142

ddc->base.regs = &ddc_clk_regs[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

149

ddc->shifts = &ddc_shift;

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

150

ddc->masks = &ddc_mask;

drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c

120

struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);

drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c

124

ddc->regs = &ddc_data_regs[en];

drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c

125

ddc->base.regs = &ddc_data_regs[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c

128

ddc->regs = &ddc_clk_regs[en];

drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c

129

ddc->base.regs = &ddc_clk_regs[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c

136

ddc->shifts = &ddc_shift;

drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c

137

ddc->masks = &ddc_mask;

drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c

120

struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);

drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c

124

ddc->regs = &ddc_data_regs[en];

drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c

125

ddc->base.regs = &ddc_data_regs[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c

128

ddc->regs = &ddc_clk_regs[en];

drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c

129

ddc->base.regs = &ddc_clk_regs[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c

136

ddc->shifts = &ddc_shift;

drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c

137

ddc->masks = &ddc_mask;

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

165

struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

169

ddc->regs = &ddc_data_regs[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

170

ddc->base.regs = &ddc_data_regs[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

173

ddc->regs = &ddc_clk_regs[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

174

ddc->base.regs = &ddc_clk_regs[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

181

ddc->shifts = &ddc_shift;

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

182

ddc->masks = &ddc_mask;

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

185

struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

189

ddc->regs = &ddc_data_regs_dcn[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

190

ddc->base.regs = &ddc_data_regs_dcn[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

193

ddc->regs = &ddc_clk_regs_dcn[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

194

ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

201

ddc->shifts = &ddc_shift[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

202

ddc->masks = &ddc_mask[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

173

struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

177

ddc->regs = &ddc_data_regs_dcn[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

178

ddc->base.regs = &ddc_data_regs_dcn[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

181

ddc->regs = &ddc_clk_regs_dcn[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

182

ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

189

ddc->shifts = &ddc_shift[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

190

ddc->masks = &ddc_mask[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

202

struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

206

ddc->regs = &ddc_data_regs_dcn[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

207

ddc->base.regs = &ddc_data_regs_dcn[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

210

ddc->regs = &ddc_clk_regs_dcn[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

211

ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

218

ddc->shifts = &ddc_shift[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

219

ddc->masks = &ddc_mask[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

194

struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

198

ddc->regs = &ddc_data_regs_dcn[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

199

ddc->base.regs = &ddc_data_regs_dcn[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

202

ddc->regs = &ddc_clk_regs_dcn[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

203

ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

210

ddc->shifts = &ddc_shift[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

211

ddc->masks = &ddc_mask[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

206

struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

210

ddc->regs = &ddc_data_regs_dcn[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

211

ddc->base.regs = &ddc_data_regs_dcn[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

214

ddc->regs = &ddc_clk_regs_dcn[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

215

ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

222

ddc->shifts = &ddc_shift[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

223

ddc->masks = &ddc_mask[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

198

struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

202

ddc->regs = &ddc_data_regs_dcn[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

203

ddc->base.regs = &ddc_data_regs_dcn[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

206

ddc->regs = &ddc_clk_regs_dcn[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

207

ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

214

ddc->shifts = &ddc_shift[en];

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

215

ddc->masks = &ddc_mask[en];

drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c

238

return gpio->hw_container.ddc;

drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c

290

gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en);

drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c

293

gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en);

drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c

324

kfree((*gpio)->hw_container.ddc);

drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c

325

(*gpio)->hw_container.ddc = NULL;

drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c

329

kfree((*gpio)->hw_container.ddc);

drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c

330

(*gpio)->hw_container.ddc = NULL;

drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c

69

if (!gpio->hw_container.ddc) {

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

488

struct ddc *dal_gpio_create_ddc(

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

496

struct ddc *ddc;

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

501

ddc = kzalloc_obj(struct ddc);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

503

if (!ddc) {

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

508

ddc->pin_data = dal_gpio_create(

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

511

if (!ddc->pin_data) {

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

516

ddc->pin_clock = dal_gpio_create(

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

519

if (!ddc->pin_clock) {

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

524

ddc->hw_info = *info;

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

526

ddc->ctx = service->ctx;

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

528

return ddc;

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

531

dal_gpio_destroy(&ddc->pin_data);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

534

kfree(ddc);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

540

struct ddc **ddc)

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

542

if (!ddc || !*ddc) {

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

547

dal_ddc_close(*ddc);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

548

dal_gpio_destroy(&(*ddc)->pin_data);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

549

dal_gpio_destroy(&(*ddc)->pin_clock);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

550

kfree(*ddc);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

552

*ddc = NULL;

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

556

struct ddc *ddc,

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

566

result = dal_gpio_open_ex(ddc->pin_data, mode);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

573

result = dal_gpio_open_ex(ddc->pin_clock, mode);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

591

config_data.config.ddc.type = config_type;

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

593

hw_data = FROM_HW_GPIO_PIN(ddc->pin_data->pin);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

594

hw_clock = FROM_HW_GPIO_PIN(ddc->pin_clock->pin);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

596

config_data.config.ddc.data_en_bit_present = hw_data->store.en != 0;

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

597

config_data.config.ddc.clock_en_bit_present = hw_clock->store.en != 0;

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

599

result = dal_gpio_set_config(ddc->pin_data, &config_data);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

606

dal_gpio_close(ddc->pin_clock);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

609

dal_gpio_close(ddc->pin_data);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

615

struct ddc *ddc,

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

621

dal_gpio_get_mode(ddc->pin_data);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

623

result = dal_gpio_change_mode(ddc->pin_data, mode);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

633

result = dal_gpio_change_mode(ddc->pin_clock, mode);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

638

dal_gpio_change_mode(ddc->pin_clock, original_mode);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

641

dal_gpio_change_mode(ddc->pin_data, original_mode);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

647

const struct ddc *ddc)

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

649

return (enum gpio_ddc_line)dal_gpio_get_enum(ddc->pin_data);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

653

struct ddc *ddc,

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

660

config_data.config.ddc.type = config_type;

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

661

config_data.config.ddc.data_en_bit_present = false;

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

662

config_data.config.ddc.clock_en_bit_present = false;

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

664

return dal_gpio_set_config(ddc->pin_data, &config_data);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

668

struct ddc *ddc)

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

670

if (ddc != NULL) {

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

671

dal_gpio_close(ddc->pin_clock);

drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c

672

dal_gpio_close(ddc->pin_data);

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

139

if (config_data->config.ddc.data_en_bit_present ||

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

140

config_data->config.ddc.clock_en_bit_present)

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

152

if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) {

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

156

if (ddc->regs->phy_aux_cntl != 0) {

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

166

if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) {

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

216

struct hw_ddc *ddc,

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

221

dal_hw_gpio_construct(&ddc->base, id, en, ctx);

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

222

ddc->base.base.funcs = &funcs;

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

39

ddc->shifts->field_name, ddc->masks->field_name

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

42

ddc->base.base.ctx

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

44

(ddc->regs->reg)

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

70

struct hw_ddc *ddc = HW_DDC_FROM_BASE(ptr);

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

77

hw_gpio = &ddc->base;

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

89

switch (config_data->config.ddc.type) {

drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c

178

i2c_command.speed = link->ddc->ctx->dc->caps.i2c_speed_in_khz;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3500

if (stream->link && stream->link->ddc) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3502

stream->link->ddc->dongle_type;

drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h

150

struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h

177

struct ddc *ddc);

drivers/gpu/drm/amd/display/dc/inc/hw/aux_engine.h

92

struct ddc *ddc;

drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h

33

struct hw_ddc *ddc;

drivers/gpu/drm/amd/display/dc/inc/link_service.h

172

void (*destroy_ddc_service)(struct ddc_service **ddc);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

174

struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/inc/link_service.h

180

int (*aux_transfer_raw)(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/inc/link_service.h

184

struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/inc/link_service.h

187

bool (*aux_transfer_with_retries_no_mutex)(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/inc/link_service.h

189

bool (*is_in_aux_transaction_mode)(struct ddc_service *ddc);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

190

uint32_t (*get_aux_defer_delay)(struct ddc_service *ddc);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

107

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

120

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

150

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

152

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

154

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

156

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

158

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

52

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

54

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

56

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

58

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

60

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

62

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

64

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

66

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

68

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c

70

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

100

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

102

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

104

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

108

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

111

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

115

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

118

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

139

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

62

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

64

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

66

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

68

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

70

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

92

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

94

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

96

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c

98

link->dc->link_srv->configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1139

set_ddc_transaction_type(link->ddc,

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1143

link_is_in_aux_transaction_mode(link->ddc);

drivers/gpu/drm/amd/display/dc/link/link_detection.c

1247

read_scdc_caps(link->ddc, link->local_sink);

drivers/gpu/drm/amd/display/dc/link/link_detection.c

288

struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/link/link_detection.c

310

.speed = ddc->ctx->dc->caps.i2c_speed_in_khz };

drivers/gpu/drm/amd/display/dc/link/link_detection.c

313

ddc->ctx,

drivers/gpu/drm/amd/display/dc/link/link_detection.c

314

ddc->link,

drivers/gpu/drm/amd/display/dc/link/link_detection.c

324

struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/link/link_detection.c

334

struct dc_link *link = ddc->link;

drivers/gpu/drm/amd/display/dc/link/link_detection.c

342

ddc,

drivers/gpu/drm/amd/display/dc/link/link_detection.c

348

if (i2c_read(ddc,

drivers/gpu/drm/amd/display/dc/link/link_detection.c

359

CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf),

drivers/gpu/drm/amd/display/dc/link/link_detection.c

408

CONN_DATA_DETECT(ddc->link, type2_dongle_buf,

drivers/gpu/drm/amd/display/dc/link/link_detection.c

416

CONN_DATA_DETECT(ddc->link, type2_dongle_buf,

drivers/gpu/drm/amd/display/dc/link/link_detection.c

423

CONN_DATA_DETECT(ddc->link, type2_dongle_buf,

drivers/gpu/drm/amd/display/dc/link/link_detection.c

440

CONN_DATA_DETECT(ddc->link, type2_dongle_buf,

drivers/gpu/drm/amd/display/dc/link/link_detection.c

447

CONN_DATA_DETECT(ddc->link, type2_dongle_buf,

drivers/gpu/drm/amd/display/dc/link/link_detection.c

458

static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/link/link_detection.c

462

query_dp_dual_mode_adaptor(ddc, sink_cap);

drivers/gpu/drm/amd/display/dc/link/link_detection.c

496

link->ddc->transaction_type ==

drivers/gpu/drm/amd/display/dc/link/link_detection.c

614

sink_caps->signal = dp_passive_dongle_detection(link->ddc,

drivers/gpu/drm/amd/display/dc/link/link_detection.c

906

if (!link->ddc)

drivers/gpu/drm/amd/display/dc/link/link_detection.c

910

bool ddc_probed = i2c_read(link->ddc, 0x50, edid_header, sizeof(edid_header));

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1951

stream->link->ddc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1977

read_scdc_data(link->ddc);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2362

link->ddc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

396

pipe_ctx->stream->link->ddc,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

446

pipe_ctx->stream->link->ddc,

drivers/gpu/drm/amd/display/dc/link/link_factory.c

374

if (link->ddc)

drivers/gpu/drm/amd/display/dc/link/link_factory.c

375

link_destroy_ddc_service(&link->ddc);

drivers/gpu/drm/amd/display/dc/link/link_factory.c

401

struct ddc *ddc;

drivers/gpu/drm/amd/display/dc/link/link_factory.c

406

ddc = get_ddc_pin(link->ddc);

drivers/gpu/drm/amd/display/dc/link/link_factory.c

408

if (ddc) {

drivers/gpu/drm/amd/display/dc/link/link_factory.c

409

switch (dal_ddc_get_line(ddc)) {

drivers/gpu/drm/amd/display/dc/link/link_factory.c

545

link->ddc = link_create_ddc_service(&ddc_service_init_data);

drivers/gpu/drm/amd/display/dc/link/link_factory.c

547

if (!link->ddc) {

drivers/gpu/drm/amd/display/dc/link/link_factory.c

552

if (!link->ddc->ddc_pin) {

drivers/gpu/drm/amd/display/dc/link/link_factory.c

558

dal_ddc_get_line(get_ddc_pin(link->ddc));

drivers/gpu/drm/amd/display/dc/link/link_factory.c

810

if (link->ddc)

drivers/gpu/drm/amd/display/dc/link/link_factory.c

811

link_destroy_ddc_service(&link->ddc);

drivers/gpu/drm/amd/display/dc/link/link_factory.c

864

link->ddc = link_create_ddc_service(&ddc_service_init_data);

drivers/gpu/drm/amd/display/dc/link/link_factory.c

865

if (!link->ddc) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

168

static void ddc_service_destruct(struct ddc_service *ddc)

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

170

if (ddc->ddc_pin)

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

171

dal_gpio_destroy_ddc(&ddc->ddc_pin);

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

174

void link_destroy_ddc_service(struct ddc_service **ddc)

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

176

if (!ddc || !*ddc) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

180

ddc_service_destruct(*ddc);

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

181

kfree(*ddc);

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

182

*ddc = NULL;

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

186

struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

189

ddc->transaction_type = type;

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

192

bool link_is_in_aux_transaction_mode(struct ddc_service *ddc)

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

194

switch (ddc->transaction_type) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

205

void set_dongle_type(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

208

ddc->dongle_type = dongle_type;

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

212

struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

215

struct dc_link *link = ddc->link;

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

247

uint32_t link_get_aux_defer_delay(struct ddc_service *ddc)

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

251

switch (ddc->transaction_type) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

253

if ((DISPLAY_DONGLE_DP_VGA_CONVERTER == ddc->dongle_type) ||

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

254

(DISPLAY_DONGLE_DP_DVI_CONVERTER == ddc->dongle_type) ||

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

256

ddc->dongle_type)) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

261

defer_delay_converter_wa(ddc, defer_delay);

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

275

static bool submit_aux_command(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

281

if (!ddc)

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

305

ret = link_aux_transfer_with_retries_no_mutex(ddc, &current_payload);

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

314

struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

323

link_is_in_aux_transaction_mode(ddc) ?

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

337

if (link_is_in_aux_transaction_mode(ddc)) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

343

payload.defer_delay = link_get_aux_defer_delay(ddc);

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

355

success = submit_aux_command(ddc, &payload);

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

367

success = submit_aux_command(ddc, &payload);

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

373

if (!i2c_payloads_create(ddc->ctx, &payloads, payloads_num))

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

379

command.speed = ddc->ctx->dc->caps.i2c_speed_in_khz;

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

391

ddc->ctx,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

392

ddc->link,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

401

int link_aux_transfer_raw(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

405

if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc ||

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

406

!ddc->ddc_pin) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

407

return dce_aux_transfer_dmub_raw(ddc, payload, operation_result);

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

409

return dce_aux_transfer_raw(ddc, payload, operation_result);

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

459

bool link_configure_fixed_vs_pe_retimer(struct ddc_service *ddc, const uint8_t *data, uint32_t length)

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

464

.address = link_get_fixed_vs_pe_retimer_write_address(ddc->link),

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

473

return link_aux_transfer_with_retries_no_mutex(ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

477

bool link_query_fixed_vs_pe_retimer(struct ddc_service *ddc, uint8_t *data, uint32_t length)

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

482

.address = link_get_fixed_vs_pe_retimer_read_address(ddc->link),

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

491

return link_aux_transfer_with_retries_no_mutex(ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

495

bool link_aux_transfer_with_retries_no_mutex(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

498

return dce_aux_transfer_with_retries(ddc, payload);

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

502

bool try_to_configure_aux_timeout(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

506

struct ddc *ddc_pin = ddc->ddc_pin;

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

508

if (((ddc->link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

509

!ddc->link->dc->debug.disable_fixed_vs_aux_timeout_wa &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

510

ddc->ctx->dce_version == DCN_VERSION_3_1) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

515

core_link_write_dpcd(ddc->link,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

524

if (ddc->link->ep_type != DISPLAY_ENDPOINT_PHY)

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

527

if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

528

ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout);

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c

535

struct ddc *get_ddc_pin(struct ddc_service *ddc_service)

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h

100

struct ddc *get_ddc_pin(struct ddc_service *ddc_service);

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h

102

int link_aux_transfer_raw(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h

43

void link_destroy_ddc_service(struct ddc_service **ddc);

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h

46

struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h

49

uint32_t link_get_aux_defer_delay(struct ddc_service *ddc);

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h

51

bool link_is_in_aux_transaction_mode(struct ddc_service *ddc);

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h

53

bool try_to_configure_aux_timeout(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h

57

struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h

72

bool link_aux_transfer_with_retries_no_mutex(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h

76

struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h

81

struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h

97

void set_dongle_type(struct ddc_service *ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1167

set_dongle_type(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1266

set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1769

try_to_configure_aux_timeout(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1817

try_to_configure_aux_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2560

struct ddc *ddc;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2570

ddc = get_ddc_pin(link->ddc);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2572

if (!ddc) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2583

if (dal_ddc_open(ddc, GPIO_MODE_INPUT,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2585

dal_ddc_close(ddc);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2599

gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

2609

dal_ddc_close(ddc);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

123

replay_context.aux_inst = link->ddc->ddc_pin->hw_info.ddc_channel;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

159

if (!link->ddc->ddc_pin && !link->aux_access_disabled &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

238

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

240

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

242

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

246

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

301

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

306

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

308

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

310

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

312

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

314

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

364

if (link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

369

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

385

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

387

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

460

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

463

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

491

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

493

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

507

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

55

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

58

link_query_fixed_vs_pe_retimer(link->ddc, &dprx_vs, 1);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

60

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

63

link_query_fixed_vs_pe_retimer(link->ddc, &dprx_pe, 1);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

90

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

93

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

96

link_configure_fixed_vs_pe_retimer(link->ddc,

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1027

replay_context.aux_inst = link->ddc->ddc_pin->hw_info.ddc_channel;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

795

psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;

drivers/gpu/drm/amd/display/include/gpio_service_interface.h

106

struct ddc *ddc,

drivers/gpu/drm/amd/display/include/gpio_service_interface.h

111

struct ddc *ddc,

drivers/gpu/drm/amd/display/include/gpio_service_interface.h

115

const struct ddc *ddc);

drivers/gpu/drm/amd/display/include/gpio_service_interface.h

118

struct ddc *ddc,

drivers/gpu/drm/amd/display/include/gpio_service_interface.h

122

struct ddc *ddc);

drivers/gpu/drm/amd/display/include/gpio_service_interface.h

71

struct ddc *dal_gpio_create_ddc(

drivers/gpu/drm/amd/display/include/gpio_service_interface.h

78

struct ddc **ddc);

drivers/gpu/drm/amd/display/include/gpio_types.h

325

struct gpio_ddc_config ddc;

drivers/gpu/drm/amd/display/include/link_service_types.h

34

struct ddc;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

172

success = hdcp->config.ddc.funcs.read_dpcd(hdcp->config.ddc.handle,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

188

success = hdcp->config.ddc.funcs.read_i2c(

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

189

hdcp->config.ddc.handle,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

243

success = hdcp->config.ddc.funcs.write_dpcd(

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

244

hdcp->config.ddc.handle,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

262

success = hdcp->config.ddc.funcs.write_i2c(

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

263

hdcp->config.ddc.handle,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

685

return hdcp->config.ddc.funcs.write_dpcd(hdcp->config.ddc.handle, cp_irq_addrs,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

710

return hdcp->config.ddc.funcs.atomic_write_poll_read_aux(

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

711

hdcp->config.ddc.handle,

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

747

return hdcp->config.ddc.funcs.atomic_write_poll_read_i2c(

drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c

748

hdcp->config.ddc.handle,

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h

325

struct mod_hdcp_ddc ddc;

drivers/gpu/drm/ast/ast_ddc.c

118

struct ast_ddc *ddc = data;

drivers/gpu/drm/ast/ast_ddc.c

119

struct ast_device *ast = ddc->ast;

drivers/gpu/drm/ast/ast_ddc.c

140

struct ast_ddc *ddc = res;

drivers/gpu/drm/ast/ast_ddc.c

142

i2c_del_adapter(&ddc->adapter);

drivers/gpu/drm/ast/ast_ddc.c

148

struct ast_ddc *ddc;

drivers/gpu/drm/ast/ast_ddc.c

153

ddc = drmm_kzalloc(dev, sizeof(*ddc), GFP_KERNEL);

drivers/gpu/drm/ast/ast_ddc.c

154

if (!ddc)

drivers/gpu/drm/ast/ast_ddc.c

156

ddc->ast = ast;

drivers/gpu/drm/ast/ast_ddc.c

158

bit = &ddc->bit;

drivers/gpu/drm/ast/ast_ddc.c

159

bit->data = ddc;

drivers/gpu/drm/ast/ast_ddc.c

169

adapter = &ddc->adapter;

drivers/gpu/drm/ast/ast_ddc.c

174

i2c_set_adapdata(adapter, ddc);

drivers/gpu/drm/ast/ast_ddc.c

182

ret = drmm_add_action_or_reset(dev, ast_ddc_release, ddc);

drivers/gpu/drm/ast/ast_ddc.c

186

return &ddc->adapter;

drivers/gpu/drm/ast/ast_ddc.c

42

struct ast_ddc *ddc = data;

drivers/gpu/drm/ast/ast_ddc.c

43

struct ast_device *ast = ddc->ast;

drivers/gpu/drm/ast/ast_ddc.c

58

struct ast_ddc *ddc = data;

drivers/gpu/drm/ast/ast_ddc.c

59

struct ast_device *ast = ddc->ast;

drivers/gpu/drm/ast/ast_ddc.c

74

struct ast_ddc *ddc = i2c_get_adapdata(adapter);

drivers/gpu/drm/ast/ast_ddc.c

75

struct ast_device *ast = ddc->ast;

drivers/gpu/drm/ast/ast_ddc.c

88

struct ast_ddc *ddc = i2c_get_adapdata(adapter);

drivers/gpu/drm/ast/ast_ddc.c

89

struct ast_device *ast = ddc->ast;

drivers/gpu/drm/ast/ast_ddc.c

96

struct ast_ddc *ddc = data;

drivers/gpu/drm/ast/ast_ddc.c

97

struct ast_device *ast = ddc->ast;

drivers/gpu/drm/ast/ast_sil164.c

110

DRM_MODE_CONNECTOR_DVII, ddc);

drivers/gpu/drm/ast/ast_sil164.c

84

struct i2c_adapter *ddc;

drivers/gpu/drm/ast/ast_sil164.c

92

ddc = ast_ddc_create(ast);

drivers/gpu/drm/ast/ast_sil164.c

93

if (IS_ERR(ddc))

drivers/gpu/drm/ast/ast_sil164.c

94

return PTR_ERR(ddc);

drivers/gpu/drm/ast/ast_vga.c

110

DRM_MODE_CONNECTOR_VGA, ddc);

drivers/gpu/drm/ast/ast_vga.c

84

struct i2c_adapter *ddc;

drivers/gpu/drm/ast/ast_vga.c

92

ddc = ast_ddc_create(ast);

drivers/gpu/drm/ast/ast_vga.c

93

if (IS_ERR(ddc))

drivers/gpu/drm/ast/ast_vga.c

94

return PTR_ERR(ddc);

drivers/gpu/drm/bridge/analogix/analogix-anx6345.c

445

anx6345->drm_edid = drm_edid_read_ddc(connector, &anx6345->aux.ddc);

drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c

816

anx78xx->drm_edid = drm_edid_read_ddc(connector, &anx78xx->aux.ddc);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

959

drm_edid = drm_edid_read_ddc(connector, &dp->aux.ddc);

drivers/gpu/drm/bridge/chrontel-ch7033.c

303

priv->next_bridge->ddc);

drivers/gpu/drm/bridge/display-connector.c

327

conn->bridge.ddc = of_get_i2c_adapter_by_node(phandle);

drivers/gpu/drm/bridge/display-connector.c

329

if (!conn->bridge.ddc)

drivers/gpu/drm/bridge/display-connector.c

373

if (conn->bridge.ddc)

drivers/gpu/drm/bridge/display-connector.c

386

conn->bridge.ddc ? "with" : "without",

drivers/gpu/drm/bridge/display-connector.c

407

if (!IS_ERR(conn->bridge.ddc))

drivers/gpu/drm/bridge/display-connector.c

408

i2c_put_adapter(conn->bridge.ddc);

drivers/gpu/drm/bridge/display-connector.c

54

if (conn->bridge.ddc && drm_probe_ddc(conn->bridge.ddc))

drivers/gpu/drm/bridge/display-connector.c

95

return drm_edid_read_ddc(connector, conn->bridge.ddc);

drivers/gpu/drm/bridge/inno-hdmi.c

1126

hdmi->bridge.ddc = inno_hdmi_i2c_adapter(hdmi);

drivers/gpu/drm/bridge/inno-hdmi.c

1127

if (IS_ERR(hdmi->bridge.ddc))

drivers/gpu/drm/bridge/inno-hdmi.c

1128

return ERR_CAST(hdmi->bridge.ddc);

drivers/gpu/drm/bridge/inno-hdmi.c

406

struct i2c_adapter *ddc;

drivers/gpu/drm/bridge/inno-hdmi.c

858

drm_edid = drm_edid_read_ddc(connector, bridge->ddc);

drivers/gpu/drm/bridge/simple-bridge.c

124

sbridge->bridge.next_bridge->ddc);

drivers/gpu/drm/bridge/synopsys/dw-dp.c

1753

edid = drm_edid_read_ddc(connector, &dp->aux.ddc);

drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c

1361

hdmi->bridge.ddc = dw_hdmi_qp_i2c_adapter(hdmi);

drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c

1362

if (IS_ERR(hdmi->bridge.ddc))

drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c

1363

return ERR_CAST(hdmi->bridge.ddc);

drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c

917

drm_edid = drm_edid_read_ddc(connector, bridge->ddc);

drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c

934

drm_edid = drm_edid_read_ddc(connector, bridge->ddc);

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

1388

if (!hdmi->ddc)

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

159

struct i2c_adapter *ddc;

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2112

drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION,

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2114

drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION,

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2476

if (!hdmi->ddc)

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2479

drm_edid = drm_edid_read_ddc(connector, hdmi->ddc);

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

2602

hdmi->ddc);

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

3378

hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

3380

if (!hdmi->ddc) {

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

3490

if (!hdmi->ddc) {

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

3509

hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

3510

if (IS_ERR(hdmi->ddc))

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

3511

hdmi->ddc = NULL;

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

3518

hdmi->bridge.ddc = hdmi->ddc;

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

3601

i2c_put_adapter(hdmi->ddc);

drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

3622

i2c_put_adapter(hdmi->ddc);

drivers/gpu/drm/bridge/tc358767.c

1729

return drm_edid_read_ddc(connector, &tc->aux.ddc);

drivers/gpu/drm/bridge/ti-sn65dsi86.c

1239

return drm_edid_read_ddc(connector, &pdata->aux.ddc);

drivers/gpu/drm/bridge/ti-tfp410.c

152

dvi->bridge.next_bridge->ddc);

drivers/gpu/drm/display/drm_bridge_connector.c

790

struct i2c_adapter *ddc = NULL;

drivers/gpu/drm/display/drm_bridge_connector.c

940

if (bridge->ddc)

drivers/gpu/drm/display/drm_bridge_connector.c

941

ddc = bridge->ddc;

drivers/gpu/drm/display/drm_bridge_connector.c

978

connector_type, ddc,

drivers/gpu/drm/display/drm_bridge_connector.c

986

connector_type, ddc);

drivers/gpu/drm/display/drm_dp_aux_bus.c

264

WARN_ON_ONCE(!aux->ddc.algo);

drivers/gpu/drm/display/drm_dp_helper.c

2235

return container_of(i2c, struct drm_dp_aux, ddc);

drivers/gpu/drm/display/drm_dp_helper.c

2363

aux->ddc.algo = &drm_dp_i2c_algo;

drivers/gpu/drm/display/drm_dp_helper.c

2364

aux->ddc.algo_data = aux;

drivers/gpu/drm/display/drm_dp_helper.c

2365

aux->ddc.retries = 3;

drivers/gpu/drm/display/drm_dp_helper.c

2367

aux->ddc.lock_ops = &drm_dp_i2c_lock_ops;

drivers/gpu/drm/display/drm_dp_helper.c

2404

if (!aux->ddc.algo)

drivers/gpu/drm/display/drm_dp_helper.c

2407

aux->ddc.owner = THIS_MODULE;

drivers/gpu/drm/display/drm_dp_helper.c

2408

aux->ddc.dev.parent = aux->dev;

drivers/gpu/drm/display/drm_dp_helper.c

2410

strscpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),

drivers/gpu/drm/display/drm_dp_helper.c

2411

sizeof(aux->ddc.name));

drivers/gpu/drm/display/drm_dp_helper.c

2417

ret = i2c_add_adapter(&aux->ddc);

drivers/gpu/drm/display/drm_dp_helper.c

2434

i2c_del_adapter(&aux->ddc);

drivers/gpu/drm/display/drm_dp_mst_topology.c

2291

&port->aux.ddc);

drivers/gpu/drm/display/drm_dp_mst_topology.c

4334

port->cached_edid = drm_edid_read_ddc(connector, &port->aux.ddc);

drivers/gpu/drm/display/drm_dp_mst_topology.c

4371

drm_edid = drm_edid_read_ddc(connector, &port->aux.ddc);

drivers/gpu/drm/display/drm_dp_mst_topology.c

5973

aux->ddc.algo = &drm_dp_mst_i2c_algo;

drivers/gpu/drm/display/drm_dp_mst_topology.c

5974

aux->ddc.algo_data = aux;

drivers/gpu/drm/display/drm_dp_mst_topology.c

5975

aux->ddc.retries = 3;

drivers/gpu/drm/display/drm_dp_mst_topology.c

5977

aux->ddc.owner = THIS_MODULE;

drivers/gpu/drm/display/drm_dp_mst_topology.c

5979

aux->ddc.dev.parent = parent_dev;

drivers/gpu/drm/display/drm_dp_mst_topology.c

5980

aux->ddc.dev.of_node = parent_dev->of_node;

drivers/gpu/drm/display/drm_dp_mst_topology.c

5982

strscpy(aux->ddc.name, aux->name ? aux->name : dev_name(parent_dev),

drivers/gpu/drm/display/drm_dp_mst_topology.c

5983

sizeof(aux->ddc.name));

drivers/gpu/drm/display/drm_dp_mst_topology.c

5985

return i2c_add_adapter(&aux->ddc);

drivers/gpu/drm/display/drm_dp_mst_topology.c

5994

i2c_del_adapter(&port->aux.ddc);

drivers/gpu/drm/display/drm_scdc_helper.c

159

ret = drm_scdc_readb(connector->ddc, SCDC_SCRAMBLER_STATUS, &status);

drivers/gpu/drm/display/drm_scdc_helper.c

189

ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);

drivers/gpu/drm/display/drm_scdc_helper.c

202

ret = drm_scdc_writeb(connector->ddc, SCDC_TMDS_CONFIG, config);

drivers/gpu/drm/display/drm_scdc_helper.c

249

ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);

drivers/gpu/drm/display/drm_scdc_helper.c

262

ret = drm_scdc_writeb(connector->ddc, SCDC_TMDS_CONFIG, config);

drivers/gpu/drm/drm_connector.c

227

struct i2c_adapter *ddc)

drivers/gpu/drm/drm_connector.c

276

connector->ddc = ddc;

drivers/gpu/drm/drm_connector.c

368

struct i2c_adapter *ddc)

drivers/gpu/drm/drm_connector.c

372

ret = drm_connector_init_only(dev, connector, funcs, connector_type, ddc);

drivers/gpu/drm/drm_connector.c

446

struct i2c_adapter *ddc)

drivers/gpu/drm/drm_connector.c

451

return drm_connector_init_only(dev, connector, funcs, connector_type, ddc);

drivers/gpu/drm/drm_connector.c

483

struct i2c_adapter *ddc)

drivers/gpu/drm/drm_connector.c

488

return drm_connector_init_and_add(dev, connector, funcs, connector_type, ddc);

drivers/gpu/drm/drm_connector.c

525

struct i2c_adapter *ddc)

drivers/gpu/drm/drm_connector.c

532

ret = drm_connector_init_and_add(dev, connector, funcs, connector_type, ddc);

drivers/gpu/drm/drm_connector.c

577

struct i2c_adapter *ddc,

drivers/gpu/drm/drm_connector.c

609

ret = drmm_connector_init(dev, connector, funcs, connector_type, ddc);

drivers/gpu/drm/drm_edid.c

2720

if (drm_WARN_ON(connector->dev, !connector->ddc))

drivers/gpu/drm/drm_edid.c

2723

return drm_edid_read_ddc(connector, connector->ddc);

drivers/gpu/drm/drm_probe_helper.c

1322

struct i2c_adapter *ddc = connector->ddc;

drivers/gpu/drm/drm_probe_helper.c

1324

if (!ddc)

drivers/gpu/drm/drm_probe_helper.c

1327

if (drm_probe_ddc(ddc))

drivers/gpu/drm/drm_sysfs.c

394

if (connector->ddc)

drivers/gpu/drm/drm_sysfs.c

396

&connector->ddc->dev.kobj, "ddc");

drivers/gpu/drm/drm_sysfs.c

403

if (connector->ddc)

drivers/gpu/drm/gma500/cdv_intel_crt.c

197

struct gma_i2c_chan *ddc_bus = to_gma_i2c_chan(connector->ddc);

drivers/gpu/drm/gma500/cdv_intel_crt.c

206

return psb_intel_ddc_get_modes(connector, connector->ddc);

drivers/gpu/drm/gma500/cdv_intel_hdmi.c

135

edid = drm_get_edid(connector, connector->ddc);

drivers/gpu/drm/gma500/cdv_intel_hdmi.c

216

edid = drm_get_edid(connector, connector->ddc);

drivers/gpu/drm/gma500/cdv_intel_hdmi.c

247

struct gma_i2c_chan *ddc_bus = to_gma_i2c_chan(connector->ddc);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

307

ret = psb_intel_ddc_get_modes(connector, connector->ddc);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

330

gma_i2c_destroy(to_gma_i2c_chan(connector->ddc));

drivers/gpu/drm/gma500/oaktrail_lvds.c

380

connector->ddc = i2c_adap;

drivers/gpu/drm/gma500/oaktrail_lvds.c

424

gma_i2c_destroy(to_gma_i2c_chan(connector->ddc));

drivers/gpu/drm/gma500/psb_intel_lvds.c

500

ret = psb_intel_ddc_get_modes(connector, connector->ddc);

drivers/gpu/drm/gma500/psb_intel_lvds.c

521

struct gma_i2c_chan *ddc_bus = to_gma_i2c_chan(connector->ddc);

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1236

return drm_get_edid(connector, &sdvo->ddc);

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1259

u8 ddc, saved_ddc = psb_intel_sdvo->ddc_bus;

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1265

for (ddc = psb_intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1266

psb_intel_sdvo->ddc_bus = ddc;

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1793

i2c_del_adapter(&psb_intel_sdvo->ddc);

drivers/gpu/drm/gma500/psb_intel_sdvo.c

2429

sdvo->ddc.owner = THIS_MODULE;

drivers/gpu/drm/gma500/psb_intel_sdvo.c

2430

snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");

drivers/gpu/drm/gma500/psb_intel_sdvo.c

2431

sdvo->ddc.dev.parent = dev->dev;

drivers/gpu/drm/gma500/psb_intel_sdvo.c

2432

sdvo->ddc.algo_data = sdvo;

drivers/gpu/drm/gma500/psb_intel_sdvo.c

2433

sdvo->ddc.algo = &psb_intel_sdvo_ddc_proxy;

drivers/gpu/drm/gma500/psb_intel_sdvo.c

2435

return i2c_add_adapter(&sdvo->ddc) == 0;

drivers/gpu/drm/gma500/psb_intel_sdvo.c

2523

i2c_del_adapter(&psb_intel_sdvo->ddc);

drivers/gpu/drm/gma500/psb_intel_sdvo.c

76

struct i2c_adapter ddc;

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c

232

DRM_MODE_CONNECTOR_DisplayPort, &dp->aux.ddc);

drivers/gpu/drm/i915/display/intel_connector.c

232

struct i2c_adapter *ddc)

drivers/gpu/drm/i915/display/intel_connector.c

237

drm_edid = drm_edid_read_ddc(connector, ddc);

drivers/gpu/drm/i915/display/intel_connector.h

28

int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *ddc);

drivers/gpu/drm/i915/display/intel_crt.c

627

struct i2c_adapter *ddc)

drivers/gpu/drm/i915/display/intel_crt.c

631

drm_edid = drm_edid_read_ddc(connector, ddc);

drivers/gpu/drm/i915/display/intel_crt.c

633

if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) {

drivers/gpu/drm/i915/display/intel_crt.c

636

intel_gmbus_force_bit(ddc, true);

drivers/gpu/drm/i915/display/intel_crt.c

637

drm_edid = drm_edid_read_ddc(connector, ddc);

drivers/gpu/drm/i915/display/intel_crt.c

638

intel_gmbus_force_bit(ddc, false);

drivers/gpu/drm/i915/display/intel_crt.c

646

struct i2c_adapter *ddc)

drivers/gpu/drm/i915/display/intel_crt.c

651

drm_edid = intel_crt_get_edid(connector, ddc);

drivers/gpu/drm/i915/display/intel_crt.c

668

drm_edid = intel_crt_get_edid(connector, connector->ddc);

drivers/gpu/drm/i915/display/intel_crt.c

940

struct i2c_adapter *ddc;

drivers/gpu/drm/i915/display/intel_crt.c

948

ret = intel_crt_ddc_get_modes(connector, connector->ddc);

drivers/gpu/drm/i915/display/intel_crt.c

953

ddc = intel_gmbus_get_adapter(display, GMBUS_PIN_DPB);

drivers/gpu/drm/i915/display/intel_crt.c

954

ret = intel_crt_ddc_get_modes(connector, ddc);

drivers/gpu/drm/i915/display/intel_ddi.c

4750

struct i2c_adapter *ddc = connector->base.ddc;

drivers/gpu/drm/i915/display/intel_ddi.c

4791

ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config);

drivers/gpu/drm/i915/display/intel_dp.c

5795

if (drm_probe_ddc(&intel_dp->aux.ddc))

drivers/gpu/drm/i915/display/intel_dp.c

5895

return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);

drivers/gpu/drm/i915/display/intel_dp.c

6845

drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc);

drivers/gpu/drm/i915/display/intel_dp.c

6964

type, &intel_dp->aux.ddc);

drivers/gpu/drm/i915/display/intel_dvo.c

353

num_modes = intel_ddc_get_modes(&connector->base, connector->base.ddc);

drivers/gpu/drm/i915/display/intel_hdmi.c

1301

struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;

drivers/gpu/drm/i915/display/intel_hdmi.c

1310

hdmi->dp_dual_mode.type, ddc, enable);

drivers/gpu/drm/i915/display/intel_hdmi.c

1317

struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;

drivers/gpu/drm/i915/display/intel_hdmi.c

1334

ret = i2c_transfer(ddc, msgs, ARRAY_SIZE(msgs));

drivers/gpu/drm/i915/display/intel_hdmi.c

1344

struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;

drivers/gpu/drm/i915/display/intel_hdmi.c

1361

ret = i2c_transfer(ddc, &msg, 1);

drivers/gpu/drm/i915/display/intel_hdmi.c

1377

struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;

drivers/gpu/drm/i915/display/intel_hdmi.c

1388

ret = intel_gmbus_output_aksv(ddc);

drivers/gpu/drm/i915/display/intel_hdmi.c

2468

struct i2c_adapter *ddc = connector->base.ddc;

drivers/gpu/drm/i915/display/intel_hdmi.c

2471

type = drm_dp_dual_mode_detect(display->drm, ddc);

drivers/gpu/drm/i915/display/intel_hdmi.c

2498

drm_dp_dual_mode_max_tmds_clock(display->drm, type, ddc);

drivers/gpu/drm/i915/display/intel_hdmi.c

2520

struct i2c_adapter *ddc = connector->base.ddc;

drivers/gpu/drm/i915/display/intel_hdmi.c

2527

drm_edid = drm_edid_read_ddc(&connector->base, ddc);

drivers/gpu/drm/i915/display/intel_hdmi.c

2529

if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) {

drivers/gpu/drm/i915/display/intel_hdmi.c

2532

intel_gmbus_force_bit(ddc, true);

drivers/gpu/drm/i915/display/intel_hdmi.c

2533

drm_edid = drm_edid_read_ddc(&connector->base, ddc);

drivers/gpu/drm/i915/display/intel_hdmi.c

2534

intel_gmbus_force_bit(ddc, false);

drivers/gpu/drm/i915/display/intel_hdmi.c

2973

if (connector && connector->base.ddc == intel_gmbus_get_adapter(display, ddc_pin))

drivers/gpu/drm/i915/display/intel_lspcon.c

159

struct i2c_adapter *ddc = &intel_dp->aux.ddc;

drivers/gpu/drm/i915/display/intel_lspcon.c

161

if (drm_lspcon_get_mode(intel_dp->aux.drm_dev, ddc, &current_mode)) {

drivers/gpu/drm/i915/display/intel_lspcon.c

218

struct i2c_adapter *ddc = &intel_dp->aux.ddc;

drivers/gpu/drm/i915/display/intel_lspcon.c

220

err = drm_lspcon_get_mode(intel_dp->aux.drm_dev, ddc, &current_mode);

drivers/gpu/drm/i915/display/intel_lspcon.c

231

err = drm_lspcon_set_mode(intel_dp->aux.drm_dev, ddc, mode,

drivers/gpu/drm/i915/display/intel_lspcon.c

265

struct i2c_adapter *ddc = &intel_dp->aux.ddc;

drivers/gpu/drm/i915/display/intel_lspcon.c

278

adaptor_type = drm_dp_dual_mode_detect(intel_dp->aux.drm_dev, ddc);

drivers/gpu/drm/i915/display/intel_lvds.c

960

drm_edid = drm_edid_read_switcheroo(&connector->base, connector->base.ddc);

drivers/gpu/drm/i915/display/intel_lvds.c

962

drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc);

drivers/gpu/drm/i915/display/intel_sdvo.c

101

struct intel_sdvo_ddc ddc[3];

drivers/gpu/drm/i915/display/intel_sdvo.c

2073

struct i2c_adapter *ddc = connector->ddc;

drivers/gpu/drm/i915/display/intel_sdvo.c

2075

if (!ddc)

drivers/gpu/drm/i915/display/intel_sdvo.c

2078

return drm_edid_read_ddc(connector, ddc);

drivers/gpu/drm/i915/display/intel_sdvo.c

2086

struct i2c_adapter *ddc;

drivers/gpu/drm/i915/display/intel_sdvo.c

2088

ddc = intel_gmbus_get_adapter(display, display->vbt.crt_ddc_pin);

drivers/gpu/drm/i915/display/intel_sdvo.c

2089

if (!ddc)

drivers/gpu/drm/i915/display/intel_sdvo.c

2092

return drm_edid_read_ddc(connector, ddc);

drivers/gpu/drm/i915/display/intel_sdvo.c

2551

for (i = 0; i < ARRAY_SIZE(sdvo->ddc); i++) {

drivers/gpu/drm/i915/display/intel_sdvo.c

2552

if (sdvo->ddc[i].ddc_bus)

drivers/gpu/drm/i915/display/intel_sdvo.c

2553

i2c_del_adapter(&sdvo->ddc[i].ddc);

drivers/gpu/drm/i915/display/intel_sdvo.c

2635

return &sdvo->ddc[ddc_bus - 1];

drivers/gpu/drm/i915/display/intel_sdvo.c

2723

intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc,

drivers/gpu/drm/i915/display/intel_sdvo.c

2731

struct intel_sdvo_ddc *ddc = NULL;

drivers/gpu/drm/i915/display/intel_sdvo.c

2735

ddc = intel_sdvo_select_ddc_bus(encoder, connector);

drivers/gpu/drm/i915/display/intel_sdvo.c

2741

ddc ? &ddc->ddc : NULL);

drivers/gpu/drm/i915/display/intel_sdvo.c

2754

if (ddc)

drivers/gpu/drm/i915/display/intel_sdvo.c

2757

ddc->ddc.name);

drivers/gpu/drm/i915/display/intel_sdvo.c

2961

intel_ddc_get_modes(connector, connector->ddc);

drivers/gpu/drm/i915/display/intel_sdvo.c

3289

struct intel_sdvo_ddc *ddc = adapter->algo_data;

drivers/gpu/drm/i915/display/intel_sdvo.c

3290

struct intel_sdvo *sdvo = ddc->sdvo;

drivers/gpu/drm/i915/display/intel_sdvo.c

3292

if (!__intel_sdvo_set_control_bus_switch(sdvo, 1 << ddc->ddc_bus))

drivers/gpu/drm/i915/display/intel_sdvo.c

3300

struct intel_sdvo_ddc *ddc = adapter->algo_data;

drivers/gpu/drm/i915/display/intel_sdvo.c

3301

struct intel_sdvo *sdvo = ddc->sdvo;

drivers/gpu/drm/i915/display/intel_sdvo.c

3314

struct intel_sdvo_ddc *ddc = adapter->algo_data;

drivers/gpu/drm/i915/display/intel_sdvo.c

3315

struct intel_sdvo *sdvo = ddc->sdvo;

drivers/gpu/drm/i915/display/intel_sdvo.c

3323

struct intel_sdvo_ddc *ddc = adapter->algo_data;

drivers/gpu/drm/i915/display/intel_sdvo.c

3324

struct intel_sdvo *sdvo = ddc->sdvo;

drivers/gpu/drm/i915/display/intel_sdvo.c

3332

struct intel_sdvo_ddc *ddc = adapter->algo_data;

drivers/gpu/drm/i915/display/intel_sdvo.c

3333

struct intel_sdvo *sdvo = ddc->sdvo;

drivers/gpu/drm/i915/display/intel_sdvo.c

3345

intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc,

drivers/gpu/drm/i915/display/intel_sdvo.c

3351

ddc->sdvo = sdvo;

drivers/gpu/drm/i915/display/intel_sdvo.c

3352

ddc->ddc_bus = ddc_bus;

drivers/gpu/drm/i915/display/intel_sdvo.c

3354

ddc->ddc.owner = THIS_MODULE;

drivers/gpu/drm/i915/display/intel_sdvo.c

3355

snprintf(ddc->ddc.name, I2C_NAME_SIZE, "SDVO %c DDC%d",

drivers/gpu/drm/i915/display/intel_sdvo.c

3357

ddc->ddc.dev.parent = &pdev->dev;

drivers/gpu/drm/i915/display/intel_sdvo.c

3358

ddc->ddc.algo_data = ddc;

drivers/gpu/drm/i915/display/intel_sdvo.c

3359

ddc->ddc.algo = &intel_sdvo_ddc_proxy;

drivers/gpu/drm/i915/display/intel_sdvo.c

3360

ddc->ddc.lock_ops = &proxy_lock_ops;

drivers/gpu/drm/i915/display/intel_sdvo.c

3362

return i2c_add_adapter(&ddc->ddc);

drivers/gpu/drm/i915/display/intel_sdvo.c

3444

for (i = 0; i < ARRAY_SIZE(intel_sdvo->ddc); i++) {

drivers/gpu/drm/i915/display/intel_sdvo.c

3447

ret = intel_sdvo_init_ddc_proxy(&intel_sdvo->ddc[i],

drivers/gpu/drm/i915/display/intel_sdvo.c

90

struct i2c_adapter ddc;

drivers/gpu/drm/imx/ipuv3/imx-tve.c

117

struct i2c_adapter *ddc;

drivers/gpu/drm/imx/ipuv3/imx-tve.c

207

if (!tve->ddc)

drivers/gpu/drm/imx/ipuv3/imx-tve.c

210

drm_edid = drm_edid_read_ddc(connector, tve->ddc);

drivers/gpu/drm/imx/ipuv3/imx-tve.c

520

DRM_MODE_CONNECTOR_VGA, tve->ddc);

drivers/gpu/drm/imx/ipuv3/imx-tve.c

557

tve->ddc = of_find_i2c_adapter_by_node(ddc_node);

drivers/gpu/drm/imx/ipuv3/imx-tve.c

559

if (tve->ddc) {

drivers/gpu/drm/imx/ipuv3/imx-tve.c

561

&tve->ddc->dev);

drivers/gpu/drm/loongson/lsdc_drv.c

83

struct i2c_adapter *ddc = NULL;

drivers/gpu/drm/loongson/lsdc_drv.c

87

ddc = &dispipe->li2c->adapter;

drivers/gpu/drm/loongson/lsdc_drv.c

89

ret = funcs->output_init(ddev, dispipe, ddc, i);

drivers/gpu/drm/loongson/lsdc_drv.h

211

struct i2c_adapter *ddc,

drivers/gpu/drm/loongson/lsdc_output.h

13

struct i2c_adapter *ddc,

drivers/gpu/drm/loongson/lsdc_output.h

18

struct i2c_adapter *ddc,

drivers/gpu/drm/loongson/lsdc_output_7a1000.c

144

struct i2c_adapter *ddc,

drivers/gpu/drm/loongson/lsdc_output_7a1000.c

161

DRM_MODE_CONNECTOR_DPI, ddc);

drivers/gpu/drm/loongson/lsdc_output_7a1000.c

46

if (conn->ddc) {

drivers/gpu/drm/loongson/lsdc_output_7a1000.c

82

struct i2c_adapter *ddc = connector->ddc;

drivers/gpu/drm/loongson/lsdc_output_7a1000.c

84

if (ddc) {

drivers/gpu/drm/loongson/lsdc_output_7a1000.c

85

if (drm_probe_ddc(ddc))

drivers/gpu/drm/loongson/lsdc_output_7a2000.c

177

if (connector->ddc) {

drivers/gpu/drm/loongson/lsdc_output_7a2000.c

178

if (drm_probe_ddc(connector->ddc))

drivers/gpu/drm/loongson/lsdc_output_7a2000.c

50

if (connector->ddc) {

drivers/gpu/drm/loongson/lsdc_output_7a2000.c

516

struct i2c_adapter *ddc,

drivers/gpu/drm/loongson/lsdc_output_7a2000.c

535

DRM_MODE_CONNECTOR_HDMIA, ddc);

drivers/gpu/drm/mediatek/mtk_dp.c

2185

drm_edid = drm_edid_read_ddc(connector, &mtk_dp->aux.ddc);

drivers/gpu/drm/mediatek/mtk_hdmi_common.c

443

hdmi->bridge.ddc = hdmi->ddc_adpt;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

101

static void ddcm_trigger_mode(struct mtk_hdmi_ddc *ddc, int mode)

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

105

sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_SIF_MODE_MASK,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

107

sif_set_bit(ddc, DDC_DDCMCTL1, DDCM_TRI);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

108

readl_poll_timeout(ddc->regs + DDC_DDCMCTL1, val,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

112

static int mtk_hdmi_ddc_read_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg)

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

114

struct device *dev = ddc->adap.dev.parent;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

120

ddcm_trigger_mode(ddc, DDCM_START);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

121

sif_write_mask(ddc, DDC_DDCMD0, 0xff, 0, (msg->addr << 1) | 0x01);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

122

sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

124

ddcm_trigger_mode(ddc, DDCM_WRITE_DATA);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

125

ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

146

sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

148

ddcm_trigger_mode(ddc, (ack_final == 1) ?

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

152

ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

175

msg->buf[index + i - 1] = sif_read_mask(ddc, offset,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

187

static int mtk_hdmi_ddc_write_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg)

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

189

struct device *dev = ddc->adap.dev.parent;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

192

ddcm_trigger_mode(ddc, DDCM_START);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

193

sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA0, 0, msg->addr << 1);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

194

sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA1, 8, msg->buf[0]);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

195

sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

197

ddcm_trigger_mode(ddc, DDCM_WRITE_DATA);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

199

ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

213

struct mtk_hdmi_ddc *ddc = adapter->algo_data;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

218

if (!ddc) {

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

223

sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SCL_STRECH);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

224

sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SM0EN);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

225

sif_clr_bit(ddc, DDC_DDCMCTL0, DDCM_ODRAIN);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

227

if (sif_bit_is_set(ddc, DDC_DDCMCTL1, DDCM_TRI)) {

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

232

sif_write_mask(ddc, DDC_DDCMCTL0, DDCM_CLK_DIV_MASK,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

242

ret = mtk_hdmi_ddc_read_msg(ddc, msg);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

244

ret = mtk_hdmi_ddc_write_msg(ddc, msg);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

249

ddcm_trigger_mode(ddc, DDCM_STOP);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

254

ddcm_trigger_mode(ddc, DDCM_STOP);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

272

struct mtk_hdmi_ddc *ddc;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

276

ddc = devm_kzalloc(dev, sizeof(struct mtk_hdmi_ddc), GFP_KERNEL);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

277

if (!ddc)

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

280

ddc->clk = devm_clk_get(dev, "ddc-i2c");

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

281

if (IS_ERR(ddc->clk))

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

282

return dev_err_probe(dev, PTR_ERR(ddc->clk),

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

285

ddc->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

286

if (IS_ERR(ddc->regs))

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

287

return PTR_ERR(ddc->regs);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

289

ret = clk_prepare_enable(ddc->clk);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

293

strscpy(ddc->adap.name, "mediatek-hdmi-ddc", sizeof(ddc->adap.name));

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

294

ddc->adap.owner = THIS_MODULE;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

295

ddc->adap.algo = &mtk_hdmi_ddc_algorithm;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

296

ddc->adap.retries = 3;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

297

ddc->adap.dev.of_node = dev->of_node;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

298

ddc->adap.algo_data = ddc;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

299

ddc->adap.dev.parent = &pdev->dev;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

301

ret = i2c_add_adapter(&ddc->adap);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

303

clk_disable_unprepare(ddc->clk);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

307

platform_set_drvdata(pdev, ddc);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

309

dev_dbg(dev, "ddc->adap: %p\n", &ddc->adap);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

310

dev_dbg(dev, "ddc->clk: %p\n", ddc->clk);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

319

struct mtk_hdmi_ddc *ddc = platform_get_drvdata(pdev);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

321

i2c_del_adapter(&ddc->adap);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

322

clk_disable_unprepare(ddc->clk);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

64

static inline void sif_set_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

67

writel(readl(ddc->regs + offset) | val, ddc->regs + offset);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

70

static inline void sif_clr_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

73

writel(readl(ddc->regs + offset) & ~val, ddc->regs + offset);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

76

static inline bool sif_bit_is_set(struct mtk_hdmi_ddc *ddc, unsigned int offset,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

79

return (readl(ddc->regs + offset) & val) == val;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

82

static inline void sif_write_mask(struct mtk_hdmi_ddc *ddc, unsigned int offset,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

88

tmp = readl(ddc->regs + offset);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

91

writel(tmp, ddc->regs + offset);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

94

static inline unsigned int sif_read_mask(struct mtk_hdmi_ddc *ddc,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c

98

return (readl(ddc->regs + offset) & mask) >> shift;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

101

regmap_write(ddc->regs, DDC_CTRL,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

108

ret = regmap_read_poll_timeout(ddc->regs, HPD_DDC_STATUS, val,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

111

dev_err(ddc->dev, "DDC I2C write timeout\n");

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

114

regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

121

ret = mtk_ddc_check_and_rise_low_bus(ddc);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

123

dev_err(ddc->dev, "Error during write operation: No ACK\n");

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

130

static int mtk_ddcm_read_hdmi(struct mtk_hdmi_ddc *ddc, u16 uc_dev,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

138

mtk_ddc_check_and_rise_low_bus(ddc);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

140

regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

160

regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

171

regmap_update_bits(ddc->regs, SCDC_CTRL, SCDC_DDC_SEGMENT,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

174

regmap_write(ddc->regs, DDC_CTRL,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

187

regmap_write(ddc->regs, DDC_CTRL,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

195

ret = regmap_read_poll_timeout(ddc->regs, HPD_DDC_STATUS, val,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

199

dev_err(ddc->dev, "Timeout waiting for DDC I2C\n");

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

202

regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

208

ret = mtk_ddc_check_and_rise_low_bus(ddc);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

210

dev_err(ddc->dev, "Error during read operation: No ACK\n");

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

217

regmap_write(ddc->regs, SI2C_CTRL,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

221

regmap_read(ddc->regs, HPD_DDC_STATUS, &val);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

224

regmap_write(ddc->regs, SI2C_CTRL,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

233

regmap_read(ddc->regs, HPD_DDC_CTRL, &val);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

241

dev_warn(ddc->dev, "Invalid read data count %u\n", uc_read_count);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

246

static int mtk_hdmi_fg_ddc_data_read(struct mtk_hdmi_ddc *ddc, u16 b_dev,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

253

dev_err(ddc->dev, "Invalid DDCM read request\n");

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

261

regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

263

read_data_cnt = mtk_ddcm_read_hdmi(ddc, b_dev, data_addr, pr_data, req_data_cnt);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

273

static int mtk_hdmi_ddc_fg_data_write(struct mtk_hdmi_ddc *ddc, u16 b_dev,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

276

regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

278

return mtk_ddcm_write_hdmi(ddc, b_dev, data_addr, data_cnt, pr_data);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

283

struct mtk_hdmi_ddc *ddc;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

287

ddc = adapter->algo_data;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

293

dev_err(ddc->dev, "No message buffer\n");

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

304

ret = mtk_hdmi_fg_ddc_data_read(ddc, msg->addr, offset,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

314

ret = mtk_hdmi_ddc_fg_data_write(ddc, msg->addr, msg->buf[0],

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

346

struct mtk_hdmi_ddc *ddc;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

349

ddc = devm_kzalloc(dev, sizeof(*ddc), GFP_KERNEL);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

350

if (!ddc)

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

353

ddc->dev = dev;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

354

ddc->regs = device_node_to_regmap(dev->parent->of_node);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

355

if (IS_ERR_OR_NULL(ddc->regs))

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

357

IS_ERR(ddc->regs) ? PTR_ERR(ddc->regs) : -EINVAL,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

360

ddc->clk = devm_clk_get_enabled(dev, NULL);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

361

if (IS_ERR(ddc->clk))

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

362

return dev_err_probe(dev, PTR_ERR(ddc->clk), "Cannot get DDC clock\n");

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

364

strscpy(ddc->adap.name, "mediatek-hdmi-ddc-v2", sizeof(ddc->adap.name));

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

365

ddc->adap.owner = THIS_MODULE;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

366

ddc->adap.algo = &mtk_hdmi_ddc_v2_algorithm;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

367

ddc->adap.retries = 3;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

368

ddc->adap.dev.of_node = dev->of_node;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

369

ddc->adap.algo_data = ddc;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

370

ddc->adap.dev.parent = &pdev->dev;

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

378

ret = devm_i2c_add_adapter(dev, &ddc->adap);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

382

platform_set_drvdata(pdev, ddc);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

44

static int mtk_ddc_check_and_rise_low_bus(struct mtk_hdmi_ddc *ddc)

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

48

regmap_read(ddc->regs, HDCP2X_DDCM_STATUS, &val);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

50

regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

58

regmap_read(ddc->regs, DDC_CTRL, &ddc_ctrl);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

59

regmap_read(ddc->regs, HPD_DDC_CTRL, &hpd_ddc_ctrl);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

60

regmap_read(ddc->regs, HPD_DDC_STATUS, &hpd_ddc_status);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

69

static int mtk_ddcm_write_hdmi(struct mtk_hdmi_ddc *ddc, u16 addr_id,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

79

dev_err(ddc->dev, "Invalid DDCM write request\n");

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

84

mtk_ddc_check_and_rise_low_bus(ddc);

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

86

regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT,

drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

95

regmap_write(ddc->regs, SI2C_CTRL,

drivers/gpu/drm/mgag200/mgag200_ddc.c

103

struct mgag200_ddc *ddc = i2c_get_adapdata(adapter);

drivers/gpu/drm/mgag200/mgag200_ddc.c

104

struct mga_device *mdev = ddc->mdev;

drivers/gpu/drm/mgag200/mgag200_ddc.c

117

struct mgag200_ddc *ddc = i2c_get_adapdata(adapter);

drivers/gpu/drm/mgag200/mgag200_ddc.c

118

struct mga_device *mdev = ddc->mdev;

drivers/gpu/drm/mgag200/mgag200_ddc.c

125

struct mgag200_ddc *ddc = res;

drivers/gpu/drm/mgag200/mgag200_ddc.c

127

i2c_del_adapter(&ddc->adapter);

drivers/gpu/drm/mgag200/mgag200_ddc.c

134

struct mgag200_ddc *ddc;

drivers/gpu/drm/mgag200/mgag200_ddc.c

139

ddc = drmm_kzalloc(dev, sizeof(*ddc), GFP_KERNEL);

drivers/gpu/drm/mgag200/mgag200_ddc.c

140

if (!ddc)

drivers/gpu/drm/mgag200/mgag200_ddc.c

147

ddc->mdev = mdev;

drivers/gpu/drm/mgag200/mgag200_ddc.c

148

ddc->data = BIT(info->i2c.data_bit);

drivers/gpu/drm/mgag200/mgag200_ddc.c

149

ddc->clock = BIT(info->i2c.clock_bit);

drivers/gpu/drm/mgag200/mgag200_ddc.c

151

bit = &ddc->bit;

drivers/gpu/drm/mgag200/mgag200_ddc.c

152

bit->data = ddc;

drivers/gpu/drm/mgag200/mgag200_ddc.c

162

adapter = &ddc->adapter;

drivers/gpu/drm/mgag200/mgag200_ddc.c

167

i2c_set_adapdata(adapter, ddc);

drivers/gpu/drm/mgag200/mgag200_ddc.c

173

ret = drmm_add_action_or_reset(dev, mgag200_ddc_release, ddc);

drivers/gpu/drm/mgag200/mgag200_ddc.c

75

struct mgag200_ddc *ddc = data;

drivers/gpu/drm/mgag200/mgag200_ddc.c

77

mga_i2c_set(ddc->mdev, ddc->data, state);

drivers/gpu/drm/mgag200/mgag200_ddc.c

82

struct mgag200_ddc *ddc = data;

drivers/gpu/drm/mgag200/mgag200_ddc.c

84

mga_i2c_set(ddc->mdev, ddc->clock, state);

drivers/gpu/drm/mgag200/mgag200_ddc.c

89

struct mgag200_ddc *ddc = data;

drivers/gpu/drm/mgag200/mgag200_ddc.c

91

return (mga_i2c_read_gpio(ddc->mdev) & ddc->data) ? 1 : 0;

drivers/gpu/drm/mgag200/mgag200_ddc.c

96

struct mgag200_ddc *ddc = data;

drivers/gpu/drm/mgag200/mgag200_ddc.c

98

return (mga_i2c_read_gpio(ddc->mdev) & ddc->clock) ? 1 : 0;

drivers/gpu/drm/mgag200/mgag200_vga.c

34

struct i2c_adapter *ddc;

drivers/gpu/drm/mgag200/mgag200_vga.c

46

ddc = mgag200_ddc_create(mdev);

drivers/gpu/drm/mgag200/mgag200_vga.c

47

if (IS_ERR(ddc)) {

drivers/gpu/drm/mgag200/mgag200_vga.c

48

ret = PTR_ERR(ddc);

drivers/gpu/drm/mgag200/mgag200_vga.c

56

DRM_MODE_CONNECTOR_VGA, ddc);

drivers/gpu/drm/mgag200/mgag200_vga_bmc.c

116

struct i2c_adapter *ddc;

drivers/gpu/drm/mgag200/mgag200_vga_bmc.c

130

ddc = mgag200_ddc_create(mdev);

drivers/gpu/drm/mgag200/mgag200_vga_bmc.c

131

if (IS_ERR(ddc)) {

drivers/gpu/drm/mgag200/mgag200_vga_bmc.c

132

ret = PTR_ERR(ddc);

drivers/gpu/drm/mgag200/mgag200_vga_bmc.c

140

DRM_MODE_CONNECTOR_VGA, ddc);

drivers/gpu/drm/msm/dp/dp_panel.c

279

msm_dp_panel->drm_edid = drm_edid_read_ddc(connector, &panel->aux->ddc);

drivers/gpu/drm/msm/hdmi/hdmi_bridge.c

504

bridge->ddc = hdmi->i2c;

drivers/gpu/drm/nouveau/dispnv50/disp.c

1933

nv_encoder->i2c = &nv_connector->aux.ddc;

drivers/gpu/drm/nouveau/dispnv50/disp.c

1944

if (nv_encoder->outp.info.ddc != NVIF_OUTP_DDC_INVALID) {

drivers/gpu/drm/nouveau/dispnv50/disp.c

2060

struct i2c_adapter *ddc;

drivers/gpu/drm/nouveau/dispnv50/disp.c

2067

bus = nvkm_i2c_bus_find(i2c, nv_encoder->outp.info.ddc);

drivers/gpu/drm/nouveau/dispnv50/disp.c

2068

ddc = bus ? &bus->i2c : NULL;

drivers/gpu/drm/nouveau/dispnv50/disp.c

2073

ddc = aux ? &aux->i2c : NULL;

drivers/gpu/drm/nouveau/dispnv50/disp.c

2080

nv_encoder->i2c = ddc;

drivers/gpu/drm/nouveau/dispnv50/disp.c

2955

outp->dcb->i2c_index = outp->outp.info.ddc;

drivers/gpu/drm/nouveau/include/nvif/if0012.h

21

__u8 ddc;

drivers/gpu/drm/nouveau/include/nvif/outp.h

29

u8 ddc;

drivers/gpu/drm/nouveau/nvif/outp.c

551

outp->info.ddc = args.ddc;

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

651

args->v0.ddc = NVKM_I2C_BUS_EXT(outp->info.extdev);

drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c

653

args->v0.ddc = outp->info.i2c_index;

drivers/gpu/drm/panel/panel-edp.c

234

struct i2c_adapter *ddc;

drivers/gpu/drm/panel/panel-edp.c

591

if (p->ddc) {

drivers/gpu/drm/panel/panel-edp.c

595

p->drm_edid = drm_edid_read_ddc(connector, p->ddc);

drivers/gpu/drm/panel/panel-edp.c

795

base_block = drm_edid_read_base_block(panel->ddc);

drivers/gpu/drm/panel/panel-edp.c

839

struct device_node *ddc;

drivers/gpu/drm/panel/panel-edp.c

874

ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);

drivers/gpu/drm/panel/panel-edp.c

875

if (ddc) {

drivers/gpu/drm/panel/panel-edp.c

876

panel->ddc = of_find_i2c_adapter_by_node(ddc);

drivers/gpu/drm/panel/panel-edp.c

877

of_node_put(ddc);

drivers/gpu/drm/panel/panel-edp.c

879

if (!panel->ddc)

drivers/gpu/drm/panel/panel-edp.c

882

panel->ddc = &aux->ddc;

drivers/gpu/drm/panel/panel-edp.c

940

if (panel->ddc && (!panel->aux || panel->ddc != &panel->aux->ddc))

drivers/gpu/drm/panel/panel-edp.c

941

put_device(&panel->ddc->dev);

drivers/gpu/drm/panel/panel-edp.c

985

if (panel->ddc && (!panel->aux || panel->ddc != &panel->aux->ddc))

drivers/gpu/drm/panel/panel-edp.c

986

put_device(&panel->ddc->dev);

drivers/gpu/drm/panel/panel-samsung-atna33xc20.c

233

p->drm_edid = drm_edid_read_ddc(connector, &aux_ep->aux->ddc);

drivers/gpu/drm/panel/panel-simple.c

156

struct i2c_adapter *ddc;

drivers/gpu/drm/panel/panel-simple.c

382

if (p->ddc) {

drivers/gpu/drm/panel/panel-simple.c

386

p->drm_edid = drm_edid_read_ddc(connector, p->ddc);

drivers/gpu/drm/panel/panel-simple.c

617

struct device_node *ddc;

drivers/gpu/drm/panel/panel-simple.c

702

ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);

drivers/gpu/drm/panel/panel-simple.c

703

if (ddc) {

drivers/gpu/drm/panel/panel-simple.c

704

panel->ddc = of_find_i2c_adapter_by_node(ddc);

drivers/gpu/drm/panel/panel-simple.c

705

of_node_put(ddc);

drivers/gpu/drm/panel/panel-simple.c

707

if (!panel->ddc)

drivers/gpu/drm/panel/panel-simple.c

748

if (panel->ddc)

drivers/gpu/drm/panel/panel-simple.c

749

put_device(&panel->ddc->dev);

drivers/gpu/drm/panel/panel-simple.c

793

if (panel->ddc)

drivers/gpu/drm/panel/panel-simple.c

794

put_device(&panel->ddc->dev);

drivers/gpu/drm/radeon/radeon_combios.c

400

enum radeon_combios_ddc ddc,

drivers/gpu/drm/radeon/radeon_combios.c

429

switch (ddc) {

drivers/gpu/drm/radeon/radeon_combios.c

454

ddc = DDC_DVI;

drivers/gpu/drm/radeon/radeon_combios.c

463

ddc = DDC_DVI;

drivers/gpu/drm/radeon/radeon_combios.c

470

ddc = DDC_MONID;

drivers/gpu/drm/radeon/radeon_combios.c

616

i2c.i2c_id = ddc;

drivers/gpu/drm/radeon/radeon_connectors.c

1839

struct i2c_adapter *ddc = NULL;

drivers/gpu/drm/radeon/radeon_connectors.c

1919

ddc = &radeon_connector->ddc_bus->adapter;

drivers/gpu/drm/radeon/radeon_connectors.c

1931

ddc);

drivers/gpu/drm/radeon/radeon_connectors.c

1956

ddc);

drivers/gpu/drm/radeon/radeon_connectors.c

2006

ddc);

drivers/gpu/drm/radeon/radeon_connectors.c

2025

ddc = &radeon_connector->ddc_bus->adapter;

drivers/gpu/drm/radeon/radeon_connectors.c

2030

ddc);

drivers/gpu/drm/radeon/radeon_connectors.c

2055

ddc = &radeon_connector->ddc_bus->adapter;

drivers/gpu/drm/radeon/radeon_connectors.c

2060

ddc);

drivers/gpu/drm/radeon/radeon_connectors.c

2091

ddc = &radeon_connector->ddc_bus->adapter;

drivers/gpu/drm/radeon/radeon_connectors.c

2096

ddc);

drivers/gpu/drm/radeon/radeon_connectors.c

2153

ddc = &radeon_connector->ddc_bus->adapter;

drivers/gpu/drm/radeon/radeon_connectors.c

2158

ddc);

drivers/gpu/drm/radeon/radeon_connectors.c

2207

ddc = &radeon_connector->ddc_bus->adapter;

drivers/gpu/drm/radeon/radeon_connectors.c

2215

ddc);

drivers/gpu/drm/radeon/radeon_connectors.c

2262

ddc = &radeon_connector->ddc_bus->adapter;

drivers/gpu/drm/radeon/radeon_connectors.c

2270

ddc);

drivers/gpu/drm/radeon/radeon_connectors.c

2285

ddc);

drivers/gpu/drm/radeon/radeon_connectors.c

2310

ddc = &radeon_connector->ddc_bus->adapter;

drivers/gpu/drm/radeon/radeon_connectors.c

2315

ddc);

drivers/gpu/drm/radeon/radeon_connectors.c

2360

struct i2c_adapter *ddc = NULL;

drivers/gpu/drm/radeon/radeon_connectors.c

2400

ddc = &radeon_connector->ddc_bus->adapter;

drivers/gpu/drm/radeon/radeon_connectors.c

2405

ddc);

drivers/gpu/drm/radeon/radeon_connectors.c

2422

ddc = &radeon_connector->ddc_bus->adapter;

drivers/gpu/drm/radeon/radeon_connectors.c

2427

ddc);

drivers/gpu/drm/radeon/radeon_connectors.c

2445

ddc = &radeon_connector->ddc_bus->adapter;

drivers/gpu/drm/radeon/radeon_connectors.c

2450

ddc);

drivers/gpu/drm/radeon/radeon_connectors.c

2471

ddc);

drivers/gpu/drm/radeon/radeon_connectors.c

2498

ddc = &radeon_connector->ddc_bus->adapter;

drivers/gpu/drm/radeon/radeon_connectors.c

2503

ddc);

drivers/gpu/drm/radeon/radeon_connectors.c

275

&radeon_connector->ddc_bus->aux.ddc);

drivers/gpu/drm/radeon/radeon_connectors.c

284

&radeon_connector->ddc_bus->aux.ddc);

drivers/gpu/drm/radeon/radeon_i2c.c

62

ret = i2c_transfer(&radeon_connector->ddc_bus->aux.ddc, msgs, 2);

drivers/gpu/drm/rockchip/rk3066_hdmi.c

477

drm_edid = drm_edid_read_ddc(connector, bridge->ddc);

drivers/gpu/drm/rockchip/rk3066_hdmi.c

712

hdmi->bridge.ddc = rk3066_hdmi_i2c_adapter(hdmi);

drivers/gpu/drm/rockchip/rk3066_hdmi.c

713

if (IS_ERR(hdmi->bridge.ddc))

drivers/gpu/drm/rockchip/rk3066_hdmi.c

714

return PTR_ERR(hdmi->bridge.ddc);

drivers/gpu/drm/rockchip/rk3066_hdmi.c

716

if (IS_ERR(hdmi->bridge.ddc))

drivers/gpu/drm/rockchip/rk3066_hdmi.c

717

return PTR_ERR(hdmi->bridge.ddc);

drivers/gpu/drm/sti/sti_hdmi.c

1381

struct device_node *ddc;

drivers/gpu/drm/sti/sti_hdmi.c

1390

ddc = of_parse_phandle(pdev->dev.of_node, "ddc", 0);

drivers/gpu/drm/sti/sti_hdmi.c

1391

if (ddc) {

drivers/gpu/drm/sti/sti_hdmi.c

1392

hdmi->ddc_adapt = of_get_i2c_adapter_by_node(ddc);

drivers/gpu/drm/sti/sti_hdmi.c

1393

of_node_put(ddc);

drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

113

struct sun4i_ddc *ddc;

drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

120

ddc = devm_kzalloc(hdmi->dev, sizeof(*ddc), GFP_KERNEL);

drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

121

if (!ddc)

drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

124

ddc->reg = devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,

drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

126

if (IS_ERR(ddc->reg))

drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

127

return PTR_ERR(ddc->reg);

drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

134

ddc->hdmi = hdmi;

drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

135

ddc->hw.init = &init;

drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

136

ddc->pre_div = hdmi->variant->ddc_clk_pre_divider;

drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

137

ddc->m_offset = hdmi->variant->ddc_clk_m_offset;

drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

139

hdmi->ddc_clk = devm_clk_register(hdmi->dev, &ddc->hw);

drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

65

struct sun4i_ddc *ddc = hw_to_ddc(hw);

drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

68

ddc->pre_div, ddc->m_offset, NULL, NULL);

drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

76

struct sun4i_ddc *ddc = hw_to_ddc(hw);

drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

80

regmap_field_read(ddc->reg, &reg);

drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

84

return (((parent_rate / ddc->pre_div) / 10) >> n) /

drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

85

(m + ddc->m_offset);

drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

91

struct sun4i_ddc *ddc = hw_to_ddc(hw);

drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

94

sun4i_ddc_calc_divider(rate, parent_rate, ddc->pre_div,

drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

95

ddc->m_offset, &div_m, &div_n);

drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

97

regmap_field_write(ddc->reg,

drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c

233

struct i2c_adapter *ddc;

drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c

244

ddc = of_get_i2c_adapter_by_node(phandle);

drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c

246

if (!ddc)

drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c

249

return ddc;

drivers/gpu/drm/tegra/drm.h

138

struct i2c_adapter *ddc;

drivers/gpu/drm/tegra/hdmi.c

1585

hdmi->output.ddc);

drivers/gpu/drm/tegra/output.c

127

ddc = of_parse_phandle(output->of_node, "nvidia,ddc-i2c-bus", 0);

drivers/gpu/drm/tegra/output.c

128

if (ddc) {

drivers/gpu/drm/tegra/output.c

129

output->ddc = of_get_i2c_adapter_by_node(ddc);

drivers/gpu/drm/tegra/output.c

130

of_node_put(ddc);

drivers/gpu/drm/tegra/output.c

132

if (!output->ddc) {

drivers/gpu/drm/tegra/output.c

188

if (output->ddc)

drivers/gpu/drm/tegra/output.c

189

i2c_put_adapter(output->ddc);

drivers/gpu/drm/tegra/output.c

201

if (output->ddc)

drivers/gpu/drm/tegra/output.c

202

i2c_put_adapter(output->ddc);

drivers/gpu/drm/tegra/output.c

39

else if (output->ddc)

drivers/gpu/drm/tegra/output.c

40

drm_edid = drm_edid_read_ddc(connector, output->ddc);

drivers/gpu/drm/tegra/output.c

99

struct device_node *ddc, *panel;

drivers/gpu/drm/tegra/sor.c

3079

sor->output.ddc);

drivers/gpu/drm/tegra/sor.c

3742

sor->output.ddc = &sor->aux->ddc;

drivers/gpu/drm/tegra/sor.c

3961

sor->output.ddc = NULL;

drivers/gpu/drm/tegra/sor.c

3981

sor->output.ddc = NULL;

drivers/gpu/drm/tests/drm_connector_test.c

101

ret = kunit_add_action_or_reset(test, i2c_del_adapter_wrapper, &priv->ddc);

drivers/gpu/drm/tests/drm_connector_test.c

1014

&priv->ddc,

drivers/gpu/drm/tests/drm_connector_test.c

1055

&priv->ddc,

drivers/gpu/drm/tests/drm_connector_test.c

1091

&priv->ddc,

drivers/gpu/drm/tests/drm_connector_test.c

1111

&priv->ddc,

drivers/gpu/drm/tests/drm_connector_test.c

1169

&priv->ddc,

drivers/gpu/drm/tests/drm_connector_test.c

1190

&priv->ddc,

drivers/gpu/drm/tests/drm_connector_test.c

120

&priv->ddc);

drivers/gpu/drm/tests/drm_connector_test.c

1225

&priv->ddc,

drivers/gpu/drm/tests/drm_connector_test.c

1479

&priv->ddc);

drivers/gpu/drm/tests/drm_connector_test.c

1502

&priv->ddc,

drivers/gpu/drm/tests/drm_connector_test.c

153

&priv->ddc);

drivers/gpu/drm/tests/drm_connector_test.c

224

&priv->ddc);

drivers/gpu/drm/tests/drm_connector_test.c

25

struct i2c_adapter ddc;

drivers/gpu/drm/tests/drm_connector_test.c

266

&priv->ddc);

drivers/gpu/drm/tests/drm_connector_test.c

314

&priv->ddc);

drivers/gpu/drm/tests/drm_connector_test.c

335

&priv->ddc);

drivers/gpu/drm/tests/drm_connector_test.c

354

&priv->ddc);

drivers/gpu/drm/tests/drm_connector_test.c

394

&priv->ddc);

drivers/gpu/drm/tests/drm_connector_test.c

677

&priv->ddc,

drivers/gpu/drm/tests/drm_connector_test.c

717

&priv->ddc,

drivers/gpu/drm/tests/drm_connector_test.c

737

&priv->ddc,

drivers/gpu/drm/tests/drm_connector_test.c

763

&priv->ddc,

drivers/gpu/drm/tests/drm_connector_test.c

796

&priv->ddc,

drivers/gpu/drm/tests/drm_connector_test.c

823

&priv->ddc,

drivers/gpu/drm/tests/drm_connector_test.c

849

&priv->ddc,

drivers/gpu/drm/tests/drm_connector_test.c

881

&priv->ddc,

drivers/gpu/drm/tests/drm_connector_test.c

908

&priv->ddc,

drivers/gpu/drm/tests/drm_connector_test.c

928

&priv->ddc,

drivers/gpu/drm/tests/drm_connector_test.c

93

strscpy(priv->ddc.name, "dummy-connector-ddc", sizeof(priv->ddc.name));

drivers/gpu/drm/tests/drm_connector_test.c

94

priv->ddc.owner = THIS_MODULE;

drivers/gpu/drm/tests/drm_connector_test.c

948

&priv->ddc,

drivers/gpu/drm/tests/drm_connector_test.c

95

priv->ddc.algo = &dummy_ddc_algorithm;

drivers/gpu/drm/tests/drm_connector_test.c

96

priv->ddc.dev.parent = dev;

drivers/gpu/drm/tests/drm_connector_test.c

973

&priv->ddc,

drivers/gpu/drm/tests/drm_connector_test.c

98

ret = i2c_add_adapter(&priv->ddc);

drivers/gpu/drm/vc4/vc4_hdmi.c

3209

put_device(&vc4_hdmi->ddc->dev);

drivers/gpu/drm/vc4/vc4_hdmi.c

3263

vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);

drivers/gpu/drm/vc4/vc4_hdmi.c

3265

if (!vc4_hdmi->ddc) {

drivers/gpu/drm/vc4/vc4_hdmi.c

331

ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);

drivers/gpu/drm/vc4/vc4_hdmi.c

549

vc4_hdmi->ddc,

drivers/gpu/drm/vc4/vc4_hdmi.h

123

struct i2c_adapter *ddc;

drivers/gpu/drm/xlnx/zynqmp_dp.c

1737

return drm_edid_read_ddc(connector, &dp->aux.ddc);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1111

NPCM7XX_PINCFG(204, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1112

NPCM7XX_PINCFG(205, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1113

NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)),

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

1114

NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)),

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

600

NPCM7XX_GRP(ddc), \

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

735

NPCM7XX_SFUNC(ddc);

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c

854

NPCM7XX_MKFUNC(ddc),

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

1023

NPCM8XX_SFUNC(ddc);

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

1246

NPCM8XX_MKFUNC(ddc),

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

785

NPCM8XX_GRP(ddc), \

drivers/pinctrl/tegra/pinctrl-tegra114.c

1810

DRV_PINGROUP(ddc, 0x8fc, 2, 3, -1, 12, 5, 20, 5, 28, 2, 30, 2, N),

drivers/pinctrl/tegra/pinctrl-tegra124.c

2017

DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),

drivers/pinctrl/tegra/pinctrl-tegra20.c

2059

MUX_PG(ddc, I2C2, RSVD2, RSVD3, RSVD4, 0x18, 31, 0x88, 0, 0xb0, 28),

drivers/pinctrl/tegra/pinctrl-tegra20.c

2201

DRV_PG(ddc, 0x8f0),

drivers/pinctrl/tegra/pinctrl-tegra30.c

2438

DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),

include/drm/display/drm_dp_helper.h

388

struct i2c_adapter ddc;

include/drm/drm_bridge.h

1176

struct i2c_adapter *ddc;

include/drm/drm_connector.h

2253

struct i2c_adapter *ddc;

include/drm/drm_connector.h

2365

struct i2c_adapter *ddc);

include/drm/drm_connector.h

2370

struct i2c_adapter *ddc);

include/drm/drm_connector.h

2375

struct i2c_adapter *ddc);

include/drm/drm_connector.h

2382

struct i2c_adapter *ddc,