ctlreg
unsigned int ctlreg = inl(0x500);
ctlreg &= ~0x8000;
outl(ctlreg, 0x500);
ctlreg = 0x05107c00;
outl(ctlreg, 0x500);
unsigned int ctlreg = inl(0x500);
&& ((1<<(36-busslot)) & ctlreg)) {
struct ctlreg __bootdata_preserved(s390_invalid_asce);
typecheck(struct ctlreg, array[0]); \
_esize = (_high - _low + 1) * sizeof(struct ctlreg); \
typecheck(struct ctlreg, array[0]); \
static __always_inline void local_ctl_load(unsigned int cr, struct ctlreg *reg)
static __always_inline void local_ctl_store(unsigned int cr, struct ctlreg *reg)
static __always_inline struct ctlreg local_ctl_set_bit(unsigned int cr, unsigned int bit)
struct ctlreg new, old;
static __always_inline struct ctlreg local_ctl_clear_bit(unsigned int cr, unsigned int bit)
struct ctlreg new, old;
static inline void system_ctl_load(unsigned int cr, struct ctlreg *reg)
struct ctlreg reg;
struct ctlreg reg;
struct ctlreg reg;
struct ctlreg reg;
_esize = (_high - _low + 1) * sizeof(struct ctlreg); \
struct ctlreg kprobe_saved_ctl[3];
struct ctlreg kernel_asce; /* 0x0388 */
struct ctlreg user_asce; /* 0x0390 */
struct ctlreg cregs_save_area[16]; /* 0x1380 */
extern struct ctlreg s390_invalid_asce;
struct ctlreg regs[16];
struct ctlreg regs[3];
struct ctlreg control;
struct ctlreg start;
struct ctlreg end;
struct ctlreg regs[3];
struct ctlreg control;
struct ctlreg start;
struct ctlreg end;
struct ctlreg cregs[16];
struct ctlreg cr0;
struct ctlreg cr6;
struct ctlreg cr6;
struct ctlreg cr1, cr7;
struct ctlreg __bootdata_preserved(s390_invalid_asce);
struct ctlreg asce;
u8 ctlreg, reg;
ctlreg = CTRL_REG4;
ctlreg = CTRL_REG1;
lis3->read(lis3, ctlreg, ®);
lis3->write(lis3, ctlreg, (reg | selftest));
lis3->write(lis3, ctlreg, reg);
if (dev->ctlreg & R852_CTL_CARDENABLE)
dev->ctlreg &= ~(R852_CTL_DATA | R852_CTL_COMMAND |
dev->ctlreg |= R852_CTL_DATA;
dev->ctlreg |= R852_CTL_COMMAND;
dev->ctlreg |= (R852_CTL_CARDENABLE | R852_CTL_ON);
dev->ctlreg &= ~R852_CTL_WRITE;
dev->ctlreg |= R852_CTL_WRITE;
r852_write_reg(dev, R852_CTL, dev->ctlreg);
if (dat == NAND_CMD_SEQIN && (dev->ctlreg & R852_CTL_COMMAND)) {
dev->ctlreg |= R852_CTL_WRITE;
r852_write_reg(dev, R852_CTL, dev->ctlreg);
dev->ctlreg |= R852_CTL_ECC_ENABLE;
dev->ctlreg | R852_CTL_ECC_ACCESS);
r852_write_reg(dev, R852_CTL, dev->ctlreg);
dev->ctlreg &= ~R852_CTL_ECC_ENABLE;
r852_write_reg(dev, R852_CTL, dev->ctlreg);
dev->ctlreg &= ~R852_CTL_ECC_ENABLE;
r852_write_reg(dev, R852_CTL, dev->ctlreg | R852_CTL_ECC_ACCESS);
r852_write_reg(dev, R852_CTL, dev->ctlreg);
r852_write_reg(dev, R852_CTL, dev->ctlreg | R852_CTL_ECC_ACCESS);
r852_write_reg(dev, R852_CTL, dev->ctlreg);
uint8_t ctlreg; /* cached contents of control reg */
struct ctlreg cr0, cr0_sync;