csio_rd_reg32
if (!(csio_rd_reg32(hw, PCIE_FW_A) & PCIE_FW_HALT_F))
val = csio_rd_reg32(hw, reg);
val |= csio_rd_reg32(hw, TP_PIO_DATA_A) & ~mask;
uint32_t val = csio_rd_reg32(hw, reg) & ~mask;
csio_rd_reg32(hw, reg);
hw->chip_ver = (char)csio_rd_reg32(hw, PL_REV_A);
uint32_t pl = csio_rd_reg32(hw, PL_INT_ENABLE_A);
pf = SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A));
pf = T6_SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A));
pf = SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A));
pf = T6_SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A));
unsigned int status = csio_rd_reg32(hw, reg);
v = (uint64_t)csio_rd_reg32(hw, SGE_INT_CAUSE1_A) |
((uint64_t)csio_rd_reg32(hw, SGE_INT_CAUSE2_A) << 32);
csio_rd_reg32(hw, MPS_INT_CAUSE_A); /* flush */
v = csio_rd_reg32(hw, addr) & MEM_INT_MASK;
uint32_t cnt = ECC_CECNT_G(csio_rd_reg32(hw, cnt_addr));
uint32_t v, status = csio_rd_reg32(hw, MA_INT_CAUSE_A);
csio_rd_reg32(hw, MA_PARITY_ERROR_STATUS_A));
v = csio_rd_reg32(hw, MA_INT_WRAP_STATUS_A);
uint32_t v = csio_rd_reg32(hw, T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A));
uint32_t cause = csio_rd_reg32(hw, PL_INT_CAUSE_A);
csio_rd_reg32(hw, PL_INT_CAUSE_A); /* flush */
if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F)
*valp = csio_rd_reg32(hw, SF_DATA_A);
if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F)
while (((reg = csio_rd_reg32(hw, PL_WHOAMI_A)) == 0xFFFFFFFF) &&
pcie_fw = csio_rd_reg32(hw, PCIE_FW_A);
if (csio_rd_reg32(hw, mc_bist_cmd_reg) & START_BIST_F)
*data++ = htonl(csio_rd_reg32(hw, MC_DATA(i)));
if (csio_rd_reg32(hw, edc_bist_cmd_reg) & START_BIST_F)
*data++ = htonl(csio_rd_reg32(hw, EDC_DATA(i)));
edc_size = EDRAM0_SIZE_G(csio_rd_reg32(hw, MA_EDRAM0_BAR_A));
mc_size = EXT_MEM_SIZE_G(csio_rd_reg32(hw,
mem_reg = csio_rd_reg32(hw,
csio_rd_reg32(hw,
*buf++ = csio_rd_reg32(hw, mem_base + offset);
int i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE_A);
size = csio_rd_reg32(hw, MA_EXT_MEMORY_BAR_A);
size = csio_rd_reg32(hw, MA_EXT_MEMORY1_BAR_A);
csio_rd_reg32(hw,
i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE_A);
csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_ENABLE_A));
csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_ENABLE_A));
csio_rd_reg32(hw, ctl_reg);
owner = MBOWNER_G(csio_rd_reg32(hw, ctl_reg));
owner = MBOWNER_G(csio_rd_reg32(hw, ctl_reg));
csio_rd_reg32(hw, ctl_reg);
ctl = csio_rd_reg32(hw, ctl_reg);
pl_cause = csio_rd_reg32(hw, MYPF_REG(PL_PF_INT_CAUSE_A));
cim_cause = csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_CAUSE_A));
ctl = csio_rd_reg32(hw, ctl_reg);
csio_rd_reg32(hw, ctl_reg);
csio_rd_reg32(hw, ctl_reg);
(csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE2_A) +
(csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE3_A) +
sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL_A);
timer_value_0_and_1 = csio_rd_reg32(hw, SGE_TIMER_VALUE_0_AND_1_A);
timer_value_2_and_3 = csio_rd_reg32(hw, SGE_TIMER_VALUE_2_AND_3_A);
timer_value_4_and_5 = csio_rd_reg32(hw, SGE_TIMER_VALUE_4_AND_5_A);
ingress_rx_threshold = csio_rd_reg32(hw, SGE_INGRESS_RX_THRESHOLD_A);
sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL_A);
sge->sge_fl_buf_size[reg] = csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE0_A +