drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1422

struct clk_mgr *clk_mgr = ctx->dc->clk_mgr;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1525

dc_state->bw_ctx.bw.dcn.clk.dramclk_khz = clk_mgr->dc_mode_softmax_enabled ?

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1526

clk_mgr->bw_params->dc_mode_softmax_memclk : clk_mgr->bw_params->max_memclk_mhz;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1528

ctx->dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1529

ctx->dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

116

clk_mgr->psr_allow_active_cache = edp_link->psr_settings.psr_allow_active;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

124

void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

138

&clk_mgr->psr_allow_active_cache, false, false, NULL);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

140

&clk_mgr->psr_allow_active_cache, false, false, NULL);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

149

struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

157

struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

159

if (clk_mgr == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

163

dce_clk_mgr_construct(ctx, clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

164

return &clk_mgr->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

167

struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

169

if (clk_mgr == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

173

dce110_clk_mgr_construct(ctx, clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

174

return &clk_mgr->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

177

struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

179

if (clk_mgr == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

185

dce_clk_mgr_construct(ctx, clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

186

return &clk_mgr->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

191

dce112_clk_mgr_construct(ctx, clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

192

return &clk_mgr->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

195

dce112_clk_mgr_construct(ctx, clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

196

return &clk_mgr->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

198

return &clk_mgr->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

201

struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

203

if (clk_mgr == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

208

dce121_clk_mgr_construct(ctx, clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

210

dce120_clk_mgr_construct(ctx, clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

211

return &clk_mgr->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

215

struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

217

if (clk_mgr == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

223

rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

224

return &clk_mgr->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

228

rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

229

return &clk_mgr->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

232

rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

233

return &clk_mgr->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

237

rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

238

return &clk_mgr->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

240

return &clk_mgr->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

243

struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

245

if (clk_mgr == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

250

dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

251

return &clk_mgr->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

254

dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

255

return &clk_mgr->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

258

dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

259

return &clk_mgr->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

262

dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

263

return &clk_mgr->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

265

dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

266

return &clk_mgr->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

270

struct clk_mgr_vgh *clk_mgr = kzalloc_obj(*clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

272

if (clk_mgr == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

276

vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

277

return &clk_mgr->base.base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

282

struct clk_mgr_dcn31 *clk_mgr = kzalloc_obj(*clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

284

if (clk_mgr == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

289

dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

290

return &clk_mgr->base.base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

294

struct clk_mgr_dcn315 *clk_mgr = kzalloc_obj(*clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

296

if (clk_mgr == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

301

dcn315_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

302

return &clk_mgr->base.base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

306

struct clk_mgr_dcn316 *clk_mgr = kzalloc_obj(*clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

308

if (clk_mgr == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

313

dcn316_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

314

return &clk_mgr->base.base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

318

struct clk_mgr_internal *clk_mgr = kzalloc_obj(*clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

320

if (clk_mgr == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

324

dcn32_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

325

return &clk_mgr->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

329

struct clk_mgr_dcn314 *clk_mgr = kzalloc_obj(*clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

331

if (clk_mgr == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

336

dcn314_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

337

return &clk_mgr->base.base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

343

struct clk_mgr_dcn42 *clk_mgr = kzalloc_obj(*clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

345

if (clk_mgr == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

349

dcn42b_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

350

return &clk_mgr->base.base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

352

struct clk_mgr_dcn35 *clk_mgr = kzalloc_obj(*clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

354

if (clk_mgr == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

359

dcn351_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

361

dcn35_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

363

return &clk_mgr->base.base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

368

struct clk_mgr_internal *clk_mgr = dcn401_clk_mgr_construct(ctx, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

370

if (clk_mgr == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

375

return &clk_mgr->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

379

struct clk_mgr_dcn42 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

381

if (clk_mgr == NULL) {

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

386

dcn42_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

387

return &clk_mgr->base.base;

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

399

void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

401

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

407

dcn3_clk_mgr_destroy(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

409

dcn3_clk_mgr_destroy(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

412

dcn3_clk_mgr_destroy(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

418

vg_clk_mgr_destroy(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

422

dcn31_clk_mgr_destroy(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

426

dcn315_clk_mgr_destroy(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

430

dcn316_clk_mgr_destroy(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

434

dcn32_clk_mgr_destroy(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

438

dcn314_clk_mgr_destroy(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

443

dcn42_clk_mgr_destroy(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

446

dcn35_clk_mgr_destroy(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

449

dcn401_clk_mgr_destroy(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

452

dcn42_clk_mgr_destroy(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

460

kfree(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

98

void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

115

static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

117

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

126

return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

129

int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

131

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

153

* clk_mgr->base.dentist_vco_freq_khz) / target_div;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

155

return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

158

int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

199

struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

329

static void dce_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

357

struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

359

struct clk_mgr *base = &clk_mgr->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

365

clk_mgr->regs = &disp_clk_regs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

366

clk_mgr->clk_mgr_shift = &disp_clk_shift;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

367

clk_mgr->clk_mgr_mask = &disp_clk_mask;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

370

clk_mgr->dfs_bypass_disp_clk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

371

clk_mgr->dprefclk_ss_percentage = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

372

clk_mgr->dprefclk_ss_divider = 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

373

clk_mgr->ss_on_dprefclk = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

386

dce_clock_read_integrated_info(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

387

dce_clock_read_ss_info(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

47

(clk_mgr->regs->reg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

51

clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h

34

int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h

45

int dce12_get_dp_ref_freq_khz(struct clk_mgr *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h

48

struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h

52

void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

111

struct dc *dc = context->clk_mgr->ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

116

pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

243

static void dce11_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

268

struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

270

dce_clk_mgr_construct(ctx, clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

272

clk_mgr->regs = &disp_clk_regs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

273

clk_mgr->clk_mgr_shift = &disp_clk_shift;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

274

clk_mgr->clk_mgr_mask = &disp_clk_mask;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c

275

clk_mgr->base.funcs = &dce110_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.h

31

struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

104

int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

107

struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

108

struct dc *dc = clk_mgr->base.ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

117

clk_mgr->base.dentist_vco_freq_khz / 62);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

127

if (clk_mgr->dfs_bypass_disp_clk != actual_clock)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

132

clk_mgr->dfs_bypass_disp_clk = actual_clock;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

137

int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

140

struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

149

if (!((clk_mgr->base.ctx->asic_id.chip_family == FAMILY_AI) &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

150

ASICREV_IS_VEGA20_P(clk_mgr->base.ctx->asic_id.hw_internal_rev)))

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

163

static void dce112_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

188

struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

190

dce_clk_mgr_construct(ctx, clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

192

clk_mgr->regs = &disp_clk_regs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

193

clk_mgr->clk_mgr_shift = &disp_clk_shift;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

194

clk_mgr->clk_mgr_mask = &disp_clk_mask;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

195

clk_mgr->base.funcs = &dce112_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

57

int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.h

32

struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.h

35

int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.h

36

int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.h

37

int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

116

void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

118

dce_clk_mgr_construct(ctx, clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

120

clk_mgr->base.dprefclk_khz = 600000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

121

clk_mgr->base.funcs = &dce120_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

124

void dce121_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

126

dce120_clk_mgr_construct(ctx, clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

127

clk_mgr->base.dprefclk_khz = 625000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

134

dce121_clock_patch_xgmi_ss_info(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.c

72

static void dce12_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.h

29

void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/dce120_clk_mgr.h

30

void dce121_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

158

clk_mgr->funcs->set_dispclk(clk_mgr, dispclk_to_dpp_threshold);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

159

clk_mgr->funcs->set_dprefclk(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

177

clk_mgr->funcs->set_dispclk(clk_mgr, new_clocks->dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

178

clk_mgr->funcs->set_dprefclk(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

182

clk_mgr->base.clks.dispclk_khz = new_clocks->dispclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

183

clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

184

clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

187

static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

191

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

202

ASSERT(clk_mgr->pp_smu);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

207

pp_smu = &clk_mgr->pp_smu->rv_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

274

ramp_up_dispclk_with_dpp(clk_mgr, dc, new_clocks, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

291

static void rv1_enable_pme_wa(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

293

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

296

if (clk_mgr->pp_smu) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

297

pp_smu = &clk_mgr->pp_smu->rv_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

316

void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

321

clk_mgr->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

322

clk_mgr->pp_smu = pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

323

clk_mgr->base.funcs = &rv1_clk_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

324

clk_mgr->funcs = &rv1_clk_internal_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

326

clk_mgr->dfs_bypass_disp_clk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

328

clk_mgr->dprefclk_ss_percentage = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

329

clk_mgr->dprefclk_ss_divider = 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

330

clk_mgr->ss_on_dprefclk = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

331

clk_mgr->base.dprefclk_khz = 600000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

334

clk_mgr->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

335

if (bp->fw_info_valid && clk_mgr->base.dentist_vco_freq_khz == 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

336

clk_mgr->base.dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

337

if (clk_mgr->base.dentist_vco_freq_khz == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

338

clk_mgr->base.dentist_vco_freq_khz = 3600000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

34

static void rv1_init_clocks(struct clk_mgr *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

343

clk_mgr->dfs_bypass_enabled = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

345

dce_clock_read_ss_info(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

36

memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

39

static int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

42

bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

44

bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

74

if (clk_mgr->base.clks.dispclk_khz <= disp_clk_threshold)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

86

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

92

int dispclk_to_dpp_threshold = rv1_determine_dppclk_threshold(clk_mgr, new_clocks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.h

29

void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

103

static int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

117

result = rv1_smu_wait_for_response(clk_mgr, 10, 1000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

125

int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

128

struct dc *dc = clk_mgr->base.ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

133

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

138

if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

85

static uint32_t rv1_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.h

29

int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv2_clk_mgr.c

37

void rv2_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv2_clk_mgr.c

40

rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv2_clk_mgr.c

42

clk_mgr->funcs = &rv2_clk_internal_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv2_clk_mgr.h

29

void rv2_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

104

void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

109

clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

110

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

119

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

122

clk_mgr->dccg->funcs->update_dpp_dto(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

123

clk_mgr->dccg, dpp_inst, dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

127

void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct dc_state *context)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

136

if (clk_mgr->base.clks.dppclk_khz == 0 || clk_mgr->base.clks.dispclk_khz == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

140

* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

142

* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

152

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

155

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

183

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

185

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

216

void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

220

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

299

if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

300

if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

302

clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

327

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

328

dcn20_update_clocks_update_dentist(clk_mgr, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

332

dcn20_update_clocks_update_dentist(clk_mgr, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

334

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

346

void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

350

struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

356

if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

357

clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

360

if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

361

clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

365

new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

366

clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

369

if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

370

clk_mgr->clks.socclk_khz = new_clocks->socclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

373

if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

374

clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

377

if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

378

clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

381

if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

382

clk_mgr->clks.fclk_khz = fclk_adj;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

385

if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

386

clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

393

if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

394

clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

395

if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

396

clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

399

clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

402

clk_mgr->clks.dtbclk_en = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

403

dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

406

void dcn2_init_clocks(struct clk_mgr *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

408

memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

410

clk_mgr->clks.p_state_change_support = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

411

clk_mgr->clks.prev_p_state_change_support = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

414

static void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

416

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

419

if (clk_mgr->pp_smu) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

420

pp_smu = &clk_mgr->pp_smu->nv_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

428

void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

430

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

44

clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

445

* clk_mgr->base.dentist_vco_freq_khz) / disp_divider;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

448

* clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

452

void dcn2_get_clock(struct clk_mgr *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

461

clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

467

clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

47

(clk_mgr->regs->reg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

496

static void dcn2_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

498

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

502

if (!clk_mgr->pp_smu || !clk_mgr->pp_smu->nv_funcs.set_voltage_by_freq)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

505

pp_smu = &clk_mgr->pp_smu->nv_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

507

clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

510

if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

511

max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

533

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

542

clk_mgr->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

543

clk_mgr->pp_smu = pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

544

clk_mgr->base.funcs = &dcn2_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

545

clk_mgr->regs = &clk_mgr_regs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

546

clk_mgr->clk_mgr_shift = &clk_mgr_shift;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

547

clk_mgr->clk_mgr_mask = &clk_mgr_mask;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

549

clk_mgr->dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

550

clk_mgr->dfs_bypass_disp_clk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

552

clk_mgr->dprefclk_ss_percentage = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

553

clk_mgr->dprefclk_ss_divider = 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

554

clk_mgr->ss_on_dprefclk = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

556

clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

570

pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

571

pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

577

clk_mgr->base.dentist_vco_freq_khz = dc_fixpt_floor(pll_req);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

580

if (clk_mgr->base.dentist_vco_freq_khz == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

581

clk_mgr->base.dentist_vco_freq_khz = 3850000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

584

clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

585

* clk_mgr->base.dentist_vco_freq_khz) / target_div;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

589

clk_mgr->dfs_bypass_enabled = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

591

dce_clock_read_ss_info(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

29

void dcn2_update_clocks(struct clk_mgr *dccg,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

33

void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

36

void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

39

void dcn2_init_clocks(struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

42

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

48

void dcn2_get_clock(struct clk_mgr *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

53

void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

56

void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

143

if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

144

if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

146

clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

160

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

161

dcn20_update_clocks_update_dentist(clk_mgr, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

165

dcn20_update_clocks_update_dentist(clk_mgr, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

167

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

180

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

186

clk_mgr->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

187

clk_mgr->base.funcs = &dcn201_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

188

clk_mgr->regs = &clk_mgr_regs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

189

clk_mgr->clk_mgr_shift = &clk_mgr_shift;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

190

clk_mgr->clk_mgr_mask = &clk_mgr_mask;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

192

clk_mgr->dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

194

clk_mgr->dfs_bypass_disp_clk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

196

clk_mgr->dprefclk_ss_percentage = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

197

clk_mgr->dprefclk_ss_divider = 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

198

clk_mgr->ss_on_dprefclk = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

200

clk_mgr->base.dprefclk_khz = REG_READ(CLK4_CLK2_CURRENT_CNT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

201

clk_mgr->base.dprefclk_khz *= 100;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

203

if (clk_mgr->base.dprefclk_khz == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

204

clk_mgr->base.dprefclk_khz = 600000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

206

REG_GET(CLK4_CLK_PLL_REQ, FbMult_int, &clk_mgr->base.dentist_vco_freq_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

207

clk_mgr->base.dentist_vco_freq_khz *= 100000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

209

if (clk_mgr->base.dentist_vco_freq_khz == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

210

clk_mgr->base.dentist_vco_freq_khz = 3000000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

214

clk_mgr->dfs_bypass_enabled = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

216

dce_clock_read_ss_info(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

43

(clk_mgr->regs->reg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

58

clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

61

clk_mgr->base.ctx

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

75

static void dcn201_init_clocks(struct clk_mgr *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

77

memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

78

clk_mgr->clks.p_state_change_support = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

79

clk_mgr->clks.prev_p_state_change_support = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

80

clk_mgr->clks.max_supported_dppclk_khz = 1200000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

81

clk_mgr->clks.max_supported_dispclk_khz = 1200000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

84

static void dcn201_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

88

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.h

30

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

106

static void rn_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

111

clk_mgr->dccg->ref_dppclk = ref_dpp_clk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

113

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

119

dpp_inst = clk_mgr->base.ctx->dc->res_pool->dpps[i]->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

122

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[dpp_inst];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

125

clk_mgr->dccg->funcs->update_dpp_dto(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

126

clk_mgr->dccg, dpp_inst, dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

131

static void rn_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

135

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

160

rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

168

rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_MISSION_MODE);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

176

rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

182

rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

208

clk_mgr_base->clks.actual_dispclk_khz = rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

216

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

222

rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

226

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

235

rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

239

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

253

static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

278

pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

284

static void rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

286

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

306

struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

438

static void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

440

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

442

rn_vbios_smu_enable_pme_wa(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

445

static void rn_init_clocks(struct clk_mgr *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

447

memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

449

clk_mgr->clks.p_state_change_support = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

450

clk_mgr->clks.prev_p_state_change_support = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

451

clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

516

static void rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

519

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

520

struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

549

static void rn_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

551

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

554

clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

557

if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

558

max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

563

rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

708

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

720

clk_mgr->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

721

clk_mgr->base.funcs = &dcn21_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

723

clk_mgr->pp_smu = pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

725

clk_mgr->dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

726

clk_mgr->dfs_bypass_disp_clk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

728

clk_mgr->dprefclk_ss_percentage = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

729

clk_mgr->dprefclk_ss_divider = 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

730

clk_mgr->ss_on_dprefclk = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

731

clk_mgr->dfs_ref_freq_khz = 48000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

733

clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

735

clk_mgr->periodic_retraining_disabled = rn_vbios_smu_is_periodic_retraining_disabled(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

739

if (clk_mgr->smu_ver >= SMU_VER_55_51_0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

743

clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

746

if (clk_mgr->base.dentist_vco_freq_khz == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

747

clk_mgr->base.dentist_vco_freq_khz = 3600000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

751

if (clk_mgr->periodic_retraining_disabled) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

770

rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

772

clk_mgr->base.dprefclk_khz = 600000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

773

dce_clock_read_ss_info(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

776

clk_mgr->base.bw_params = &rn_bw_params;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

783

rn_clk_mgr_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

786

clk_mgr->base.bw_params->num_channels = 1;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

791

if (clk_mgr->smu_ver >= 0x00371500)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

792

rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

86

static void rn_set_low_power_state(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

89

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

99

rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h

45

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

105

result = rn_smu_wait_for_response(clk_mgr, 10, 200000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

123

result = rn_smu_wait_for_response(clk_mgr, 10, 200000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

134

int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

137

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

143

int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

146

struct dc *dc = clk_mgr->base.ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

151

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

156

if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

167

int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

171

if (clk_mgr->smu_ver < 0x370c00)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

175

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

182

int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

186

if (clk_mgr->smu_ver < 0x370c00)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

190

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

197

void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

200

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

205

int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

210

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

219

void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum dcn_pwr_state state)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

229

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

234

void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

237

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

242

void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

245

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

250

int rn_vbios_smu_is_periodic_retraining_disabled(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

253

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

80

static uint32_t rn_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

99

static int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

31

int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

32

int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

33

int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

34

int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

35

void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

36

int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

37

void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum dcn_pwr_state);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

38

void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

39

void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

40

int rn_vbios_smu_is_periodic_retraining_disabled(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

102

static void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

105

dcn3_fpu_build_wm_range_table(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

109

void dcn3_init_clocks(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

111

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

117

clk_mgr->smu_present = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

122

if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

123

clk_mgr->smu_present = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

125

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

129

dcn30_smu_check_driver_if_version(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

130

dcn30_smu_check_msg_header_version(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

133

dcn3_init_single_clock(clk_mgr, PPCLK_DCEFCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

136

dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, 0);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

139

dcn3_init_single_clock(clk_mgr, PPCLK_DTBCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

144

dcn3_init_single_clock(clk_mgr, PPCLK_SOCCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

150

dcn3_init_single_clock(clk_mgr, PPCLK_DISPCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

155

dcn3_init_single_clock(clk_mgr, PPCLK_PIXCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

160

dcn3_init_single_clock(clk_mgr, PPCLK_PHYCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

169

dcn3_build_wm_range_table(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

173

static int dcn30_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

184

pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

185

pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

188

pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

193

static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

197

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

211

if (dc->work_arounds.skip_clock_update || !clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

229

dcn30_smu_set_num_of_displays(clk_mgr, display_count);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

240

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

245

dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

256

if (dc->clk_mgr->dc_mode_softmax_enabled && safe_to_lower && !p_state_change_support) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

257

int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

270

if (dc->clk_mgr->dc_mode_softmax_enabled &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

271

new_clocks->dramclk_khz <= (int)(dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

272

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

273

(uint16_t)dc->clk_mgr->bw_params->dc_mode_softmax_memclk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

275

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

290

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

297

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

303

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

310

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

311

dcn20_update_clocks_update_dentist(clk_mgr, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

315

dcn20_update_clocks_update_dentist(clk_mgr, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

319

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

330

static void dcn3_notify_wm_ranges(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

333

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

334

WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

336

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

347

if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

348

table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_dcfclk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

349

table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_dcfclk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

350

table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_uclk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

351

table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_uclk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

353

table->Watermarks.WatermarkRow[WM_DCEFCLK][i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

356

dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

357

dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

358

dcn30_smu_transfer_wm_table_dram_2_smu(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

362

static void dcn3_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

364

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

366

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

371

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

374

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

378

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

384

static void dcn3_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

386

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

388

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

391

dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

396

static void dcn3_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

398

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

400

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

403

dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

405

static void dcn3_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

407

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

409

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

411

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

415

static void dcn3_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

417

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

420

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

424

dcn3_init_single_clock(clk_mgr, PPCLK_UCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

429

clk_mgr_base->bw_params->dc_mode_softmax_memclk = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

433

clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

436

static bool dcn3_is_smu_present(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

438

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

439

return clk_mgr->smu_present;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

461

static void dcn3_enable_pme_wa(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

463

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

465

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

468

dcn30_smu_set_pme_workaround(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

472

static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

474

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

477

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

482

clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

485

if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

486

max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

491

dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

50

clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

512

static void dcn3_init_clocks_fpga(struct clk_mgr *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

514

dcn2_init_clocks(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

528

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

53

(clk_mgr->regs->reg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

535

clk_mgr->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

536

clk_mgr->base.funcs = &dcn3_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

537

clk_mgr->regs = &clk_mgr_regs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

538

clk_mgr->clk_mgr_shift = &clk_mgr_shift;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

539

clk_mgr->clk_mgr_mask = &clk_mgr_mask;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

541

clk_mgr->dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

542

clk_mgr->dfs_bypass_disp_clk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

544

clk_mgr->dprefclk_ss_percentage = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

545

clk_mgr->dprefclk_ss_divider = 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

546

clk_mgr->ss_on_dprefclk = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

547

clk_mgr->dfs_ref_freq_khz = 100000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

549

clk_mgr->base.dprefclk_khz = 730000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

552

clk_mgr->base.dentist_vco_freq_khz = dcn30_get_vco_frequency_from_reg(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

555

if (clk_mgr->base.dentist_vco_freq_khz == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

556

clk_mgr->base.dentist_vco_freq_khz = 3650000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

564

clk_mgr->base.dprefclk_khz = s.dprefclk * 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

566

clk_mgr->dfs_bypass_enabled = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

568

clk_mgr->smu_present = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

570

dce_clock_read_ss_info(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

572

clk_mgr->base.bw_params = kzalloc_obj(*clk_mgr->base.bw_params);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

573

if (!clk_mgr->base.bw_params) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

579

clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

581

&clk_mgr->wm_range_table_addr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

582

if (!clk_mgr->wm_range_table) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

588

void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

590

kfree(clk_mgr->base.bw_params);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

592

if (clk_mgr->wm_range_table)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

593

dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

594

clk_mgr->wm_range_table);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

81

static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, uint8_t *num_levels)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

85

uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

97

*((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

98

entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h

89

void dcn3_init_clocks(struct clk_mgr *clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h

92

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h

96

void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

112

bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

118

if (dcn30_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

126

bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

130

if (dcn30_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

142

bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

148

if (dcn30_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

161

bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

167

if (dcn30_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

179

void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

183

dcn30_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

187

void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

191

dcn30_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

195

void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

199

dcn30_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

203

void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

207

dcn30_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

212

unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

221

dcn30_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

230

unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

239

dcn30_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

261

unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

270

dcn30_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

279

unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

288

dcn30_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

296

void dcn30_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

300

dcn30_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

304

void dcn30_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

308

dcn30_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

312

void dcn30_smu_set_display_refresh_from_mall(struct clk_mgr_internal *clk_mgr, bool enable, uint8_t cache_timer_delay, uint8_t cache_timer_scale)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

320

dcn30_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

324

void dcn30_smu_set_external_client_df_cstate_allow(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

328

dcn30_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

332

void dcn30_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

336

dcn30_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

54

static uint32_t dcn30_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

72

TRACE_SMU_MSG_DELAY(0, 0, delay_us * (initial_max_retries - max_retries), clk_mgr->base.ctx);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

77

static bool dcn30_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

81

dcn30_smu_wait_for_response(clk_mgr, 10, 200000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

92

TRACE_SMU_MSG(msg_id, param_in, clk_mgr->base.ctx);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

94

result = dcn30_smu_wait_for_response(clk_mgr, 10, 200000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

33

bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

34

bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

35

bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

36

bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

37

void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

38

void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

39

void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

40

void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

41

unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

42

unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

43

unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

44

unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

45

void dcn30_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

46

void dcn30_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

47

void dcn30_smu_set_display_refresh_from_mall(struct clk_mgr_internal *clk_mgr, bool enable, uint8_t cache_timer_delay, uint8_t cache_timer_scale);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

48

void dcn30_smu_set_external_client_df_cstate_allow(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h

49

void dcn30_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.c

31

uint32_t dcn30m_set_smartmux_switch(struct clk_mgr *clk_mgr_base, uint32_t pins_to_set)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.c

33

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.c

35

return dcn30m_smu_set_smart_mux_switch(clk_mgr, pins_to_set);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.h

29

uint32_t dcn30m_set_smartmux_switch(struct clk_mgr *clk_mgr_base, uint32_t pins_to_set);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

108

uint32_t dcn30m_smu_set_smart_mux_switch(struct clk_mgr_internal *clk_mgr, uint32_t pins_to_set)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

114

dcn30m_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

53

static uint32_t dcn30m_smu_wait_for_response(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

76

static bool dcn30m_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

81

dcn30m_smu_wait_for_response(clk_mgr, 10, 200000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

92

result = dcn30m_smu_wait_for_response(clk_mgr, 10, 200000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.h

33

uint32_t dcn30m_smu_set_smart_mux_switch(struct clk_mgr_internal *clk_mgr, uint32_t pins_to_set);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

104

result = dcn301_smu_wait_for_response(clk_mgr, 10, 200000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

122

result = dcn301_smu_wait_for_response(clk_mgr, 10, 200000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

133

int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

135

int smu_version = dcn301_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

145

int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

153

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

160

int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

164

DC_LOG_DEBUG("%s %d\n", __func__, clk_mgr->base.dprefclk_khz / 1000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

167

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

169

khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

176

int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

183

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

190

int dcn301_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

197

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

204

int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

211

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

218

void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

225

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

230

void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

242

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

247

void dcn301_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

250

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

255

void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

259

dcn301_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

263

void dcn301_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

267

dcn301_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

271

void dcn301_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

273

dcn301_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

277

void dcn301_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

279

dcn301_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

80

static uint32_t dcn301_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

98

static int dcn301_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

150

int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

151

int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

152

int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

153

int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

154

int dcn301_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

155

int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

156

void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

157

void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

158

void dcn301_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

159

void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

160

void dcn301_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

161

void dcn301_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

162

void dcn301_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

126

dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

136

dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

144

dcn301_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

150

dcn301_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

157

if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

158

if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

166

dcn301_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

173

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

174

dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

178

dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

180

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

185

static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

210

pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

216

static void vg_dump_clk_registers_internal(struct dcn301_clk_internal *internal, struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

218

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

238

struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

370

static void vg_enable_pme_wa(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

372

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

374

dcn301_smu_enable_pme_wa(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

377

static void vg_init_clocks(struct clk_mgr *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

379

memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

381

clk_mgr->clks.p_state_change_support = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

382

clk_mgr->clks.prev_p_state_change_support = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

383

clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

445

static void vg_notify_wm_ranges(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

447

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

448

struct clk_mgr_vgh *clk_mgr_vgh = TO_CLK_MGR_VGH(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

451

if (!clk_mgr->smu_ver)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

461

dcn301_smu_set_dram_addr_high(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

463

dcn301_smu_set_dram_addr_low(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

465

dcn301_smu_transfer_wm_table_dram_2_smu(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

55

#define TO_CLK_MGR_VGH(clk_mgr)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

56

container_of(clk_mgr, struct clk_mgr_vgh, base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

563

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

569

struct clk_bw_params *bw_params = clk_mgr->base.bw_params;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

662

static void vg_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

667

if (!clk_mgr->smu_ver)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

675

dcn301_smu_set_dram_addr_high(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

677

dcn301_smu_set_dram_addr_low(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

679

dcn301_smu_transfer_dpm_table_smu_2_dram(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

684

struct clk_mgr_vgh *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

691

clk_mgr->base.base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

692

clk_mgr->base.base.funcs = &vg_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

694

clk_mgr->base.pp_smu = pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

696

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

697

clk_mgr->base.dfs_bypass_disp_clk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

699

clk_mgr->base.dprefclk_ss_percentage = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

700

clk_mgr->base.dprefclk_ss_divider = 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

701

clk_mgr->base.ss_on_dprefclk = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

702

clk_mgr->base.dfs_ref_freq_khz = 48000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

704

clk_mgr->smu_wm_set.wm_set = (struct watermarks *)dm_helpers_allocate_gpu_mem(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

705

clk_mgr->base.base.ctx,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

708

&clk_mgr->smu_wm_set.mc_address.quad_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

710

if (!clk_mgr->smu_wm_set.wm_set) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

711

clk_mgr->smu_wm_set.wm_set = &dummy_wms;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

712

clk_mgr->smu_wm_set.mc_address.quad_part = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

714

ASSERT(clk_mgr->smu_wm_set.wm_set);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

717

clk_mgr->base.base.ctx,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

729

clk_mgr->base.smu_ver = dcn301_smu_get_smu_version(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

731

if (clk_mgr->base.smu_ver)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

732

clk_mgr->base.smu_present = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

735

clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

738

if (clk_mgr->base.base.dentist_vco_freq_khz == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

739

clk_mgr->base.base.dentist_vco_freq_khz = 3600000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

748

vg_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

750

clk_mgr->base.base.dprefclk_khz = 600000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

751

dce_clock_read_ss_info(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

753

clk_mgr->base.base.bw_params = &vg_bw_params;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

755

vg_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

758

&clk_mgr->base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

764

dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

770

struct clk_mgr_vgh *clk_mgr = TO_CLK_MGR_VGH(clk_mgr_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

772

if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

774

clk_mgr->smu_wm_set.wm_set);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

95

static void vg_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

99

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.h

46

struct clk_mgr_vgh *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.h

50

void vg_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

117

static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

137

void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

142

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

160

dcn31_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

165

dcn31_smu_set_dtbclk(clk_mgr, false);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

177

dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

185

dcn31_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

190

dcn31_smu_set_dtbclk(clk_mgr, true);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

197

dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

205

dcn31_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

211

dcn31_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

218

if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

219

if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

229

dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

237

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

238

dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

242

dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

245

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

261

static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

285

pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

291

static void dcn31_enable_pme_wa(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

293

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

295

dcn31_smu_enable_pme_wa(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

298

void dcn31_init_clocks(struct clk_mgr *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

300

uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

302

memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

304

clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

305

clk_mgr->clks.p_state_change_support = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

306

clk_mgr->clks.prev_p_state_change_support = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

307

clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

308

clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

331

struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

483

static void dcn31_notify_wm_ranges(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

485

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

486

struct clk_mgr_dcn31 *clk_mgr_dcn31 = TO_CLK_MGR_DCN31(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

489

if (!clk_mgr->smu_ver)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

499

dcn31_smu_set_dram_addr_high(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

501

dcn31_smu_set_dram_addr_low(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

503

dcn31_smu_transfer_wm_table_dram_2_smu(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

506

static void dcn31_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

511

if (!clk_mgr->smu_ver)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

519

dcn31_smu_set_dram_addr_high(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

521

dcn31_smu_set_dram_addr_low(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

523

dcn31_smu_transfer_dpm_table_smu_2_dram(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

562

static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

568

struct clk_bw_params *bw_params = clk_mgr->base.bw_params;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

58

clk_mgr->base.base.ctx->logger

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

640

static void dcn31_set_low_power_state(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

643

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

656

dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

663

int dcn31_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

682

struct clk_mgr_dcn31 *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

689

clk_mgr->base.base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

690

clk_mgr->base.base.funcs = &dcn31_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

692

clk_mgr->base.pp_smu = pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

694

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

695

clk_mgr->base.dfs_bypass_disp_clk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

697

clk_mgr->base.dprefclk_ss_percentage = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

698

clk_mgr->base.dprefclk_ss_divider = 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

699

clk_mgr->base.ss_on_dprefclk = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

700

clk_mgr->base.dfs_ref_freq_khz = 48000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

702

clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

703

clk_mgr->base.base.ctx,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

706

&clk_mgr->smu_wm_set.mc_address.quad_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

708

if (!clk_mgr->smu_wm_set.wm_set) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

709

clk_mgr->smu_wm_set.wm_set = &dummy_wms;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

710

clk_mgr->smu_wm_set.mc_address.quad_part = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

712

ASSERT(clk_mgr->smu_wm_set.wm_set);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

715

clk_mgr->base.base.ctx,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

727

clk_mgr->base.smu_ver = dcn31_smu_get_smu_version(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

729

if (clk_mgr->base.smu_ver)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

73

#define TO_CLK_MGR_DCN31(clk_mgr)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

730

clk_mgr->base.smu_present = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

733

clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

74

container_of(clk_mgr, struct clk_mgr_dcn31, base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

742

dcn31_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

743

&clk_mgr->base.base, &log_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

745

clk_mgr->base.base.dprefclk_khz = 600000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

746

clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

747

dce_clock_read_ss_info(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

751

clk_mgr->base.base.bw_params = &dcn31_bw_params;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

753

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

756

dcn31_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

799

&clk_mgr->base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

806

dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

812

struct clk_mgr_dcn31 *clk_mgr = TO_CLK_MGR_DCN31(clk_mgr_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

814

if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

816

clk_mgr->smu_wm_set.wm_set);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h

44

void dcn31_init_clocks(struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h

45

void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h

50

struct clk_mgr_dcn31 *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h

54

int dcn31_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

103

static int dcn31_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

109

result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

127

result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

147

int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

150

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

156

int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

160

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

165

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

172

int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

176

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

177

return clk_mgr->base.dprefclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

180

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

182

khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

189

int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

193

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

196

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

200

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

207

int dcn31_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

211

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

214

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

218

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

225

int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

229

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

233

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

240

void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

242

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

245

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

250

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

255

void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

259

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

268

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

273

void dcn31_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

275

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

279

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

284

void dcn31_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

286

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

289

dcn31_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

293

void dcn31_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

295

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

298

dcn31_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

302

void dcn31_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

304

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

307

dcn31_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

311

void dcn31_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

313

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

316

dcn31_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

320

void dcn31_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

324

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

327

if (!clk_mgr->base.ctx->dc->debug.enable_z9_disable_interface &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

343

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

350

void dcn31_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

352

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

356

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

85

static uint32_t dcn31_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

254

int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

255

int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

256

int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

257

int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

258

int dcn31_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

259

int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

260

void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

261

void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

262

void dcn31_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

263

void dcn31_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

264

void dcn31_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

265

void dcn31_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

266

void dcn31_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

268

void dcn31_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

269

void dcn31_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

107

#define TO_CLK_MGR_DCN314(clk_mgr)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

108

container_of(clk_mgr, struct clk_mgr_dcn314, base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

151

static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

177

bool dcn314_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

179

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

187

void dcn314_init_clocks(struct clk_mgr *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

189

struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

190

uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

192

memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

194

clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

195

clk_mgr->clks.p_state_change_support = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

196

clk_mgr->clks.prev_p_state_change_support = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

197

clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

198

clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

201

if (dcn314_is_spll_ssc_enabled(clk_mgr))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

202

clk_mgr->dp_dto_source_clock_in_khz =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

203

dce_adjust_dp_ref_freq_for_ss(clk_mgr_int, clk_mgr->dprefclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

205

clk_mgr->dp_dto_source_clock_in_khz = clk_mgr->dprefclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

208

void dcn314_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

213

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

232

dcn314_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

237

dcn314_smu_set_dtbclk(clk_mgr, false);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

248

dcn314_smu_set_display_idle_optimization(clk_mgr, idle_info.data);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

256

dcn314_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

261

dcn314_smu_set_dtbclk(clk_mgr, true);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

269

dcn314_smu_set_display_idle_optimization(clk_mgr, idle_info.data);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

277

dcn314_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

283

dcn314_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

290

if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

291

if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

307

dcn314_smu_set_dispclk(clk_mgr, requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

316

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

317

dcn314_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

321

dcn314_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

324

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

340

static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

364

pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

370

static void dcn314_enable_pme_wa(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

372

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

374

dcn314_smu_enable_pme_wa(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

397

struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

554

static void dcn314_notify_wm_ranges(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

556

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

557

struct clk_mgr_dcn314 *clk_mgr_dcn314 = TO_CLK_MGR_DCN314(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

560

if (!clk_mgr->smu_ver)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

570

dcn314_smu_set_dram_addr_high(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

572

dcn314_smu_set_dram_addr_low(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

574

dcn314_smu_transfer_wm_table_dram_2_smu(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

577

static void dcn314_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

582

if (!clk_mgr->smu_ver)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

590

dcn314_smu_set_dram_addr_high(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

592

dcn314_smu_set_dram_addr_low(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

594

dcn314_smu_transfer_dpm_table_smu_2_dram(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

630

static void dcn314_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

634

struct clk_bw_params *bw_params = clk_mgr->base.bw_params;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

779

static void dcn314_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

787

if (dcn314_is_spll_ssc_enabled(&clk_mgr->base) && (clock_source < ARRAY_SIZE(ss_info_table.ss_percentage))) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

788

clk_mgr->dprefclk_ss_percentage = ss_info_table.ss_percentage[clock_source];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

79

clk_mgr->base.base.ctx->logger

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

790

if (clk_mgr->dprefclk_ss_percentage != 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

791

clk_mgr->ss_on_dprefclk = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

792

clk_mgr->dprefclk_ss_divider = ss_info_table.ss_divider;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

799

struct clk_mgr_dcn314 *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

806

clk_mgr->base.base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

807

clk_mgr->base.base.funcs = &dcn314_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

809

clk_mgr->base.pp_smu = pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

811

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

812

clk_mgr->base.dfs_bypass_disp_clk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

814

clk_mgr->base.dprefclk_ss_percentage = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

815

clk_mgr->base.dprefclk_ss_divider = 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

816

clk_mgr->base.ss_on_dprefclk = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

817

clk_mgr->base.dfs_ref_freq_khz = 48000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

819

clk_mgr->smu_wm_set.wm_set = (struct dcn314_watermarks *)dm_helpers_allocate_gpu_mem(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

820

clk_mgr->base.base.ctx,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

823

&clk_mgr->smu_wm_set.mc_address.quad_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

825

if (!clk_mgr->smu_wm_set.wm_set) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

826

clk_mgr->smu_wm_set.wm_set = &dummy_wms;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

827

clk_mgr->smu_wm_set.mc_address.quad_part = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

829

ASSERT(clk_mgr->smu_wm_set.wm_set);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

832

clk_mgr->base.base.ctx,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

844

clk_mgr->base.smu_ver = dcn314_smu_get_smu_version(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

846

if (clk_mgr->base.smu_ver)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

847

clk_mgr->base.smu_present = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

850

clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

859

dcn314_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

860

&clk_mgr->base.base, &log_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

862

clk_mgr->base.base.dprefclk_khz = 600000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

863

clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

864

dce_clock_read_ss_info(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

865

dcn314_read_ss_info_from_lut(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

868

clk_mgr->base.base.bw_params = &dcn314_bw_params;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

870

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

873

dcn314_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

916

&clk_mgr->base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

923

dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

929

struct clk_mgr_dcn314 *clk_mgr = TO_CLK_MGR_DCN314(clk_mgr_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

931

if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

933

clk_mgr->smu_wm_set.wm_set);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h

53

bool dcn314_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h

55

void dcn314_init_clocks(struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h

57

void dcn314_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h

62

struct clk_mgr_dcn314 *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

101

static uint32_t dcn314_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

119

static int dcn314_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

125

result = dcn314_smu_wait_for_response(clk_mgr, 10, 200000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

143

result = dcn314_smu_wait_for_response(clk_mgr, 10, 200000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

166

int dcn314_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

169

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

175

int dcn314_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

179

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

184

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

191

int dcn314_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

195

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

196

return clk_mgr->base.dprefclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

199

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

201

khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

208

int dcn314_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

212

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

215

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

219

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

226

int dcn314_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

230

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

233

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

237

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

244

int dcn314_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

248

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

252

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

259

void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

261

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

264

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

269

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

274

void dcn314_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

278

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

287

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

292

void dcn314_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

294

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

298

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

303

void dcn314_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

305

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

308

dcn314_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

312

void dcn314_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

314

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

317

dcn314_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

321

void dcn314_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

323

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

326

dcn314_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

330

void dcn314_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

332

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

335

dcn314_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

339

void dcn314_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

343

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

382

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

389

void dcn314_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

391

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

395

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

100

void dcn314_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

101

void dcn314_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

102

void dcn314_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

103

void dcn314_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

104

void dcn314_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

105

void dcn314_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

107

void dcn314_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

108

void dcn314_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

93

int dcn314_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

94

int dcn314_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

95

int dcn314_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

96

int dcn314_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

97

int dcn314_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

98

int dcn314_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.h

99

void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

103

static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

128

static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

133

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

152

dcn315_smu_set_dtbclk(clk_mgr, false);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

163

dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

170

dcn315_smu_set_dtbclk(clk_mgr, true);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

176

dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

187

dcn315_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

193

dcn315_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

200

if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

201

if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

217

dcn315_smu_set_dispclk(clk_mgr, requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

226

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

227

dcn315_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

231

dcn315_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

234

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

251

struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

446

static void dcn315_notify_wm_ranges(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

448

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

449

struct clk_mgr_dcn315 *clk_mgr_dcn315 = TO_CLK_MGR_DCN315(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

452

if (!clk_mgr->smu_ver)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

462

dcn315_smu_set_dram_addr_high(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

464

dcn315_smu_set_dram_addr_low(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

466

dcn315_smu_transfer_wm_table_dram_2_smu(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

469

static void dcn315_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

47

clk_mgr->base.base.ctx->logger

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

474

if (!clk_mgr->smu_ver)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

482

dcn315_smu_set_dram_addr_high(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

484

dcn315_smu_set_dram_addr_low(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

486

dcn315_smu_transfer_dpm_table_smu_2_dram(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

490

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

496

struct clk_bw_params *bw_params = clk_mgr->base.bw_params;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

51

#define TO_CLK_MGR_DCN315(clk_mgr)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

52

container_of(clk_mgr, struct clk_mgr_dcn315, base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

595

static void dcn315_enable_pme_wa(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

597

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

599

dcn315_smu_enable_pme_wa(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

615

struct clk_mgr_dcn315 *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

622

clk_mgr->base.base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

623

clk_mgr->base.base.funcs = &dcn315_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

625

clk_mgr->base.pp_smu = pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

627

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

628

clk_mgr->base.dfs_bypass_disp_clk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

630

clk_mgr->base.dprefclk_ss_percentage = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

631

clk_mgr->base.dprefclk_ss_divider = 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

632

clk_mgr->base.ss_on_dprefclk = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

633

clk_mgr->base.dfs_ref_freq_khz = 48000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

635

clk_mgr->smu_wm_set.wm_set = (struct dcn315_watermarks *)dm_helpers_allocate_gpu_mem(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

636

clk_mgr->base.base.ctx,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

639

&clk_mgr->smu_wm_set.mc_address.quad_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

641

if (!clk_mgr->smu_wm_set.wm_set) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

642

clk_mgr->smu_wm_set.wm_set = &dummy_wms;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

643

clk_mgr->smu_wm_set.mc_address.quad_part = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

645

ASSERT(clk_mgr->smu_wm_set.wm_set);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

648

clk_mgr->base.base.ctx,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

660

clk_mgr->base.smu_ver = dcn315_smu_get_smu_version(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

662

if (clk_mgr->base.smu_ver > 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

663

clk_mgr->base.smu_present = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

672

dcn315_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

673

&clk_mgr->base.base, &log_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

675

clk_mgr->base.base.dprefclk_khz = 600000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

676

clk_mgr->base.base.dprefclk_khz = dcn315_smu_get_dpref_clk(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

677

clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

678

dce_clock_read_ss_info(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

679

clk_mgr->base.base.clks.ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

681

clk_mgr->base.base.bw_params = &dcn315_bw_params;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

683

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

686

dcn315_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

729

&clk_mgr->base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

736

dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

742

struct clk_mgr_dcn315 *clk_mgr = TO_CLK_MGR_DCN315(clk_mgr_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

744

if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

746

clk_mgr->smu_wm_set.wm_set);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h

43

struct clk_mgr_dcn315 *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

114

static uint32_t dcn315_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

133

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

140

result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

167

result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

177

int dcn315_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

180

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

186

int dcn315_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

190

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

195

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

202

int dcn315_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

206

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

209

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

213

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

220

int dcn315_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

224

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

227

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

231

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

238

int dcn315_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

242

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

246

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

253

void dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

255

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

258

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

263

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

268

void dcn315_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

272

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

281

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

286

void dcn315_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

288

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

292

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

296

void dcn315_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

298

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

301

dcn315_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

305

void dcn315_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

307

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

310

dcn315_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

314

void dcn315_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

316

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

319

dcn315_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

323

void dcn315_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

325

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

328

dcn315_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

332

int dcn315_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

335

if (clk_mgr->smu_present) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

337

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

344

int dcn315_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

348

if (clk_mgr->smu_present) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

350

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

357

void dcn315_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

359

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

363

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

53

#define CTX clk_mgr->base.ctx

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

114

int dcn315_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

115

int dcn315_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

116

int dcn315_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

117

int dcn315_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

118

int dcn315_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

119

void dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

120

void dcn315_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

121

void dcn315_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

122

void dcn315_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

123

void dcn315_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

124

void dcn315_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

125

void dcn315_smu_request_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

126

void dcn315_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

127

int dcn315_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

128

int dcn315_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h

129

void dcn315_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

105

static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

131

static void dcn316_enable_pme_wa(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

133

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

135

dcn316_smu_enable_pme_wa(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

138

static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

143

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

161

dcn316_smu_set_dtbclk(clk_mgr, false);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

173

dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

180

dcn316_smu_set_dtbclk(clk_mgr, true);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

187

dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

195

dcn316_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

201

dcn316_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

208

if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

209

if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

225

dcn316_smu_set_dispclk(clk_mgr, requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

234

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

235

dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

239

dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

242

dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

259

struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

412

static void dcn316_notify_wm_ranges(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

414

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

415

struct clk_mgr_dcn316 *clk_mgr_dcn316 = TO_CLK_MGR_DCN316(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

418

if (!clk_mgr->smu_ver)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

428

dcn316_smu_set_dram_addr_high(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

430

dcn316_smu_set_dram_addr_low(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

432

dcn316_smu_transfer_wm_table_dram_2_smu(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

435

static void dcn316_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

440

if (!clk_mgr->smu_ver)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

448

dcn316_smu_set_dram_addr_high(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

450

dcn316_smu_set_dram_addr_low(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

452

dcn316_smu_transfer_dpm_table_smu_2_dram(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

492

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

498

struct clk_bw_params *bw_params = clk_mgr->base.bw_params;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

590

struct clk_mgr_dcn316 *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

597

clk_mgr->base.base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

598

clk_mgr->base.base.funcs = &dcn316_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

600

clk_mgr->base.pp_smu = pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

602

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

603

clk_mgr->base.dfs_bypass_disp_clk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

605

clk_mgr->base.dprefclk_ss_percentage = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

606

clk_mgr->base.dprefclk_ss_divider = 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

607

clk_mgr->base.ss_on_dprefclk = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

608

clk_mgr->base.dfs_ref_freq_khz = 48000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

610

clk_mgr->smu_wm_set.wm_set = (struct dcn316_watermarks *)dm_helpers_allocate_gpu_mem(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

611

clk_mgr->base.base.ctx,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

614

&clk_mgr->smu_wm_set.mc_address.quad_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

616

if (!clk_mgr->smu_wm_set.wm_set) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

617

clk_mgr->smu_wm_set.wm_set = &dummy_wms;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

618

clk_mgr->smu_wm_set.mc_address.quad_part = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

620

ASSERT(clk_mgr->smu_wm_set.wm_set);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

623

clk_mgr->base.base.ctx,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

635

clk_mgr->base.smu_ver = dcn316_smu_get_smu_version(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

637

if (clk_mgr->base.smu_ver > 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

638

clk_mgr->base.smu_present = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

642

clk_mgr->base.base.dentist_vco_freq_khz = 2500000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

645

if (clk_mgr->base.base.dentist_vco_freq_khz == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

646

clk_mgr->base.base.dentist_vco_freq_khz = 2500000; /* 2400MHz */

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

656

dcn316_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

657

&clk_mgr->base.base, &log_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

659

clk_mgr->base.base.dprefclk_khz = 600000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

66

#define TO_CLK_MGR_DCN316(clk_mgr)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

660

clk_mgr->base.base.dprefclk_khz = dcn316_smu_get_dpref_clk(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

661

clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

662

dce_clock_read_ss_info(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

666

clk_mgr->base.base.bw_params = &dcn316_bw_params;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

668

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

669

dcn316_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

67

container_of(clk_mgr, struct clk_mgr_dcn316, base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

673

&clk_mgr->base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

680

dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

686

struct clk_mgr_dcn316 *clk_mgr = TO_CLK_MGR_DCN316(clk_mgr_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

688

if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

690

clk_mgr->smu_wm_set.wm_set);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.h

43

struct clk_mgr_dcn316 *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

100

static uint32_t dcn316_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

119

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

124

result = dcn316_smu_wait_for_response(clk_mgr, 10, 200000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

142

result = dcn316_smu_wait_for_response(clk_mgr, 10, 200000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

152

int dcn316_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

155

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

161

int dcn316_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

165

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

170

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

177

int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

181

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

184

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

188

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

195

int dcn316_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

199

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

202

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

206

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

213

int dcn316_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

217

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

221

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

228

void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

230

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

233

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

238

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

243

void dcn316_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

247

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

256

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

261

void dcn316_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

263

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

266

dcn316_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

270

void dcn316_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

272

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

275

dcn316_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

279

void dcn316_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

281

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

284

dcn316_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

288

void dcn316_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

290

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

293

dcn316_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

297

void dcn316_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

299

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

303

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

309

void dcn316_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

311

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

315

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

320

int dcn316_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

324

if (clk_mgr->smu_present) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

326

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

333

int dcn316_smu_get_smu_fclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

337

if (clk_mgr->smu_present) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

339

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

122

int dcn316_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

123

int dcn316_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

124

int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

125

int dcn316_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

126

int dcn316_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

127

void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

128

void dcn316_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

129

void dcn316_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

130

void dcn316_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

131

void dcn316_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

132

void dcn316_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

133

void dcn316_smu_request_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

134

void dcn316_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

135

void dcn316_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

136

int dcn316_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

137

int dcn316_smu_get_smu_fclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1001

if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1003

table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1005

dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1006

dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1007

dcn32_smu_transfer_wm_table_dram_2_smu(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1011

static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1013

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1015

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1020

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1023

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1026

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1032

static void dcn32_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1034

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1036

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1039

dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)clk_mgr_base->bw_params->max_memclk_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1043

static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1045

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1049

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1053

dcn32_init_single_clock(clk_mgr, PPCLK_UCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1056

clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1062

dcn32_init_single_clock(clk_mgr, PPCLK_FCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1065

clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1073

if (clk_mgr->dpm_present && !num_levels)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1074

clk_mgr->dpm_present = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1076

if (!clk_mgr->dpm_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1081

clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1105

static void dcn32_enable_pme_wa(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1107

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1109

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1112

dcn32_smu_set_pme_workaround(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1115

static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1117

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1118

return clk_mgr->smu_present;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1121

static void dcn32_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1123

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1125

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1128

dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1131

static void dcn32_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1133

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1135

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1138

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1161

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1168

clk_mgr->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1169

clk_mgr->base.funcs = &dcn32_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1170

if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1171

clk_mgr->regs = &clk_mgr_regs_dcn321;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1172

clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn321;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1173

clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn321;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1175

clk_mgr->regs = &clk_mgr_regs_dcn32;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1176

clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn32;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1177

clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn32;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1180

clk_mgr->dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1181

clk_mgr->dfs_bypass_disp_clk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1183

clk_mgr->dprefclk_ss_percentage = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1184

clk_mgr->dprefclk_ss_divider = 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1185

clk_mgr->ss_on_dprefclk = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1186

clk_mgr->dfs_ref_freq_khz = 100000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1192

clk_mgr->base.dprefclk_khz = 716666;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1196

clk_mgr->base.clks.ref_dtbclk_khz = 477800;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1198

clk_mgr->base.clks.ref_dtbclk_khz = 268750;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1203

clk_mgr->base.dentist_vco_freq_khz = dcn32_get_vco_frequency_from_reg(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1206

if (clk_mgr->base.dentist_vco_freq_khz == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1207

clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1209

dcn32_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1212

clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1213

clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1216

if (clk_mgr->base.boot_snapshot.dprefclk != 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1217

clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1219

dcn32_clock_read_ss_info(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1221

clk_mgr->dfs_bypass_enabled = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1223

clk_mgr->smu_present = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1225

clk_mgr->base.bw_params = kzalloc_obj(*clk_mgr->base.bw_params);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1226

if (!clk_mgr->base.bw_params) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1232

clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1234

&clk_mgr->wm_range_table_addr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1235

if (!clk_mgr->wm_range_table) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1241

void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1243

kfree(clk_mgr->base.bw_params);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1245

if (clk_mgr->wm_range_table)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1246

dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1247

clk_mgr->wm_range_table);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

132

static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

138

uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

150

*((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

151

entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

155

static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

158

dcn32_build_wm_range_table_fpu(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

162

void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

164

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

178

clk_mgr->smu_present = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

179

clk_mgr->dpm_present = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

181

if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

182

clk_mgr->smu_present = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

184

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

187

dcn30_smu_check_driver_if_version(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

188

dcn30_smu_check_msg_header_version(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

191

dcn32_init_single_clock(clk_mgr, PPCLK_DCFCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

194

clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

197

dcn32_init_single_clock(clk_mgr, PPCLK_SOCCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

200

clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

203

if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

204

dcn32_init_single_clock(clk_mgr, PPCLK_DTBCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

208

dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DTBCLK);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

212

dcn32_init_single_clock(clk_mgr, PPCLK_DISPCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

216

clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

222

dcn32_init_single_clock(clk_mgr, PPCLK_DPPCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

226

clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DPPCLK);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

234

clk_mgr->dpm_present = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

263

dcn32_build_wm_range_table(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

266

static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

270

struct dccg *dccg = clk_mgr->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

274

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

298

dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

309

static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

316

* clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

317

new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

321

* clk_mgr->base.dentist_vco_freq_khz / new_clocks->dispclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

322

new_clocks->dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

326

void dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

331

clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

332

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

352

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

355

clk_mgr->dccg->funcs->update_dpp_dto(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

356

clk_mgr->dccg, dpp_inst, dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

361

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

369

struct dc *dc = clk_mgr->base.ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

371

if (clk_mgr->base.clks.dispclk_khz == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

375

* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

383

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

386

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

413

uint32_t temp_dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / temp_disp_divider;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

415

if (clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

423

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

437

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

439

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

462

if (clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

470

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

471

(uint16_t)khz_to_mhz_floor(clk_mgr->base.clks.dispclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

486

static int dcn32_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

488

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

497

return (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

519

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

553

num_fclk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

556

dramclk_khz_override = clk_mgr->base.bw_params->max_memclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

559

fclk_khz_override = clk_mgr->base.bw_params->clk_table.entries[num_fclk_levels].fclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

633

static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

637

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

669

if (clk_mgr->smu_present) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

671

dcn30_smu_set_num_of_displays(clk_mgr, display_count);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

684

dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

698

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

704

dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

717

dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

727

if (dc->clk_mgr->dc_mode_softmax_enabled) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

733

dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)dc->clk_mgr->bw_params->max_memclk_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

734

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)dc->clk_mgr->bw_params->max_memclk_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

736

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

737

(uint16_t)dc->clk_mgr->bw_params->dc_mode_softmax_memclk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

739

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)dc->clk_mgr->bw_params->max_memclk_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

745

dcn32_smu_wait_for_dmub_ack_mclk(clk_mgr, true);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

747

dcn32_smu_wait_for_dmub_ack_mclk(clk_mgr, false);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

757

dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

771

if (dc->clk_mgr->dc_mode_softmax_enabled && dc->debug.disable_dc_mode_overwrite)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

772

dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

773

(uint16_t)max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

776

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

782

dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

786

dcn32_update_dppclk_dispclk_freq(clk_mgr, new_clocks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

793

if (clk_mgr->smu_present && !dpp_clock_lowered)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

801

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

822

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, (uint16_t)khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

824

dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

830

dcn32_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

831

dcn32_update_clocks_update_dentist(clk_mgr, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

832

if (clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

840

dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

845

dcn32_update_clocks_update_dentist(clk_mgr, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

850

dcn32_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

86

clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

860

dcn32_auto_dpm_test_log(new_clocks, clk_mgr, context);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

864

static uint32_t dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

870

if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

879

pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

880

pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

883

pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

889

struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

89

(clk_mgr->regs->reg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

892

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

900

if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

928

* clk_mgr->base.dentist_vco_freq_khz) / target_div;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

934

* clk_mgr->base.dentist_vco_freq_khz) / target_div;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

940

* clk_mgr->base.dentist_vco_freq_khz) / target_div;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

946

* clk_mgr->base.dentist_vco_freq_khz) / target_div;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

952

* clk_mgr->base.dentist_vco_freq_khz) / target_div;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

955

static void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

957

struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

971

clk_mgr->ss_on_dprefclk = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

972

clk_mgr->dprefclk_ss_divider = info.spread_percentage_divider;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

979

clk_mgr->dprefclk_ss_percentage =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

985

static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

988

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

989

WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

991

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h

28

void dcn32_init_clocks(struct clk_mgr *clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h

31

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h

35

void dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h

38

void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

107

static uint32_t dcn32_smu_wait_for_response_delay(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries, unsigned int *total_delay_us)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

124

TRACE_SMU_MSG_DELAY(0, 0, *total_delay_us, clk_mgr->base.ctx);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

129

static bool dcn32_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out, unsigned int *total_delay_us)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

135

dcn32_smu_wait_for_response_delay(clk_mgr, 10, 200000, &delay1_us);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

146

TRACE_SMU_MSG(msg_id, param_in, clk_mgr->base.ctx);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

149

if (dcn32_smu_wait_for_response_delay(clk_mgr, 10, 200000, &delay2_us) == DALSMC_Result_OK) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

161

void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

165

dcn32_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

169

void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

173

dcn32_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_SetCabForUclkPstate, param, NULL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

177

void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

181

dcn32_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

185

void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

189

dcn32_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

194

static bool dcn32_get_hard_min_status_supported(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

196

if (ASICREV_IS_GC_11_0_0(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

197

if (clk_mgr->smu_ver >= 0x4e6a00)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

199

} else if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

200

if (clk_mgr->smu_ver >= 0x524e00)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

203

if (clk_mgr->smu_ver >= 0x503900)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

210

static unsigned int dcn32_smu_get_hard_min_status(struct clk_mgr_internal *clk_mgr, bool *no_timeout, unsigned int *total_delay_us)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

217

*no_timeout = dcn32_smu_send_msg_with_param_delay(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

226

static bool dcn32_smu_wait_get_hard_min_status(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

254

readDalHardMinClkBits = dcn32_smu_get_hard_min_status(clk_mgr, &no_timeout, &read_total_delay_us);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

281

unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

291

dcn32_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

294

if (dcn32_get_hard_min_status_supported(clk_mgr)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

295

hard_min_done = dcn32_smu_wait_get_hard_min_status(clk_mgr, clk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

303

void dcn32_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

307

dcn32_smu_send_msg_with_param(clk_mgr, 0x14, enable ? 1 : 0, NULL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

50

static uint32_t dcn32_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

66

TRACE_SMU_MSG_DELAY(0, 0, delay_us * (initial_max_retries - max_retries), clk_mgr->base.ctx);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

72

static bool dcn32_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

75

dcn32_smu_wait_for_response(clk_mgr, 10, 200000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

86

TRACE_SMU_MSG(msg_id, param_in, clk_mgr->base.ctx);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

89

if (dcn32_smu_wait_for_response(clk_mgr, 10, 200000) == DALSMC_Result_OK) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h

39

void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h

40

void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h

41

void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h

42

void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h

43

unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h

44

void dcn32_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

122

#define TO_CLK_MGR_DCN35(clk_mgr)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

123

container_of(clk_mgr, struct clk_mgr_dcn35, base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

128

struct clk_mgr_dcn35 *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

133

clk_mgr->base.regs = &clk_mgr_regs_dcn351;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

134

clk_mgr->base.clk_mgr_shift = &clk_mgr_shift_dcn351;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

135

clk_mgr->base.clk_mgr_mask = &clk_mgr_mask_dcn351;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

137

dcn35_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

97

(clk_mgr->regs->reg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1039

static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1043

struct clk_bw_params *bw_params = clk_mgr->base.bw_params;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1213

static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1227

static void dcn35_exit_low_power_state(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1229

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1232

dcn35_smu_exit_low_power_state(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1236

static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1238

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1240

return dcn35_smu_get_ips_supported(clk_mgr) ? true : false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1243

static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1245

init_clk_states(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

125

clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1250

static void dcn35_update_clocks_fpga(struct clk_mgr *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1254

struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1266

if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1267

clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1270

if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1271

clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1275

new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1276

clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1279

if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

128

(clk_mgr->regs->reg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1280

clk_mgr->clks.socclk_khz = new_clocks->socclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1283

if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1284

clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1287

if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1288

clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1291

if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1292

clk_mgr->clks.fclk_khz = fclk_adj;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1295

if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1296

clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1303

if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1304

clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1305

if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1306

clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1309

clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1312

clk_mgr->clks.dtbclk_en = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1313

dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1316

dcn35_update_clocks_update_dtb_dto(clk_mgr_int, context, clk_mgr->clks.ref_dtbclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1319

static unsigned int dcn35_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1321

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1327

num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1329

clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 :

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1330

clk_mgr->base.boot_snapshot.dispclk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1332

num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1334

clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dppclk_mhz * 1000 :

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1335

clk_mgr->base.boot_snapshot.dppclk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1337

num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1339

clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 / 3 :

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1340

clk_mgr->base.boot_snapshot.dispclk / 3;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1422

struct clk_mgr_dcn35 *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1428

clk_mgr->base.base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1429

clk_mgr->base.base.funcs = &dcn35_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1431

clk_mgr->base.pp_smu = pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1433

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1434

clk_mgr->base.dfs_bypass_disp_clk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1436

clk_mgr->base.dprefclk_ss_percentage = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1437

clk_mgr->base.dprefclk_ss_divider = 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1438

clk_mgr->base.ss_on_dprefclk = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1439

clk_mgr->base.dfs_ref_freq_khz = 48000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1441

clk_mgr->base.regs = &clk_mgr_regs_dcn35;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1442

clk_mgr->base.clk_mgr_shift = &clk_mgr_shift_dcn35;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1443

clk_mgr->base.clk_mgr_mask = &clk_mgr_mask_dcn35;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1447

clk_mgr->smu_wm_set.wm_set = (struct dcn35_watermarks *)dm_helpers_allocate_gpu_mem(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1448

clk_mgr->base.base.ctx,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1451

&clk_mgr->smu_wm_set.mc_address.quad_part);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1453

if (!clk_mgr->smu_wm_set.wm_set) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1454

clk_mgr->smu_wm_set.wm_set = &dummy_wms;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1455

clk_mgr->smu_wm_set.mc_address.quad_part = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1457

ASSERT(clk_mgr->smu_wm_set.wm_set);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1460

clk_mgr->base.base.ctx,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1472

clk_mgr->base.base.ctx,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1482

clk_mgr->base.smu_ver = dcn35_smu_get_smu_version(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1484

if (clk_mgr->base.smu_ver)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1485

clk_mgr->base.smu_present = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1488

clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1497

dcn35_save_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1499

clk_mgr->base.base.dprefclk_khz = dcn35_smu_get_dprefclk(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1500

clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1502

dce_clock_read_ss_info(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1505

dcn35_read_ss_info_from_lut(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1507

clk_mgr->base.base.bw_params = &dcn35_bw_params;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1509

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1512

dcn351_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks_dcn351);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1515

dcn35_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

153

#define TO_CLK_MGR_DCN35(clk_mgr)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

154

container_of(clk_mgr, struct clk_mgr_dcn35, base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1566

&clk_mgr->base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1573

dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_GART,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1577

dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_GART,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1584

ips_support = dcn35_smu_get_ips_supported(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1594

((clk_mgr->base.smu_ver & 0x00FFFFFF) <= 0x005d0c00))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1605

struct clk_mgr_dcn35 *clk_mgr = TO_CLK_MGR_DCN35(clk_mgr_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1607

if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1609

clk_mgr->smu_wm_set.wm_set);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

189

void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

256

static void dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

260

struct dccg *dccg = clk_mgr->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

264

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

288

dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

294

static void dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

301

clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

302

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

322

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

325

clk_mgr->dccg->funcs->update_dpp_dto(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

326

clk_mgr->dccg, dpp_inst, dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

330

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

331

struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

334

clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, old_dpp->inst, 0);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

355

static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct dc_state *context,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

359

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

386

dcn35_smu_notify_host_router_bw(clk_mgr, i, new_clocks->host_router_bw_kbps[i]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

391

void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

396

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

421

dcn35_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

427

if (clk_mgr->base.ctx->dc->config.allow_0_dtb_clk)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

428

dcn35_smu_set_dtbclk(clk_mgr, false);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

441

dcn35_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

449

dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

450

dcn35_smu_set_dtbclk(clk_mgr, true);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

464

dcn35_smu_set_display_idle_optimization(clk_mgr, idle_info.data);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

478

dcn35_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

484

dcn35_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

491

if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

492

if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

508

dcn35_smu_set_dispclk(clk_mgr, requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

52

clk_mgr->base.base.ctx->logger

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

520

dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

526

dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

527

dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

531

dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

532

dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

552

static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

576

pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

582

static void dcn35_enable_pme_wa(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

584

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

586

dcn35_smu_enable_pme_wa(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

609

static void dcn35_save_clk_registers_internal(struct dcn35_clk_internal *internal, struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

611

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

639

struct clk_mgr_dcn35 *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

644

dcn35_save_clk_registers_internal(&internal, &clk_mgr->base.base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

667

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

723

static bool dcn35_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

725

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

738

static void init_clk_states(struct clk_mgr *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

740

uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

742

memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

744

clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

745

clk_mgr->clks.p_state_change_support = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

746

clk_mgr->clks.prev_p_state_change_support = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

747

clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

748

clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

751

void dcn35_init_clocks(struct clk_mgr *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

753

struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

756

init_clk_states(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

759

if (dcn35_is_spll_ssc_enabled(clk_mgr))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

760

clk_mgr->dp_dto_source_clock_in_khz =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

761

dce_adjust_dp_ref_freq_for_ss(clk_mgr_int, clk_mgr->dprefclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

763

clk_mgr->dp_dto_source_clock_in_khz = clk_mgr->dprefclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

765

dcn35_save_clk_registers(&clk_mgr->boot_snapshot, clk_mgr_dcn35);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

767

clk_mgr->clks.ref_dtbclk_khz = clk_mgr->boot_snapshot.dtbclk * 10;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

768

if (clk_mgr->boot_snapshot.dtbclk > 59000) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

770

clk_mgr->clks.dtbclk_en = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

866

static void dcn35_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

873

if (dcn35_is_spll_ssc_enabled(&clk_mgr->base) && (clock_source < ARRAY_SIZE(ss_info_table.ss_percentage))) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

874

clk_mgr->dprefclk_ss_percentage = ss_info_table.ss_percentage[clock_source];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

876

if (clk_mgr->dprefclk_ss_percentage != 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

877

clk_mgr->ss_on_dprefclk = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

878

clk_mgr->dprefclk_ss_divider = ss_info_table.ss_divider;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

940

static void dcn35_notify_wm_ranges(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

942

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

943

struct clk_mgr_dcn35 *clk_mgr_dcn35 = TO_CLK_MGR_DCN35(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

946

if (!clk_mgr->smu_ver)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

956

dcn35_smu_set_dram_addr_high(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

958

dcn35_smu_set_dram_addr_low(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

960

dcn35_smu_transfer_wm_table_dram_2_smu(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

963

static void dcn35_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

968

if (!clk_mgr->smu_ver)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

976

dcn35_smu_set_dram_addr_high(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

978

dcn35_smu_set_dram_addr_low(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

980

dcn35_smu_transfer_dpm_table_smu_2_dram(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

983

static void dcn351_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

988

if (!clk_mgr->smu_ver)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

993

dcn35_smu_set_dram_addr_high(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

995

dcn35_smu_set_dram_addr_low(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

997

dcn35_smu_transfer_dpm_table_smu_2_dram(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

51

void dcn35_init_clocks(struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

52

void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

57

struct clk_mgr_dcn35 *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

64

struct clk_mgr_dcn35 *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

68

void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

115

static uint32_t dcn35_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

129

if (clk_mgr->base.ctx->dc->debug.disable_timeout)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

136

static int dcn35_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

142

result = dcn35_smu_wait_for_response(clk_mgr, 10, 2000000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

161

result = dcn35_smu_wait_for_response(clk_mgr, 10, 2000000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

176

result = dcn35_smu_wait_for_response(clk_mgr, 10, 2000000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

184

int dcn35_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

187

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

193

int dcn35_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

197

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

202

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

210

int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

214

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

215

return clk_mgr->base.dprefclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

218

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

220

khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

227

int dcn35_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

231

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

235

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

244

int dcn35_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

248

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

252

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

261

int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

265

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

269

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

278

void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

280

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

283

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

288

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

294

void dcn35_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

298

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

307

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

313

void dcn35_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

315

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

319

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

325

void dcn35_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

327

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

330

dcn35_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

334

void dcn35_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

336

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

339

dcn35_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

343

void dcn35_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

345

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

348

dcn35_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

352

void dcn35_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

354

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

357

dcn35_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

361

void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

365

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

409

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

415

int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

419

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

422

dprefclk = dcn35_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

430

int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

434

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

437

dtbclk = dcn35_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

445

void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

447

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

451

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

457

void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

459

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

463

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

469

int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

473

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

477

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

484

int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

488

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

492

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

500

void dcn35_smu_notify_host_router_bw(struct clk_mgr_internal *clk_mgr, uint32_t hr_id, uint32_t bw_kbps)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

507

dcn35_smu_send_msg_with_param(clk_mgr, VBIOSSMC_MSG_NotifyHostRouterBW, msg_data.all);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

196

int dcn35_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

197

int dcn35_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

198

int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

199

int dcn35_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

200

int dcn35_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

201

int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

202

void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

203

void dcn35_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

204

void dcn35_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

205

void dcn35_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

206

void dcn35_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

207

void dcn35_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

208

void dcn35_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

210

void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

211

void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

212

void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

214

int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

215

int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

216

int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

217

int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h

218

void dcn35_smu_notify_host_router_bw(struct clk_mgr_internal *clk_mgr, uint32_t hr_id, uint32_t bw_kbps);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

105

clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels > 1;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1085

struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

109

clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels > 1;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

115

ppclk_dpm_enabled &= clk_mgr->smu_present;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

120

static bool dcn401_is_ppclk_idle_dpm_enabled(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1242

static void dcn401_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

127

if (ASICREV_IS_GC_12_0_0_A0(clk_mgr->base.ctx->asic_id.hw_internal_rev) &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1274

static uint32_t dcn401_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

128

clk_mgr->smu_ver >= 0x681800) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1286

pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1287

pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1290

pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1295

static void dcn401_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1297

struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

130

} else if (ASICREV_IS_GC_12_0_1_A0(clk_mgr->base.ctx->asic_id.hw_internal_rev) &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

131

clk_mgr->smu_ver >= 0x661300) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1311

clk_mgr->ss_on_dprefclk = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1312

clk_mgr->dprefclk_ss_divider = info.spread_percentage_divider;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1319

clk_mgr->dprefclk_ss_percentage =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1325

static void dcn401_notify_wm_ranges(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1328

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1329

WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1331

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1341

if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1343

table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1345

dcn401_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1346

dcn401_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1347

dcn401_smu_transfer_wm_table_dram_2_smu(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1351

static void dcn401_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1353

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1354

const struct dc *dc = clk_mgr->base.ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1359

if (!clk_mgr->smu_present || !dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1384

static int dcn401_get_hard_min_memclk(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1386

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1388

return clk_mgr->base.ctx->dc->current_state->bw_ctx.bw.dcn.clk.dramclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

139

ppclk_idle_dpm_enabled &= clk_mgr->smu_present;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1391

static int dcn401_get_hard_min_fclk(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1393

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1395

return clk_mgr->base.ctx->dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1399

static void dcn401_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1401

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1405

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1409

dcn401_init_single_clock(clk_mgr, PPCLK_UCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1417

clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1423

dcn401_init_single_clock(clk_mgr, PPCLK_FCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1426

clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1435

if (clk_mgr->dpm_present && !num_levels)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1436

clk_mgr->dpm_present = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1438

clk_mgr_base->bw_params->num_channels = dcn401_smu_get_num_of_umc_channels(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

144

static bool dcn401_is_df_throttle_opt_enabled(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1449

clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1473

static void dcn401_enable_pme_wa(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1475

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1477

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

148

if (ASICREV_IS_GC_12_0_1_A0(clk_mgr->base.ctx->asic_id.hw_internal_rev) &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1480

dcn401_smu_set_pme_workaround(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1483

static bool dcn401_is_smu_present(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1485

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1486

return clk_mgr->smu_present;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

149

clk_mgr->smu_ver >= 0x663500) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1490

static int dcn401_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1492

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1496

if (clk_mgr->smu_present && dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DTBCLK)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

150

is_df_throttle_opt_enabled = !clk_mgr->base.ctx->dc->debug.force_subvp_df_throttle;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1507

static int dcn401_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1509

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1518

return (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1523

unsigned int dcn401_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1525

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

153

is_df_throttle_opt_enabled &= clk_mgr->smu_present;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1531

num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1532

return dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DISPCLK) ?

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1533

clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 :

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1534

clk_mgr->base.boot_snapshot.dispclk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1536

num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1537

return dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DPPCLK) ?

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1538

clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dppclk_mhz * 1000 :

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1539

clk_mgr->base.boot_snapshot.dppclk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1541

num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1542

return dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DISPCLK) ?

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1543

clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 / 3 :

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1544

clk_mgr->base.boot_snapshot.dispclk / 3;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1577

struct clk_mgr_internal *clk_mgr;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1582

clk_mgr = &clk_mgr401->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1583

clk_mgr->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1584

clk_mgr->base.funcs = &dcn401_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1585

clk_mgr->regs = &clk_mgr_regs_dcn401;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1586

clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn401;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1587

clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn401;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1589

clk_mgr->dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

159

static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1590

clk_mgr->dfs_bypass_disp_clk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1592

clk_mgr->dprefclk_ss_percentage = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1593

clk_mgr->dprefclk_ss_divider = 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1594

clk_mgr->ss_on_dprefclk = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1595

clk_mgr->dfs_ref_freq_khz = 100000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1601

clk_mgr->base.dprefclk_khz = 720000; //TODO update from VBIOS

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1604

clk_mgr->base.dentist_vco_freq_khz = dcn401_get_vco_frequency_from_reg(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1607

if (clk_mgr->base.dentist_vco_freq_khz == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1608

clk_mgr->base.dentist_vco_freq_khz = 4500000; //TODO Update from VBIOS

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1610

dcn401_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1613

clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1614

clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1617

if (clk_mgr->base.boot_snapshot.dprefclk != 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1618

clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1620

dcn401_clock_read_ss_info(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1622

clk_mgr->dfs_bypass_enabled = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1624

clk_mgr->smu_present = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1626

clk_mgr->base.bw_params = kzalloc_obj(*clk_mgr->base.bw_params);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1627

if (!clk_mgr->base.bw_params) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1634

clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1636

&clk_mgr->wm_range_table_addr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1637

if (!clk_mgr->wm_range_table) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1639

kfree(clk_mgr->base.bw_params);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1647

void dcn401_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1649

kfree(clk_mgr->base.bw_params);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

165

uint32_t ret = dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1651

if (clk_mgr->wm_range_table)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1652

dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1653

clk_mgr->wm_range_table);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

176

for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

177

*((unsigned int *)entry_i) = (dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, (uint8_t)i) & 0xFFFF);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

178

entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

182

static void dcn401_build_wm_range_table(struct clk_mgr *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

185

unsigned int min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

186

unsigned int min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

189

clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

190

clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

191

clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = (uint16_t)min_dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

192

clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

193

clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = (uint16_t)min_uclk_mhz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

194

clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

197

clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

201

if (clk_mgr->ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

202

clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

203

clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

204

clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_dcfclk = (uint16_t)min_dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

205

clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_dcfclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

206

clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_uclk = (uint16_t)min_uclk_mhz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

207

clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_uclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

209

clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

213

clk_mgr->bw_params->wm_table.nv_entries[WM_1B].valid = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

216

void dcn401_init_clocks(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

218

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

231

clk_mgr->smu_present = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

232

clk_mgr->dpm_present = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

234

if (!clk_mgr_base->force_smu_not_present && dcn401_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

235

clk_mgr->smu_present = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

237

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

240

dcn401_smu_check_driver_if_version(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

241

dcn401_smu_check_msg_header_version(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

244

dcn401_init_single_clock(clk_mgr, PPCLK_DCFCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

247

clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

253

dcn401_init_single_clock(clk_mgr, PPCLK_SOCCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

256

clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

262

if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

263

dcn401_init_single_clock(clk_mgr, PPCLK_DTBCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

266

clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DTBCLK);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

273

dcn401_init_single_clock(clk_mgr, PPCLK_DISPCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

276

clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

282

dcn401_init_single_clock(clk_mgr, PPCLK_DPPCLK,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

289

clk_mgr->dpm_present = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

314

bool dcn401_is_dc_mode_present(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

316

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

318

return clk_mgr->smu_present && clk_mgr->dpm_present &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

334

struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

337

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

363

* clk_mgr->base.dentist_vco_freq_khz) / target_div;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

369

* clk_mgr->base.dentist_vco_freq_khz) / target_div;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

375

* clk_mgr->base.dentist_vco_freq_khz) / target_div;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

381

* clk_mgr->base.dentist_vco_freq_khz) / target_div;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

387

* clk_mgr->base.dentist_vco_freq_khz) / target_div;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

393

* clk_mgr->base.dentist_vco_freq_khz) / target_div;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

413

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

438

dcn401_dump_clk_registers(&clk_register_dump, &clk_mgr->base, &log_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

44

clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

444

num_fclk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

447

dramclk_khz_override = clk_mgr->base.bw_params->max_memclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

450

fclk_khz_override = clk_mgr->base.bw_params->clk_table.entries[num_fclk_levels].fclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

47

(clk_mgr->regs->reg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

525

static void dcn401_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

531

struct dccg *dccg = clk_mgr->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

559

static void dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

564

clk_mgr->dccg->ref_dppclk = ref_dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

565

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

585

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

588

clk_mgr->dccg->funcs->update_dpp_dto(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

589

clk_mgr->dccg, dpp_inst, dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

593

static int dcn401_set_hard_min_by_freq_optimized(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, int requested_clk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

595

if (!clk_mgr->smu_present || !dcn401_is_ppclk_dpm_enabled(clk_mgr, clk))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

608

int actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, (uint16_t)khz_to_mhz_floor(requested_clk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

611

actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, (uint16_t)khz_to_mhz_ceil(requested_clk_khz));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

617

struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

624

struct dc *dc = clk_mgr->base.ctx->dc;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

626

if (clk_mgr->base.clks.dispclk_khz == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

630

* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

647

static void dcn401_execute_block_sequence(struct clk_mgr *clk_mgr_base, unsigned int num_steps)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

72

#define TO_DCN401_CLK_MGR(clk_mgr)\

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

73

container_of(clk_mgr, struct dcn401_clk_mgr, base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

75

static bool dcn401_is_ppclk_dpm_enabled(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

769

struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

82

clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_socclk_levels > 1;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

86

clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_memclk_levels > 1;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

90

clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels > 1;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

925

if (dc->clk_mgr->dc_mode_softmax_enabled) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

94

clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels > 1;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

98

clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels > 1;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

107

void dcn401_init_clocks(struct clk_mgr *clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

108

bool dcn401_is_dc_mode_present(struct clk_mgr *clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

113

void dcn401_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

115

unsigned int dcn401_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

112

static bool dcn401_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out, unsigned int *total_delay_us)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

118

dcn401_smu_wait_for_response_delay(clk_mgr, 10, 200000, &delay1_us);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

120

TRACE_SMU_MSG_ENTER(msg_id, param_in, clk_mgr->base.ctx);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

132

if (dcn401_smu_wait_for_response_delay(clk_mgr, 10, 200000, &delay2_us) == DALSMC_Result_OK) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

137

TRACE_SMU_MSG_EXIT(true, param_out ? *param_out : 0, clk_mgr->base.ctx);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

142

TRACE_SMU_MSG_EXIT(false, 0, clk_mgr->base.ctx);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

146

bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

150

if (dcn401_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

162

bool dcn401_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

168

if (dcn401_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

181

bool dcn401_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

187

if (dcn401_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

199

void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

203

dcn401_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

207

void dcn401_smu_send_uclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

211

dcn401_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

215

void dcn401_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

219

dcn401_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_SetCabForUclkPstate, param, NULL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

223

void dcn401_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

227

dcn401_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

231

void dcn401_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

235

dcn401_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

239

void dcn401_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

243

dcn401_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

247

void dcn401_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

251

dcn401_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

255

static unsigned int dcn401_smu_get_hard_min_status(struct clk_mgr_internal *clk_mgr, bool *no_timeout, unsigned int *total_delay_us)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

262

*no_timeout = dcn401_smu_send_msg_with_param_delay(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

271

static bool dcn401_smu_wait_hard_min_status(struct clk_mgr_internal *clk_mgr, uint32_t ppclk)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

292

hardmin_status = dcn401_smu_get_hard_min_status(clk_mgr, &no_timeout, &read_total_delay_us);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

301

unsigned int dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

311

dcn401_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

315

hard_min_done = dcn401_smu_wait_hard_min_status(clk_mgr, clk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

321

void dcn401_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

325

dcn401_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_SetAlwaysWaitDmcubResp, enable ? 1 : 0, NULL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

328

void dcn401_smu_indicate_drr_status(struct clk_mgr_internal *clk_mgr, bool mod_drr_for_pstate)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

332

dcn401_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

336

bool dcn401_smu_set_idle_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

348

success = dcn401_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

352

success &= dcn401_smu_wait_hard_min_status(clk_mgr, PPCLK_UCLK);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

358

bool dcn401_smu_set_active_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

37

static uint32_t dcn401_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

370

success = dcn401_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

374

success &= dcn401_smu_wait_hard_min_status(clk_mgr, PPCLK_UCLK);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

380

bool dcn401_smu_set_subvp_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

392

success = dcn401_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

398

void dcn401_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

402

dcn401_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

406

void dcn401_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

410

dcn401_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

414

unsigned int dcn401_smu_get_num_of_umc_channels(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

418

dcn401_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_GetNumUmcChannels, 0, &response);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

439

unsigned int dcn401_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

448

dcn401_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

457

unsigned int dcn401_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

466

dcn401_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

55

static bool dcn401_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

58

dcn401_smu_wait_for_response(clk_mgr, 10, 200000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

60

TRACE_SMU_MSG_ENTER(msg_id, param_in, clk_mgr->base.ctx);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

72

if (dcn401_smu_wait_for_response(clk_mgr, 10, 200000) == DALSMC_Result_OK) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

76

TRACE_SMU_MSG_EXIT(true, param_out ? *param_out : 0, clk_mgr->base.ctx);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

80

TRACE_SMU_MSG_EXIT(false, 0, clk_mgr->base.ctx);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

92

static uint32_t dcn401_smu_wait_for_response_delay(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries, unsigned int *total_delay_us)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

13

bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

14

bool dcn401_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

15

bool dcn401_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

16

void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

17

void dcn401_smu_send_uclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

18

void dcn401_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

19

void dcn401_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

20

void dcn401_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

21

void dcn401_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

22

void dcn401_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

23

unsigned int dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

24

void dcn401_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

25

void dcn401_smu_indicate_drr_status(struct clk_mgr_internal *clk_mgr, bool mod_drr_for_pstate);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

26

bool dcn401_smu_set_idle_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

29

bool dcn401_smu_set_active_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

32

bool dcn401_smu_set_subvp_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

35

void dcn401_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

36

void dcn401_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

37

unsigned int dcn401_smu_get_num_of_umc_channels(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

38

unsigned int dcn401_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h

39

unsigned int dcn401_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1046

struct clk_mgr_dcn42 *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1050

clk_mgr->base.base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1051

clk_mgr->base.base.funcs = &dcn42_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1052

clk_mgr->base.regs = &clk_mgr_regs_dcn42;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1053

clk_mgr->base.clk_mgr_shift = &clk_mgr_shift_dcn42;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1054

clk_mgr->base.clk_mgr_mask = &clk_mgr_mask_dcn42;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1056

clk_mgr->base.pp_smu = pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1058

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1059

clk_mgr->base.dfs_bypass_disp_clk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1061

clk_mgr->base.dprefclk_ss_percentage = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1062

clk_mgr->base.dprefclk_ss_divider = 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1063

clk_mgr->base.ss_on_dprefclk = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1064

clk_mgr->base.dfs_ref_freq_khz = 48000; /*sync with pmfw*/

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1065

clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1071

clk_mgr->base.base.dprefclk_khz = 600000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1073

clk_mgr->base.smu_present = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1074

clk_mgr->base.smu_ver = dcn42_smu_get_pmfw_version(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1075

if (clk_mgr->base.smu_ver && clk_mgr->base.smu_ver != -1)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1076

clk_mgr->base.smu_present = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1079

clk_mgr->base.base.dentist_vco_freq_khz = ctx->dc_bios->integrated_info->dentist_vco_freq;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1084

if (clk_mgr->base.smu_present) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1085

clk_mgr->base.base.clks.ref_dtbclk_khz = dcn42_smu_get_dtbclk(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1086

clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1088

clk_mgr->base.base.bw_params = &dcn42_bw_params;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1090

if (clk_mgr->base.smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1091

dcn42_get_smu_clocks(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1094

if (clk_mgr->base.base.dentist_vco_freq_khz == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1095

clk_mgr->base.base.dentist_vco_freq_khz = 3000000; /* 3000MHz */

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1098

dcn42_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1100

dce_clock_read_ss_info(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1103

dcn42_read_ss_info_from_lut(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1105

clk_mgr->base.base.bw_params = &dcn42_bw_params;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1106

if (clk_mgr->base.smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1107

dcn42_get_smu_clocks(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1112

struct clk_mgr_dcn42 *clk_mgr = TO_CLK_MGR_DCN42(clk_mgr_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1114

if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1116

clk_mgr->smu_wm_set.wm_set);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1117

clk_mgr->smu_wm_set.wm_set = NULL;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1118

clk_mgr->smu_wm_set.mc_address.quad_part = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

114

static uint32_t dcn42_get_clock_freq_from_clkip(struct clk_mgr *clk_mgr_base, enum clock_type clock)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

116

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

157

void dcn42_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

161

(void)clk_mgr;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

167

void dcn42_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

174

clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

175

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

195

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

198

clk_mgr->dccg->funcs->update_dpp_dto(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

199

clk_mgr->dccg, dpp_inst, dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

203

for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

204

struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

207

clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, old_dpp->inst, 0);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

211

void dcn42_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

216

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

238

dcn42_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

243

if (clk_mgr->base.ctx->dc->config.allow_0_dtb_clk)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

244

dcn42_smu_set_dtbclk(clk_mgr, false);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

256

dcn42_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

266

dcn42_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

267

dcn42_smu_set_dtbclk(clk_mgr, true);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

280

dcn42_smu_set_display_idle_optimization(clk_mgr, idle_info.data);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

296

dcn42_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

308

dcn42_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

315

if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

316

if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

332

dcn42_smu_set_dispclk(clk_mgr, requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

343

dcn42_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

349

dcn42_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

350

dcn42_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

354

dcn42_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

355

dcn42_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

371

void dcn42_enable_pme_wa(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

373

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

375

dcn42_smu_enable_pme_wa(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

398

static void dcn42_dump_clk_registers_internal(struct dcn42_clk_internal *internal, struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

400

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

425

struct clk_mgr_dcn42 *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

430

DC_LOGGER_INIT(clk_mgr->base.base.ctx->logger);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

433

dcn42_dump_clk_registers_internal(&internal, &clk_mgr->base.base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

448

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

48

clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

505

bool dcn42_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

507

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

508

struct dc_context *ctx = clk_mgr->base.ctx;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

51

(clk_mgr->regs->reg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

513

return (clk_mgr->dprefclk_ss_percentage == 0);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

519

static void init_clk_states(struct clk_mgr *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

521

uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

523

memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

525

clk_mgr->clks.dtbclk_en = true; // request DTBCLK disable on first commit

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

526

clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

527

clk_mgr->clks.p_state_change_support = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

528

clk_mgr->clks.prev_p_state_change_support = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

529

clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

530

clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

533

void dcn42_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

538

if (!clk_mgr->smu_ver)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

546

dcn42_smu_set_dram_addr_high(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

548

dcn42_smu_set_dram_addr_low(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

550

dcn42_smu_transfer_dpm_table_smu_2_dram(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

587

void dcn42_init_clocks(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

590

struct clk_mgr_dcn42 *clk_mgr = TO_CLK_MGR_DCN42(clk_mgr_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

605

dcn42_dump_clk_registers(&clk_mgr_base->boot_snapshot, clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

625

static void dcn42_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

631

if (dcn42_is_spll_ssc_enabled(&clk_mgr->base) && (clock_source < ARRAY_SIZE(dcn42_ss_info_table.ss_percentage))) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

632

clk_mgr->dprefclk_ss_percentage = dcn42_ss_info_table.ss_percentage[clock_source];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

634

if (clk_mgr->dprefclk_ss_percentage != 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

635

clk_mgr->ss_on_dprefclk = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

636

clk_mgr->dprefclk_ss_divider = dcn42_ss_info_table.ss_divider;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

699

void dcn42_notify_wm_ranges(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

703

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

704

struct clk_mgr_dcn42 *clk_mgr_dcn42 = TO_CLK_MGR_DCN42(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

706

if (!clk_mgr->smu_ver)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

712

clk_mgr->base.ctx,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

739

dcn42_smu_set_dram_addr_high(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

741

dcn42_smu_set_dram_addr_low(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

743

dcn42_smu_transfer_wm_table_dram_2_smu(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

746

dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

754

void dcn42_set_low_power_state(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

767

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

772

dcn42_smu_set_display_idle_optimization(clk_mgr, idle_info.data);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

776

void dcn42_exit_low_power_state(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

782

static void dcn42_init_clocks_fpga(struct clk_mgr *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

784

init_clk_states(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

788

void dcn42_update_clocks_fpga(struct clk_mgr *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

792

struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

804

if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

805

clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

807

if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

808

clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

811

new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

812

clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

814

if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

815

clk_mgr->clks.socclk_khz = new_clocks->socclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

817

if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

818

clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

820

if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

821

clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

823

if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

824

clk_mgr->clks.fclk_khz = fclk_adj;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

826

if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

827

clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

833

if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

834

clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

835

if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

836

clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

839

clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

841

dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

842

if (clk_mgr->clks.dtbclk_en) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

843

dcn42_update_clocks_update_dtb_dto(clk_mgr_int, context, clk_mgr->clks.ref_dtbclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

845

clk_mgr->clks.ref_dtbclk_khz = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

850

unsigned int dcn42_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

852

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

858

num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

860

clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 :

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

861

clk_mgr->base.boot_snapshot.dispclk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

863

num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

865

clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dppclk_mhz * 1000 :

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

866

clk_mgr->base.boot_snapshot.dppclk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

868

num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

870

clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 / 3 :

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

871

clk_mgr->base.boot_snapshot.dispclk / 3;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

879

int dcn42_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

882

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

891

return (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

895

bool dcn42_is_smu_present(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

897

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

898

return clk_mgr->smu_present;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

903

struct clk_mgr *clk_mgr_base = &clk_mgr_int->base;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

51

void dcn42_init_clocks(struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

52

void dcn42_update_clocks(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

57

struct clk_mgr_dcn42 *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

69

void dcn42_enable_pme_wa(struct clk_mgr *clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

70

void dcn42_notify_wm_ranges(struct clk_mgr *clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

71

void dcn42_set_low_power_state(struct clk_mgr *clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

72

void dcn42_exit_low_power_state(struct clk_mgr *clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

73

unsigned int dcn42_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

74

bool dcn42_is_smu_present(struct clk_mgr *clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

78

void dcn42_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, bool safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

79

void dcn42_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, int ref_dtbclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

80

bool dcn42_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

82

void dcn42_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, struct dcn42_smu_dpm_clks *smu_dpm_clks);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

84

void dcn42_update_clocks_fpga(struct clk_mgr *clk_mgr, struct dc_state *context, bool safe_to_lower);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

85

int dcn42_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

105

static uint32_t dcn42_smu_wait_for_response(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

120

if (clk_mgr->base.ctx->dc->debug.disable_timeout)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

127

static int dcn42_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

133

result = dcn42_smu_wait_for_response(clk_mgr, 10, 2000000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

151

result = dcn42_smu_wait_for_response(clk_mgr, 10, 2000000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

164

result = dcn42_smu_wait_for_response(clk_mgr, 10, 2000000);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

172

int dcn42_smu_get_pmfw_version(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

175

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

181

int dcn42_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

185

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

190

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

200

int dcn42_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

204

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

208

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

218

int dcn42_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

222

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

226

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

236

int dcn42_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

240

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

244

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

254

void dcn42_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

256

if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

259

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

263

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

269

void dcn42_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

273

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

282

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

288

void dcn42_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

290

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

294

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

300

void dcn42_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

302

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

305

dcn42_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

309

void dcn42_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

311

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

314

dcn42_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

318

void dcn42_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

320

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

323

dcn42_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

327

void dcn42_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

329

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

332

dcn42_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

336

void dcn42_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

340

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

384

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

390

int dcn42_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

394

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

397

dprefclk = dcn42_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

405

int dcn42_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

409

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

412

dtbclk = dcn42_smu_send_msg_with_param(clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

420

void dcn42_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

422

if (!clk_mgr->smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

426

clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

170

int dcn42_smu_get_pmfw_version(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

171

int dcn42_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

172

int dcn42_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

173

int dcn42_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

174

int dcn42_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

175

void dcn42_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

176

void dcn42_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

177

void dcn42_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

178

void dcn42_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

179

void dcn42_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

180

void dcn42_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

181

void dcn42_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

183

void dcn42_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

184

void dcn42_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

185

void dcn42_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

187

int dcn42_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h

188

int dcn42_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

100

static void dcn42b_dump_clk_registers_internal(struct dcn42b_clk_internal *internal, struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

102

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

128

struct clk_mgr_dcn42 *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

133

DC_LOGGER_INIT(clk_mgr->base.base.ctx->logger);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

136

dcn42b_dump_clk_registers_internal(&internal, &clk_mgr->base.base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

151

if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

206

static void init_clk_states(struct clk_mgr *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

213

memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

214

clk_mgr->clks.dtbclk_en = false; /* DTBCLK tied off in DCN42B */

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

217

clk_mgr->clks.ref_dtbclk_khz = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

218

clk_mgr->clks.p_state_change_support = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

219

clk_mgr->clks.prev_p_state_change_support = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

220

clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

221

clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

228

void dcn42b_init_clocks(struct clk_mgr *clk_mgr_base)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

231

struct clk_mgr_dcn42 *clk_mgr = TO_CLK_MGR_DCN42B(clk_mgr_int);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

246

dcn42b_dump_clk_registers(&clk_mgr_base->boot_snapshot, clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

333

static void dcn42b_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

339

if (dcn42_is_spll_ssc_enabled(&clk_mgr->base) && (clock_source < ARRAY_SIZE(dcn42_ss_info_table.ss_percentage))) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

340

clk_mgr->dprefclk_ss_percentage = dcn42_ss_info_table.ss_percentage[clock_source];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

342

if (clk_mgr->dprefclk_ss_percentage != 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

343

clk_mgr->ss_on_dprefclk = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

344

clk_mgr->dprefclk_ss_divider = dcn42_ss_info_table.ss_divider;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

349

uint32_t dcn42b_get_clock_freq_from_clkip(struct clk_mgr *clk_mgr_base, enum clock_type clock)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

351

struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

417

struct clk_mgr_dcn42 *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

421

clk_mgr->base.base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

422

clk_mgr->base.base.funcs = &dcn42b_funcs;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

423

clk_mgr->base.regs = &clk_mgr_regs_dcn42b;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

424

clk_mgr->base.clk_mgr_shift = &clk_mgr_shift_dcn42b;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

425

clk_mgr->base.clk_mgr_mask = &clk_mgr_mask_dcn42b;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

427

clk_mgr->base.pp_smu = pp_smu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

429

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

430

clk_mgr->base.dfs_bypass_disp_clk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

432

clk_mgr->base.dprefclk_ss_percentage = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

433

clk_mgr->base.dprefclk_ss_divider = 1000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

434

clk_mgr->base.ss_on_dprefclk = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

435

clk_mgr->base.dfs_ref_freq_khz = 48000; /*sync with pmfw*/

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

436

clk_mgr->base.base.clks.ref_dtbclk_khz = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

442

clk_mgr->base.base.dprefclk_khz = 600000;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

444

clk_mgr->base.smu_present = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

445

clk_mgr->base.smu_ver = dcn42_smu_get_pmfw_version(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

446

if (clk_mgr->base.smu_ver && clk_mgr->base.smu_ver != -1)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

447

clk_mgr->base.smu_present = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

450

clk_mgr->base.base.dentist_vco_freq_khz = ctx->dc_bios->integrated_info->dentist_vco_freq;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

459

if (clk_mgr->base.smu_present)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

460

clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

464

if (clk_mgr->base.base.dentist_vco_freq_khz == 0)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

465

clk_mgr->base.base.dentist_vco_freq_khz = 3000000; /* 3000MHz */

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

468

dcn42b_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

470

dce_clock_read_ss_info(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

473

dcn42b_read_ss_info_from_lut(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

475

clk_mgr->base.base.bw_params = &dcn42b_bw_params;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

476

if (clk_mgr->base.smu_present) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

477

dcn42_get_smu_clocks(&clk_mgr->base);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

479

clk_mgr->base.base.bw_params->clk_table.entries[0].dtbclk_mhz = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

480

clk_mgr->base.base.bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

481

clk_mgr->base.base.clks.ref_dtbclk_khz = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

67

clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

70

(clk_mgr->regs->reg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.h

39

void dcn42b_init_clocks(struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.h

42

struct clk_mgr_dcn42 *clk_mgr,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.h

45

uint32_t dcn42b_get_clock_freq_from_clkip(struct clk_mgr *clk_mgr_base,

drivers/gpu/drm/amd/display/dc/core/dc.c

1095

dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);

drivers/gpu/drm/amd/display/dc/core/dc.c

1096

if (!dc->clk_mgr)

drivers/gpu/drm/amd/display/dc/core/dc.c

1099

dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;

drivers/gpu/drm/amd/display/dc/core/dc.c

1102

dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);

drivers/gpu/drm/amd/display/dc/core/dc.c

6253

if (dc->clk_mgr->funcs->set_low_power_state)

drivers/gpu/drm/amd/display/dc/core/dc.c

6254

dc->clk_mgr->funcs->set_low_power_state(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/core/dc.c

6388

if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present)

drivers/gpu/drm/amd/display/dc/core/dc.c

6389

if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr))

drivers/gpu/drm/amd/display/dc/core/dc.c

6395

if (dc->hwss.apply_idle_power_optimizations && dc->clk_mgr != NULL &&

drivers/gpu/drm/amd/display/dc/core/dc.c

6402

if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->get_hard_min_fclk)

drivers/gpu/drm/amd/display/dc/core/dc.c

6403

idle_fclk_khz = dc->clk_mgr->funcs->get_hard_min_fclk(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/core/dc.c

6405

if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->get_hard_min_memclk)

drivers/gpu/drm/amd/display/dc/core/dc.c

6406

idle_dramclk_khz = dc->clk_mgr->funcs->get_hard_min_memclk(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/core/dc.c

6444

if (dc->clk_mgr->funcs->set_hard_min_memclk)

drivers/gpu/drm/amd/display/dc/core/dc.c

6445

dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);

drivers/gpu/drm/amd/display/dc/core/dc.c

6447

if (dc->clk_mgr->funcs->set_hard_max_memclk)

drivers/gpu/drm/amd/display/dc/core/dc.c

6448

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/core/dc.c

6454

if (dc->clk_mgr->funcs->get_memclk_states_from_smu)

drivers/gpu/drm/amd/display/dc/core/dc.c

6455

dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/core/dc.c

6457

if (dc->clk_mgr->funcs->set_hard_min_memclk)

drivers/gpu/drm/amd/display/dc/core/dc.c

6458

dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);

drivers/gpu/drm/amd/display/dc/core/dc.c

6460

if (dc->clk_mgr->funcs->set_hard_max_memclk)

drivers/gpu/drm/amd/display/dc/core/dc.c

6461

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/core/dc.c

6487

if (dc->clk_mgr->funcs->set_max_memclk)

drivers/gpu/drm/amd/display/dc/core/dc.c

6488

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, memclk_mhz);

drivers/gpu/drm/amd/display/dc/core/dc.c

6489

if (dc->clk_mgr->funcs->set_min_memclk)

drivers/gpu/drm/amd/display/dc/core/dc.c

6490

dc->clk_mgr->funcs->set_min_memclk(dc->clk_mgr, memclk_mhz);

drivers/gpu/drm/amd/display/dc/core/dc.c

6529

softMax = dc->clk_mgr->bw_params->dc_mode_softmax_memclk;

drivers/gpu/drm/amd/display/dc/core/dc.c

6530

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries; i++) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6531

if (dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz > maxDPM)

drivers/gpu/drm/amd/display/dc/core/dc.c

6532

maxDPM = dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz;

drivers/gpu/drm/amd/display/dc/core/dc.c

6534

funcMin = (dc->clk_mgr->clks.dramclk_khz + 999) / 1000;

drivers/gpu/drm/amd/display/dc/core/dc.c

6535

p_state_change_support = dc->clk_mgr->clks.p_state_change_support;

drivers/gpu/drm/amd/display/dc/core/dc.c

6537

if (enable && !dc->clk_mgr->dc_mode_softmax_enabled) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6539

if (funcMin <= softMax && dc->clk_mgr->funcs->set_max_memclk)

drivers/gpu/drm/amd/display/dc/core/dc.c

6540

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, softMax);

drivers/gpu/drm/amd/display/dc/core/dc.c

6547

} else if (!enable && dc->clk_mgr->dc_mode_softmax_enabled) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6549

if (funcMin <= softMax && dc->clk_mgr->funcs->set_max_memclk)

drivers/gpu/drm/amd/display/dc/core/dc.c

6550

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, maxDPM);

drivers/gpu/drm/amd/display/dc/core/dc.c

6558

dc->clk_mgr->dc_mode_softmax_enabled = enable;

drivers/gpu/drm/amd/display/dc/core/dc.c

7173

if (!context->clk_mgr || !context->clk_mgr->ctx || !context->clk_mgr->ctx->dc)

drivers/gpu/drm/amd/display/dc/core/dc.c

7175

struct dc *dc = context->clk_mgr->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

7193

struct dc *dc = context->clk_mgr->ctx->dc;

drivers/gpu/drm/amd/display/dc/core/dc.c

7277

out_data->uclk_p_state = dc->current_state->clk_mgr->clks.p_state_change_support;

drivers/gpu/drm/amd/display/dc/core/dc.c

7492

if (dc->clk_mgr && dc->clk_mgr->clks.dispclk_khz > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7494

state->dccg.dispclk_khz = dc->clk_mgr->clks.dispclk_khz;

drivers/gpu/drm/amd/display/dc/core/dc.c

7501

state->dccg.dppclk_khz[i] = dc->clk_mgr->clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/core/dc.c

7884

if (dc->clk_mgr && dc->clk_mgr->funcs->get_requested_memory_qos) {

drivers/gpu/drm/amd/display/dc/core/dc.c

7885

dc->clk_mgr->funcs->get_requested_memory_qos(dc->clk_mgr, &requested);

drivers/gpu/drm/amd/display/dc/core/dc.c

7900

if (!dc->clk_mgr || !dc->clk_mgr->funcs)

drivers/gpu/drm/amd/display/dc/core/dc.c

7903

return dc->clk_mgr->funcs->override_memory_bandwidth_request(

drivers/gpu/drm/amd/display/dc/core/dc.c

7904

dc->clk_mgr, bw_mbps * 1000) / 1000;

drivers/gpu/drm/amd/display/dc/core/dc.c

894

if (dc->clk_mgr) {

drivers/gpu/drm/amd/display/dc/core/dc.c

895

dc_destroy_clk_mgr(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/core/dc.c

896

dc->clk_mgr = NULL;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5943

if (context->clk_mgr->ctx->dc->res_pool->funcs->program_mcache_pipe_config)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5944

context->clk_mgr->ctx->dc->res_pool->funcs->program_mcache_pipe_config(context, mcache_params);

drivers/gpu/drm/amd/display/dc/core/dc_state.c

327

state->clk_mgr = dc->clk_mgr;

drivers/gpu/drm/amd/display/dc/core/dc_state.c

366

state->clk_mgr = NULL;

drivers/gpu/drm/amd/display/dc/dc.h

1872

struct clk_mgr *clk_mgr;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1477

if (dc->clk_mgr->funcs->exit_low_power_state) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1527

dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1544

dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1095

dtbclk_p_src_clk_khz = clock_source->ctx->dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(clock_source->ctx->dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1098

dtbclk_p_src_clk_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1219

unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1371

clock_source->ctx->dc->clk_mgr->dprefclk_khz*1000);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1407

unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

971

unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

978

if (clock_source->ctx->dc->clk_mgr->dp_dto_source_clock_in_khz != 0 &&

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

981

dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dp_dto_source_clock_in_khz;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2192

dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2199

dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2210

dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2257

struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

298

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

301

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

302

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

303

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

346

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

366

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

371

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

372

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

373

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

413

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

418

dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

422

int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

425

dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

434

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts)

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

439

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

441

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

442

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

521

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

584

dcn3_0_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

585

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

639

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

664

void dcn3_fpu_build_wm_range_table(struct clk_mgr *base)

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h

69

void dcn3_fpu_build_wm_range_table(struct clk_mgr *base);

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

392

dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

393

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

436

struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

218

dcn3_02_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

219

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

214

dcn3_03_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

215

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

458

if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

459

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

460

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

461

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

469

if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

474

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

476

dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

478

dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

659

dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

660

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

186

void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

189

double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

190

double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

191

double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

192

double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

194

uint16_t min_uclk_mhz = (uint16_t)clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

195

uint16_t min_dcfclk_mhz = (uint16_t)clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

198

(uint16_t)clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

204

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

207

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk =

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

208

(uint16_t)clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

210

if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

211

setb_min_uclk_mhz = (uint16_t)clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

214

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

215

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

216

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

217

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

218

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

219

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

220

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

221

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

222

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

223

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

226

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

227

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

228

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us = fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

229

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

230

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

231

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2314

if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2317

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

232

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2320

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

233

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = setb_min_uclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

234

clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2358

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2362

if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2365

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

238

if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2388

context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

239

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

240

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 50;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

241

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2412

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2413

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2414

context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2415

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2416

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

242

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

243

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

244

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

245

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

246

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

247

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

248

clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2481

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2486

dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

249

clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2490

int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2493

dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

250

clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 50;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2502

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2507

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2509

context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

251

clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2510

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2511

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

252

clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2529

if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

253

clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

254

clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2549

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

255

clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2550

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2551

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

256

clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2592

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2599

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

260

clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2604

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

261

clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

262

clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us = fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

263

clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2; // TBD

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

264

clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us / 2; // TBD

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

265

clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

266

clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

267

clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

268

clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

269

clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

295

dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3120

dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3121

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3122

dc->dml2_options.bbox_overrides.disp_pll_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3125

dc->dml2_options.bbox_overrides.dprefclk_mhz = dc->clk_mgr->dprefclk_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3292

if (dc->clk_mgr->bw_params->clk_table.num_entries > 1) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3295

dc->dml2_options.bbox_overrides.clks_table.num_states = dc->clk_mgr->bw_params->clk_table.num_entries;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3298

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3301

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3304

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3307

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3310

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3313

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3316

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dppclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3318

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3319

if (dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3321

dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3324

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3325

if (dc->clk_mgr->bw_params->clk_table.entries[i].fclk_mhz)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3327

dc->clk_mgr->bw_params->clk_table.entries[i].fclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3330

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3331

if (dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3333

dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3336

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3337

if (dc->clk_mgr->bw_params->clk_table.entries[i].socclk_mhz)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3339

dc->clk_mgr->bw_params->clk_table.entries[i].socclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3342

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3343

if (dc->clk_mgr->bw_params->clk_table.entries[i].dtbclk_mhz)

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3345

dc->clk_mgr->bw_params->clk_table.entries[i].dtbclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3348

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3349

if (dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3351

dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3353

dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3584

int num_mclk_levels = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3586

if (context->bw_ctx.dml.vba.DRAMSpeed <= dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 16 &&

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

3588

context->bw_ctx.dml.vba.DRAMSpeed = dc->clk_mgr->bw_params->clk_table.entries[1].memclk_mhz * 16;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

32

void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

704

dcn3_21_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

705

dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

706

dc->dml2_options.bbox_overrides.disp_pll_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

709

dc->dml2_options.bbox_overrides.dprefclk_mhz = dc->clk_mgr->dprefclk_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

867

if (dc->clk_mgr->bw_params->clk_table.num_entries > 1) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

870

dc->dml2_options.bbox_overrides.clks_table.num_states = dc->clk_mgr->bw_params->clk_table.num_entries;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

873

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

876

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

879

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

882

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

885

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

888

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

891

dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dppclk_levels;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

894

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

895

if (dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz)

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

897

dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

900

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

901

if (dc->clk_mgr->bw_params->clk_table.entries[i].fclk_mhz)

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

903

dc->clk_mgr->bw_params->clk_table.entries[i].fclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

906

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

907

if (dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

909

dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

912

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

913

if (dc->clk_mgr->bw_params->clk_table.entries[i].socclk_mhz)

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

915

dc->clk_mgr->bw_params->clk_table.entries[i].socclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

918

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

919

if (dc->clk_mgr->bw_params->clk_table.entries[i].dtbclk_mhz)

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

921

dc->clk_mgr->bw_params->clk_table.entries[i].dtbclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

924

for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

925

if (dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz) {

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

927

dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

929

dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

203

void dcn35_build_wm_range_table_fpu(struct clk_mgr *clk_mgr)

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

205

(void)clk_mgr;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h

32

void dcn35_build_wm_range_table_fpu(struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

436

copy_dummy_pstate_table(s->dummy_pstate_table, in_dc->clk_mgr->bw_params->dummy_pstate_table, 4);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1069

if (!dc->clk_mgr || !dc->clk_mgr->funcs->get_max_clock_khz || !dc->res_pool || dc->debug.disable_dsc)

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1073

max_dscclk_khz = dc->clk_mgr->funcs->get_max_clock_khz(dc->clk_mgr, CLK_TYPE_DSCCLK);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1113

if (dsc->ctx->dc->clk_mgr &&

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1114

dsc->ctx->dc->clk_mgr->funcs->get_max_clock_khz) {

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1116

max_dispclk_khz = dsc->ctx->dc->clk_mgr->funcs->get_max_clock_khz(dsc->ctx->dc->clk_mgr, CLK_TYPE_DISPCLK);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

615

if (hubbub1->base.ctx->dc->clk_mgr->clks.prev_p_state_change_support == true &&

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

616

hubbub1->base.ctx->dc->clk_mgr->clks.p_state_change_support == false)

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

114

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

115

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

126

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c

127

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1128

struct clk_mgr *clk_mgr;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1139

clk_mgr = dc->clk_mgr;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1151

if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1153

clk_mgr->funcs->enable_pme_wa(clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1168

struct clk_mgr *clk_mgr;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1178

clk_mgr = dc->clk_mgr;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1189

if (clk_mgr->funcs->enable_pme_wa)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1191

clk_mgr->funcs->enable_pme_wa(clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1547

if (state->clk_mgr &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1552

state->clk_mgr->funcs->get_dp_ref_clk_frequency(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1553

state->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2139

clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2159

clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2539

dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2593

dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3080

struct clk_mgr *dccg = dc->clk_mgr;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3094

struct clk_mgr *dccg = dc->clk_mgr;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3533

if (dc->clk_mgr->funcs->notify_link_rate_change)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3534

dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1817

if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1818

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1821

if (dc->clk_mgr && dc->clk_mgr->clks.dispclk_khz != 0 && dc->clk_mgr->clks.dppclk_khz != 0) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1822

dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz = dc->clk_mgr->clks.dispclk_khz;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1823

dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz = dc->clk_mgr->clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1941

if (dc->clk_mgr && dc->clk_mgr->funcs->notify_wm_ranges)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1942

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1988

if (dc->clk_mgr->funcs->set_low_power_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1989

dc->clk_mgr->funcs->set_low_power_state(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2442

dc->res_pool->dp_clock_source->ctx->dc->clk_mgr->dprefclk_khz*10;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3072

dc->clk_mgr->clks.dispclk_khz)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3077

dc->clk_mgr->clks.dispclk_khz / 2;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3090

dc->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3091

dc->clk_mgr->clks.dispclk_khz / 2 :

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3092

dc->clk_mgr->clks.dispclk_khz;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3398

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3399

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3436

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3437

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4122

if (!dc->clk_mgr || !dc->clk_mgr->funcs->get_clock)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4125

dc->clk_mgr->funcs->get_clock(dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4145

if (dc->clk_mgr->funcs->update_clocks)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4146

dc->clk_mgr->funcs->update_clocks(dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4158

if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4159

dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2382

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2383

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2447

if (dc->clk_mgr->dc_mode_softmax_enabled) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2448

int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2450

if (dc->clk_mgr->clks.dramclk_khz > softmax_memclk_khz &&

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2452

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2463

dc->clk_mgr->clks.fw_based_mclk_switching = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2465

dc->clk_mgr->clks.fw_based_mclk_switching = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2468

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2469

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3062

dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3156

if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3157

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

895

dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

237

if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

238

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

101

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

102

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

111

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

112

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1219

if ((!dc->clk_mgr->clks.p_state_change_support || subvp_in_use ||

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1242

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !dc->clk_mgr->clks.fw_based_mclk_switching) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1247

if (dc->clk_mgr->dc_mode_softmax_enabled) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1248

int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1250

if (dc->clk_mgr->clks.dramclk_khz <= softmax_memclk_khz &&

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1252

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1257

if (!dc->clk_mgr->clks.fw_based_mclk_switching)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

655

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

656

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

816

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

817

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

820

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->set_hard_max_memclk &&

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

821

!dc->clk_mgr->dc_mode_softmax_enabled)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

822

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

123

if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

124

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

261

if (dc->clk_mgr && dc->clk_mgr->funcs->notify_wm_ranges)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

262

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

264

if (dc->clk_mgr && dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

265

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1016

dc->clk_mgr && dc->clk_mgr->bw_params) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1018

dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1822

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1827

if (dc->clk_mgr->dc_mode_softmax_enabled) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1828

int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1830

if (dc->clk_mgr->clks.dramclk_khz <= softmax_memclk_khz &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1832

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1840

if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

761

if (!dc->clk_mgr || !dc->clk_mgr->bw_params || !dc->clk_mgr->funcs)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

765

clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

766

clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

767

clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

768

clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

769

clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

774

clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

775

} else if (dc->clk_mgr->funcs->get_dispclk_from_dentist) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

781

clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

784

if (dc->clk_mgr->funcs->update_clocks)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

785

dc->clk_mgr->funcs->update_clocks(dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

801

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

802

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

980

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

981

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

983

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->set_hard_max_memclk &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

984

!dc->clk_mgr->dc_mode_softmax_enabled)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

985

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

154

if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

155

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1566

if (pix_clk_mhz > dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

297

if (dc->clk_mgr && dc->clk_mgr->funcs->notify_wm_ranges)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

298

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

300

if (dc->clk_mgr && dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

301

dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

575

if (dc->clk_mgr->funcs->set_low_power_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

576

dc->clk_mgr->funcs->set_low_power_state(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

578

if (dc->clk_mgr->clks.pwr_state == DCN_PWR_STATE_LOW_POWER)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1458

if (dc->clk_mgr->dc_mode_softmax_enabled) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1459

int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1461

if (dc->clk_mgr->clks.dramclk_khz <= softmax_memclk_khz &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1463

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1467

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1468

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1530

if (dc->clk_mgr->dc_mode_softmax_enabled) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1531

int softmax_memclk_khz = dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1533

if (dc->clk_mgr->clks.dramclk_khz > softmax_memclk_khz &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1535

dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

154

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1542

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1543

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

155

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

158

dc->caps.dcmode_power_limits_present = dc->clk_mgr->funcs->is_dc_mode_present &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

159

dc->clk_mgr->funcs->is_dc_mode_present(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1876

if ((!dc->clk_mgr->clks.p_state_change_support ||

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1883

dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, dc->current_state, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1887

dc->clk_mgr->clks.p_state_change_support = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1888

dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, dc->current_state, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

373

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

374

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

400

dc->clk_mgr && dc->clk_mgr->bw_params) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

403

dc->clk_mgr->bw_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

64

clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

65

clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

66

clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

67

clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

69

clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

76

if (dc->clk_mgr->funcs->get_dispclk_from_dentist) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

77

clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

79

clocks->dispclk_khz = dc->clk_mgr->boot_snapshot.dispclk * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

82

clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

86

dc->clk_mgr->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

87

dc->clk_mgr,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1566

if (dc->clk_mgr->funcs->set_low_power_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1567

dc->clk_mgr->funcs->set_low_power_state(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

254

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

255

dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

265

dc->clk_mgr && dc->clk_mgr->bw_params &&

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

268

dc->clk_mgr->bw_params->num_channels,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

286

dc->clk_mgr && dc->clk_mgr->bw_params) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

288

dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

74

if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

75

dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

78

dc->caps.dcmode_power_limits_present = dc->clk_mgr->funcs->is_dc_mode_present &&

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

79

dc->clk_mgr->funcs->is_dc_mode_present(dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

665

struct clk_mgr *clk_mgr;

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

329

void (*update_clocks)(struct clk_mgr *clk_mgr,

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

333

int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

334

int (*get_dtb_ref_clk_frequency)(struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

336

void (*set_low_power_state)(struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

337

void (*exit_low_power_state)(struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

338

bool (*is_ips_supported)(struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

340

void (*init_clocks)(struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

343

struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

345

void (*enable_pme_wa) (struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

346

void (*get_clock)(struct clk_mgr *clk_mgr,

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

353

void (*notify_wm_ranges)(struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

356

void (*notify_link_rate_change)(struct clk_mgr *clk_mgr, struct dc_link *link);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

362

void (*set_hard_min_memclk)(struct clk_mgr *clk_mgr, bool current_mode);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

364

int (*get_hard_min_memclk)(struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

365

int (*get_hard_min_fclk)(struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

368

void (*set_hard_max_memclk)(struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

371

void (*set_max_memclk)(struct clk_mgr *clk_mgr, unsigned int memclk_mhz);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

372

void (*set_min_memclk)(struct clk_mgr *clk_mgr, unsigned int memclk_mhz);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

375

void (*get_memclk_states_from_smu)(struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

378

bool (*is_smu_present)(struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

380

int (*get_dispclk_from_dentist)(struct clk_mgr *clk_mgr_base);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

382

bool (*is_dc_mode_present)(struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

384

uint32_t (*set_smartmux_switch)(struct clk_mgr *clk_mgr, uint32_t pins_to_set);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

386

unsigned int (*get_max_clock_khz)(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

397

struct clk_mgr *clk_mgr,

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

406

struct clk_mgr *clk_mgr,

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

428

struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

430

void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

432

void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

434

void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

440

struct clk_mgr base;

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

527

int (*set_dispclk)(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

528

int (*set_dprefclk)(struct clk_mgr_internal *clk_mgr);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

70

#define TO_CLK_MGR_INTERNAL(clk_mgr)\

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

71

container_of(clk_mgr, struct clk_mgr_internal, base)

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

74

clk_mgr->base.ctx

drivers/gpu/drm/amd/display/dc/link/link_detection.c

831

clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/link/link_detection.c

836

clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1996

core_dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(core_dc->clk_mgr),

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2094

if (state->clk_mgr && !apply_seamless_boot_optimization)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2095

state->clk_mgr->funcs->update_clocks(state->clk_mgr,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c

87

if (dc->clk_mgr->funcs->notify_link_rate_change)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c

88

dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

875

const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1912

if ((unsigned int)pixel_clk_params->requested_pix_clk_100hz > (unsigned int)(4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1914

} else if ((unsigned int)pixel_clk_params->requested_pix_clk_100hz > (unsigned int)(2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1916

} else if ((unsigned int)pixel_clk_params->requested_pix_clk_100hz > (unsigned int)(stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1929

for (unsigned int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1930

if (context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz == 0 ||

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1931

uclk_mhz < context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1933

if (uclk_mhz > context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1706

if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1708

} else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1710

} else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1671

if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1673

} else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1675

} else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

214

soc_bb->dprefclk_mhz = dc->clk_mgr->dprefclk_khz / 1000;

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

215

soc_bb->dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

218

if (dc->clk_mgr->funcs->is_smu_present &&

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

219

dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr)) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c

221

dc->clk_mgr->bw_params,

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

153

soc_bb->dprefclk_mhz = dc->clk_mgr->dprefclk_khz / 1000;

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

154

soc_bb->dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

157

if (dc->clk_mgr->funcs->is_smu_present &&

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

158

dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr)) {

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

160

dc->clk_mgr->bw_params);

drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c

163

if (dc->clk_mgr->bw_params->vram_type == Ddr5MemType) {