clrsetbits_be32
clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset);
clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r);
clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,
clrsetbits_be32(&gpt->regs->mode, clear, set);
clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000);
clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550);
clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0);
clrsetbits_be32(im + MPC83XX_SICRL_OFFS, MPC837X_SICRL_USBB_MASK,
clrsetbits_be32(im + MPC83XX_SICRH_OFFS, MPC837X_SICRH_SPI_MASK,
clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
clrsetbits_be32(immap + MPC83XX_SICRH_OFFS,
clrsetbits_be32(immap + MPC83XX_SICRL_OFFS,
clrsetbits_be32(immap + MPC83XX_SICRH_OFFS,
clrsetbits_be32(immap + MPC83XX_SICRL_OFFS,
clrsetbits_be32(immap + MPC83XX_SICRH_OFFS,
clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, MPC837X_SCCR_USB_DRCM_11,
clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC837X_SICRL_USB_MASK,
clrsetbits_be32(&guts->pmuxcr, PMUXCR_ELBCDIU_MASK,
clrsetbits_be32(&lbc->lbcr, LBCR_BMT, LBCR_BMTPS);
clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift);
clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift);
clrsetbits_be32(&fec->fecp->fec_mii_speed, 0x7E, fec->mii_speed);
clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
clrsetbits_be32(&guts->pmuxcr, CCSR_GUTS_PMUXCR_SSI_DMA_TDM_MASK,
clrsetbits_be32(&guts->dmuxcr, 3 << shift, device << shift);
clrsetbits_be32(&guts->pmuxcr, CCSR_GUTS_PMUXCR_UART0_I2C1_MASK,
clrsetbits_be32(&guts->pmuxcr, CCSR_GUTS_PMUXCR_UART0_I2C1_MASK,
clrsetbits_be32(&guts->pmuxcr, CCSR_GUTS_PMUXCR_SSI_DMA_TDM_MASK,
clrsetbits_be32(&guts->dmuxcr, 3 << shift, device << shift);