arch/powerpc/include/asm/mpc52xx.h

277

extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv);

arch/powerpc/platforms/52xx/mpc52xx_common.c

172

int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv)

arch/powerpc/platforms/52xx/mpc52xx_common.c

183

mclken_div = 0x8000 | (clkdiv & 0x1FF);

drivers/bluetooth/btnxpuart.c

309

struct uart_reg clkdiv;

drivers/bluetooth/btnxpuart.c

821

uart_config.clkdiv.address = __cpu_to_le32(clkdivaddr);

drivers/bluetooth/btnxpuart.c

823

uart_config.clkdiv.value = __cpu_to_le32(0x01000000);

drivers/bluetooth/btnxpuart.c

825

uart_config.clkdiv.value = __cpu_to_le32(0x00c00000);

drivers/clk/qcom/clk-spmi-pmic-div.c

100

spin_unlock_irqrestore(&clkdiv->lock, flags);

drivers/clk/qcom/clk-spmi-pmic-div.c

107

struct clkdiv *clkdiv = to_clkdiv(hw);

drivers/clk/qcom/clk-spmi-pmic-div.c

110

spin_lock_irqsave(&clkdiv->lock, flags);

drivers/clk/qcom/clk-spmi-pmic-div.c

111

spmi_pmic_clkdiv_set_enable_state(clkdiv, false);

drivers/clk/qcom/clk-spmi-pmic-div.c

112

spin_unlock_irqrestore(&clkdiv->lock, flags);

drivers/clk/qcom/clk-spmi-pmic-div.c

132

struct clkdiv *clkdiv = to_clkdiv(hw);

drivers/clk/qcom/clk-spmi-pmic-div.c

135

regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor);

drivers/clk/qcom/clk-spmi-pmic-div.c

144

struct clkdiv *clkdiv = to_clkdiv(hw);

drivers/clk/qcom/clk-spmi-pmic-div.c

149

guard(spinlock_irqsave)(&clkdiv->lock);

drivers/clk/qcom/clk-spmi-pmic-div.c

151

enabled = is_spmi_pmic_clkdiv_enabled(clkdiv);

drivers/clk/qcom/clk-spmi-pmic-div.c

153

ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, false);

drivers/clk/qcom/clk-spmi-pmic-div.c

158

ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1,

drivers/clk/qcom/clk-spmi-pmic-div.c

164

ret = __spmi_pmic_clkdiv_set_enable_state(clkdiv, true,

drivers/clk/qcom/clk-spmi-pmic-div.c

179

struct clkdiv clks[] __counted_by(nclks);

drivers/clk/qcom/clk-spmi-pmic-div.c

201

struct clkdiv *clkdiv;

drivers/clk/qcom/clk-spmi-pmic-div.c

253

for (i = 0, clkdiv = cc->clks; i < nclks; i++) {

drivers/clk/qcom/clk-spmi-pmic-div.c

256

spin_lock_init(&clkdiv[i].lock);

drivers/clk/qcom/clk-spmi-pmic-div.c

257

clkdiv[i].base = start + i * 0x100;

drivers/clk/qcom/clk-spmi-pmic-div.c

258

clkdiv[i].regmap = regmap;

drivers/clk/qcom/clk-spmi-pmic-div.c

259

clkdiv[i].cxo_period_ns = NSEC_PER_SEC / cxo_hz;

drivers/clk/qcom/clk-spmi-pmic-div.c

260

clkdiv[i].hw.init = &init;

drivers/clk/qcom/clk-spmi-pmic-div.c

262

ret = devm_clk_hw_register(dev, &clkdiv[i].hw);

drivers/clk/qcom/clk-spmi-pmic-div.c

34

static inline struct clkdiv *to_clkdiv(struct clk_hw *hw)

drivers/clk/qcom/clk-spmi-pmic-div.c

36

return container_of(hw, struct clkdiv, hw);

drivers/clk/qcom/clk-spmi-pmic-div.c

52

static bool is_spmi_pmic_clkdiv_enabled(struct clkdiv *clkdiv)

drivers/clk/qcom/clk-spmi-pmic-div.c

56

regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val);

drivers/clk/qcom/clk-spmi-pmic-div.c

62

__spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable,

drivers/clk/qcom/clk-spmi-pmic-div.c

66

unsigned int ns = clkdiv->cxo_period_ns;

drivers/clk/qcom/clk-spmi-pmic-div.c

69

ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_EN_CTL,

drivers/clk/qcom/clk-spmi-pmic-div.c

82

static int spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable)

drivers/clk/qcom/clk-spmi-pmic-div.c

86

regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor);

drivers/clk/qcom/clk-spmi-pmic-div.c

89

return __spmi_pmic_clkdiv_set_enable_state(clkdiv, enable, div_factor);

drivers/clk/qcom/clk-spmi-pmic-div.c

94

struct clkdiv *clkdiv = to_clkdiv(hw);

drivers/clk/qcom/clk-spmi-pmic-div.c

98

spin_lock_irqsave(&clkdiv->lock, flags);

drivers/clk/qcom/clk-spmi-pmic-div.c

99

ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, true);

drivers/gpu/drm/bridge/tc358775.c

380

u16 dsiclk, clkdiv, byteclk, t1, t2, t3, vsdelay;

drivers/gpu/drm/bridge/tc358775.c

440

clkdiv = dsiclk / (tc->lvds_link == DUAL_LINK ? DIVIDE_BY_6 : DIVIDE_BY_3);

drivers/gpu/drm/bridge/tc358775.c

443

t2 = ((100000 / clkdiv)) * (hactive + hback_porch + hsync_len + hfront_porch) / 1000;

drivers/gpu/drm/bridge/tc358775.c

447

vsdelay = (clkdiv * (t1 + t3) / byteclk) - hback_porch - hsync_len - hactive;

drivers/gpu/drm/exynos/exynos7_drm_decon.c

196

u32 clkdiv;

drivers/gpu/drm/exynos/exynos7_drm_decon.c

199

clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk);

drivers/gpu/drm/exynos/exynos7_drm_decon.c

201

return (clkdiv < 0x100) ? clkdiv : 0xff;

drivers/gpu/drm/exynos/exynos7_drm_decon.c

208

u32 val, clkdiv;

drivers/gpu/drm/exynos/exynos7_drm_decon.c

254

clkdiv = decon_calc_clkdiv(ctx, mode);

drivers/gpu/drm/exynos/exynos7_drm_decon.c

255

if (clkdiv > 1) {

drivers/gpu/drm/exynos/exynos7_drm_decon.c

256

val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1);

drivers/gpu/drm/exynos/exynos_drm_fimd.c

196

u32 clkdiv;

drivers/gpu/drm/exynos/exynos_drm_fimd.c

422

u32 clkdiv;

drivers/gpu/drm/exynos/exynos_drm_fimd.c

448

clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk);

drivers/gpu/drm/exynos/exynos_drm_fimd.c

449

if (clkdiv >= 0x200) {

drivers/gpu/drm/exynos/exynos_drm_fimd.c

455

ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff;

drivers/gpu/drm/exynos/exynos_drm_fimd.c

590

if (ctx->clkdiv > 1)

drivers/gpu/drm/exynos/exynos_drm_fimd.c

591

val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;

drivers/gpu/drm/exynos/exynos_drm_vidi.c

46

unsigned int clkdiv;

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

208

unsigned int clkdiv;

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

211

clkdiv = 2; /* first try using a standard divider of 2 */

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

216

ret = clk_set_rate(priv->clk, pclk_rate * clkdiv);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

218

real_pclk_rate = clk_rate / clkdiv;

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

234

clkdiv = DIV_ROUND_CLOSEST(clk_rate, pclk_rate);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

243

real_pclk_rate = clk_rate / clkdiv;

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

255

tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv);

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

258

tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) |

drivers/hwmon/ltc4282.c

192

u32 clkdiv;

drivers/hwmon/ltc4282.c

195

ret = regmap_read(st->map, LTC4282_CLK_DIV, &clkdiv);

drivers/hwmon/ltc4282.c

199

clkdiv = FIELD_GET(LTC4282_CLKOUT_MASK, clkdiv);

drivers/hwmon/ltc4282.c

200

if (!clkdiv)

drivers/hwmon/ltc4282.c

202

if (clkdiv == LTC4282_CLKOUT_INT)

drivers/hwtracing/intel_th/pti.c

113

return scnprintf(buf, PAGE_SIZE, "%d\n", 1u << pti->clkdiv);

drivers/hwtracing/intel_th/pti.c

131

pti->clkdiv = val;

drivers/hwtracing/intel_th/pti.c

159

ctl |= pti->clkdiv << __ffs(PTI_CLKDIV);

drivers/hwtracing/intel_th/pti.c

183

pti->clkdiv = (ctl & PTI_CLKDIV) >> __ffs(PTI_CLKDIV);

drivers/hwtracing/intel_th/pti.c

188

if (!pti->clkdiv)

drivers/hwtracing/intel_th/pti.c

189

pti->clkdiv = 1;

drivers/hwtracing/intel_th/pti.c

27

unsigned int clkdiv;

drivers/i2c/busses/i2c-ibm_iic.c

153

out_8(&iic->clkdiv, dev->clckdiv);

drivers/i2c/busses/i2c-ibm_iic.c

91

in_8(&iic->extsts), in_8(&iic->clkdiv), in_8(&iic->xfrcnt),

drivers/i2c/busses/i2c-ibm_iic.h

33

u8 clkdiv;

drivers/iio/adc/lpc18xx_adc.c

133

unsigned int clkdiv;

drivers/iio/adc/lpc18xx_adc.c

176

clkdiv = DIV_ROUND_UP(rate, LPC18XX_ADC_CLK_TARGET);

drivers/iio/adc/lpc18xx_adc.c

178

adc->cr_reg = (clkdiv << LPC18XX_ADC_CR_CLKDIV_SHIFT) |

drivers/media/dvb-frontends/cx24120.c

1116

state->dnxt.clkdiv = (-(rate < 31000001) & 3) + 2;

drivers/media/dvb-frontends/cx24120.c

1119

state->dnxt.clkdiv = 3;

drivers/media/dvb-frontends/cx24120.c

1191

state->dcur.clkdiv, state->dcur.ratediv);

drivers/media/dvb-frontends/cx24120.c

1218

cmd.arg[13] = state->dcur.clkdiv;

drivers/media/dvb-frontends/cx24120.c

1227

ret = cx24120_writereg(state, CX24120_REG_CLKDIV, state->dcur.clkdiv);

drivers/media/dvb-frontends/cx24120.c

123

u8 clkdiv;

drivers/media/dvb-frontends/stv6111.c

366

u32 clkdiv = 0;

drivers/media/dvb-frontends/stv6111.c

386

if (clkdiv <= 3)

drivers/media/dvb-frontends/stv6111.c

387

state->reg[0x00] |= (clkdiv & 0x03);

drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c

124

writew(TWI_CLKDIV, &i2c->regs->clkdiv);

drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c

55

__le16 clkdiv;

drivers/mmc/host/atmel-mci.c

1428

int clkdiv;

drivers/mmc/host/atmel-mci.c

1451

clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;

drivers/mmc/host/atmel-mci.c

1452

if (clkdiv < 0) {

drivers/mmc/host/atmel-mci.c

1456

clkdiv = 0;

drivers/mmc/host/atmel-mci.c

1457

} else if (clkdiv > 511) {

drivers/mmc/host/atmel-mci.c

1461

clkdiv = 511;

drivers/mmc/host/atmel-mci.c

1463

host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)

drivers/mmc/host/atmel-mci.c

1464

| ATMCI_MR_CLKODD(clkdiv & 1);

drivers/mmc/host/atmel-mci.c

1466

clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;

drivers/mmc/host/atmel-mci.c

1467

if (clkdiv > 255) {

drivers/mmc/host/atmel-mci.c

1471

clkdiv = 255;

drivers/mmc/host/atmel-mci.c

1473

host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);

drivers/mmc/host/omap_hsmmc.c

538

unsigned long clkdiv;

drivers/mmc/host/omap_hsmmc.c

546

clkdiv = calc_divisor(host, ios);

drivers/mmc/host/omap_hsmmc.c

547

regval = regval | (clkdiv << 6) | (DTO << 16);

drivers/mmc/host/omap_hsmmc.c

572

if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)

drivers/mmc/host/sdhci-omap.c

701

unsigned long clkdiv;

drivers/mmc/host/sdhci-omap.c

708

clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock);

drivers/mmc/host/sdhci-omap.c

709

clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT;

drivers/mmc/host/sdhci-omap.c

710

sdhci_enable_clk(host, clkdiv);

drivers/mmc/host/sh_mmcif.c

485

unsigned int clkdiv;

drivers/mmc/host/sh_mmcif.c

497

clkdiv = 0;

drivers/mmc/host/sh_mmcif.c

516

clkdiv = i;

drivers/mmc/host/sh_mmcif.c

522

(best_freq >> (clkdiv + 1)), clk, best_freq, clkdiv);

drivers/mmc/host/sh_mmcif.c

525

clkdiv = clkdiv << 16;

drivers/mmc/host/sh_mmcif.c

527

clkdiv = CLK_SUP_PCLK;

drivers/mmc/host/sh_mmcif.c

529

clkdiv = (fls(DIV_ROUND_UP(current_clk, clk) - 1) - 1) << 16;

drivers/mmc/host/sh_mmcif.c

532

sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv);

drivers/mmc/host/sunplus-mmc.c

233

unsigned int clkdiv;

drivers/mmc/host/sunplus-mmc.c

243

clkdiv = (clk_get_rate(host->clk) + clk) / clk - 1;

drivers/mmc/host/sunplus-mmc.c

244

if (clkdiv > 0xfff)

drivers/mmc/host/sunplus-mmc.c

245

clkdiv = 0xfff;

drivers/mmc/host/sunplus-mmc.c

247

value |= FIELD_PREP(SPMMC_CLOCK_DIVISION, clkdiv);

drivers/mmc/host/sunplus-mmc.c

254

int clkdiv = FIELD_GET(SPMMC_CLOCK_DIVISION, readl(host->base + SPMMC_SD_CONFIG0_REG));

drivers/mmc/host/sunplus-mmc.c

255

int delay = clkdiv / 2 < 7 ? clkdiv / 2 : 7;

drivers/net/ethernet/chelsio/cxgb/subr.c

273

u32 clkdiv = bi->clock_elmer0 / (2 * bi->mdio_mdc) - 1;

drivers/net/ethernet/chelsio/cxgb/subr.c

275

V_MI1_MDI_ENABLE(bi->mdio_mdien) | V_MI1_CLK_DIV(clkdiv);

drivers/net/ethernet/chelsio/cxgb3/t3_hw.c

199

u32 clkdiv = adap->params.vpd.cclk / (2 * adap->params.vpd.mdc) - 1;

drivers/net/ethernet/chelsio/cxgb3/t3_hw.c

200

u32 val = F_PREEN | V_CLKDIV(clkdiv);

drivers/net/ethernet/ethoc.c

1184

u32 clkdiv = MIIMODER_CLKDIV(eth_clkfreq / 2500000 + 1);

drivers/net/ethernet/ethoc.c

1186

if (!clkdiv)

drivers/net/ethernet/ethoc.c

1187

clkdiv = 2;

drivers/net/ethernet/ethoc.c

1188

dev_dbg(&pdev->dev, "setting MII clkdiv to %u\n", clkdiv);

drivers/net/ethernet/ethoc.c

1191

clkdiv);

drivers/net/wireless/broadcom/brcm80211/include/chipcommon.h

79

u32 clkdiv; /* corerev >= 3 */

drivers/pwm/pwm-mediatek.c

150

u32 clkdiv, enable;

drivers/pwm/pwm-mediatek.c

187

clkdiv = FIELD_MAX(PWMCON_CLKDIV);

drivers/pwm/pwm-mediatek.c

190

clkdiv = ilog2(cnt_period) - ilog2(FIELD_MAX(PWMDWIDTH_PERIOD));

drivers/pwm/pwm-mediatek.c

191

cnt_period >>= clkdiv;

drivers/pwm/pwm-mediatek.c

194

clkdiv = 0;

drivers/pwm/pwm-mediatek.c

197

cnt_duty = mul_u64_u64_div_u64(wf->duty_length_ns, clk_rate, NSEC_PER_SEC) >> clkdiv;

drivers/pwm/pwm-mediatek.c

212

enable, clkdiv, cnt_period, cnt_duty);

drivers/pwm/pwm-mediatek.c

216

.con = clkdiv,

drivers/pwm/pwm-mediatek.c

229

u32 clkdiv, cnt_period, cnt_duty;

drivers/pwm/pwm-mediatek.c

239

clkdiv = FIELD_GET(PWMCON_CLKDIV, wfhw->con);

drivers/pwm/pwm-mediatek.c

250

DIV_ROUND_UP_ULL((u64)(cnt_period + 1) * NSEC_PER_SEC << clkdiv, clk_rate),

drivers/pwm/pwm-mediatek.c

252

DIV_ROUND_UP_ULL((u64)(cnt_duty + 1) * NSEC_PER_SEC << clkdiv, clk_rate),

drivers/pwm/pwm-mediatek.c

255

clkdiv = 0;

drivers/pwm/pwm-mediatek.c

272

pwm->hwpwm, wfhw->enable, clkdiv, cnt_period, cnt_duty, clk_rate,

drivers/pwm/pwm-mediatek.c

283

u32 enable, clkdiv, cnt_period, cnt_duty;

drivers/pwm/pwm-mediatek.c

303

clkdiv = FIELD_GET(PWMCON_CLKDIV, pwm_mediatek_readl(pc, pwm->hwpwm, PWMCON));

drivers/pwm/pwm-mediatek.c

309

.con = BIT(15) | clkdiv,

drivers/pwm/pwm-tiehrpwm.c

147

unsigned int clkdiv, hspclkdiv;

drivers/pwm/pwm-tiehrpwm.c

149

for (clkdiv = 0; clkdiv <= CLKDIV_MAX; clkdiv++) {

drivers/pwm/pwm-tiehrpwm.c

162

*prescale_div = (1 << clkdiv) *

drivers/pwm/pwm-tiehrpwm.c

165

*tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) |

drivers/spi/spi-cavium.c

36

unsigned int clkdiv;

drivers/spi/spi-cavium.c

48

clkdiv = p->sys_freq / (2 * xfer->speed_hz);

drivers/spi/spi-cavium.c

52

mpi_cfg.s.clkdiv = clkdiv;

drivers/spi/spi-cavium.h

111

uint64_t clkdiv:13;

drivers/spi/spi-cavium.h

118

uint64_t clkdiv:13;

drivers/spi/spi-cavium.h

142

uint64_t clkdiv:13;

drivers/spi/spi-cavium.h

150

uint64_t clkdiv:13;

drivers/spi/spi-cavium.h

180

uint64_t clkdiv:13;

drivers/spi/spi-cavium.h

187

uint64_t clkdiv:13;

drivers/spi/spi-cavium.h

217

uint64_t clkdiv:13;

drivers/spi/spi-cavium.h

46

uint64_t clkdiv:13;

drivers/spi/spi-cavium.h

78

uint64_t clkdiv:13;

drivers/spi/spi-cavium.h

85

uint64_t clkdiv:13;

drivers/spi/spi-pci1xxxx.c

139

u8 clkdiv;

drivers/spi/spi-pci1xxxx.c

451

u8 clkdiv, u32 len)

drivers/spi/spi-pci1xxxx.c

463

regval |= FIELD_PREP(SPI_MST_CTL_SPEED_MASK, clkdiv);

drivers/spi/spi-pci1xxxx.c

489

u8 clkdiv;

drivers/spi/spi-pci1xxxx.c

493

clkdiv = pci1xxxx_get_clock_div(par, xfer->speed_hz);

drivers/spi/spi-pci1xxxx.c

517

pci1xxxx_spi_setup(par, p->hw_inst, spi->mode, clkdiv, len);

drivers/spi/spi-pci1xxxx.c

562

p->clkdiv = pci1xxxx_get_clock_div(par, xfer->speed_hz);

drivers/spi/spi-pci1xxxx.c

570

pci1xxxx_spi_setup(par, p->hw_inst, p->mode, p->clkdiv, p->tx_sgl_len);

drivers/spi/spi-pci1xxxx.c

675

p->hw_inst, p->mode, p->clkdiv, p->tx_sgl_len);

drivers/tty/serial/amba-pl011.c

2097

unsigned int baud, quot, clkdiv;

drivers/tty/serial/amba-pl011.c

2101

clkdiv = 8;

drivers/tty/serial/amba-pl011.c

2103

clkdiv = 16;

drivers/tty/serial/amba-pl011.c

2109

port->uartclk / clkdiv);

drivers/video/fbdev/s3c-fb.c

1290

int clkdiv;

drivers/video/fbdev/s3c-fb.c

1296

clkdiv = s3c_fb_calc_pixclk(sfb, vmode->pixclock);

drivers/video/fbdev/s3c-fb.c

1301

if (clkdiv > 1)

drivers/video/fbdev/s3c-fb.c

1302

data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR;

drivers/video/fbdev/vga16fb.c

293

par->clkdiv = best->seq_clock_mode;

drivers/video/fbdev/vga16fb.c

542

seq[VGA_SEQ_CLOCK_MODE] = 0x01 | par->clkdiv;

drivers/video/fbdev/vga16fb.c

60

u8 misc, pel_msk, vss, clkdiv;

drivers/w1/masters/mxc_w1.c

116

clkdiv = DIV_ROUND_CLOSEST(clkrate, 1000000);

drivers/w1/masters/mxc_w1.c

117

clkrate /= clkdiv;

drivers/w1/masters/mxc_w1.c

132

writeb(clkdiv - 1, mdev->regs + MXC_W1_TIME_DIVIDER);

drivers/w1/masters/mxc_w1.c

95

unsigned int clkdiv;

sound/soc/adi/axi-spdif.c

103

AXI_SPDIF_CTRL_CLKDIV_MASK, clkdiv);

sound/soc/adi/axi-spdif.c

80

unsigned int clkdiv, stat;

sound/soc/adi/axi-spdif.c

97

clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(spdif->clk_ref),

sound/soc/adi/axi-spdif.c

99

clkdiv <<= AXI_SPDIF_CTRL_CLKDIV_OFFSET;

sound/soc/codecs/adau1701.c

299

static int adau1701_reset(struct snd_soc_component *component, unsigned int clkdiv,

sound/soc/codecs/adau1701.c

308

if (clkdiv != ADAU1707_CLKDIV_UNSET && adau1701->gpio_pll_mode) {

sound/soc/codecs/adau1701.c

309

switch (clkdiv) {

sound/soc/codecs/adau1701.c

331

adau1701->pll_clkdiv = clkdiv;

sound/soc/codecs/adau1701.c

346

if (clkdiv != ADAU1707_CLKDIV_UNSET) {

sound/soc/codecs/adau1701.c

438

unsigned int clkdiv = adau1701->sysclk / params_rate(params);

sound/soc/codecs/adau1701.c

447

if (clkdiv != adau1701->pll_clkdiv) {

sound/soc/codecs/adau1701.c

448

ret = adau1701_reset(component, clkdiv, params_rate(params));