clk_register_mux
return clk_register_mux(NULL, name,
clk_register_mux(dev, i2s_clk_names[i],
clk = clk_register_mux(NULL, clk_name, (const char **)&parents,
pll_mux_clk = clk_register_mux(&pdev->dev, "spll_mux_clk",
clk = clk_register_mux(NULL, clks[i].name,
ctrl->muxes[n] = clk_register_mux(NULL, desc[n].name,
return clk_register_mux(NULL, name, parent_names, num_parents,
clk = clk_register_mux(NULL, mux[i].name, mux[i].parents,
clk = clk_register_mux(NULL, list->name,
clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents,
clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents,
clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents,
clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents,
clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents,
clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents,
clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents,
clk = clk_register_mux(NULL, "pci_mclk", pci_parents,
clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents,
clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents,
clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk",
clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents,
clk = clk_register_mux(NULL, "uart1_mclk", uart_parents,
clk = clk_register_mux(NULL, "uart2_mclk", uart_parents,
clk = clk_register_mux(NULL, "uart3_mclk", uart_parents,
clk = clk_register_mux(NULL, "uart4_mclk", uart_parents,
clk = clk_register_mux(NULL, "uart5_mclk", uart_parents,
clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents,
clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
clk = clk_register_mux(NULL, "sys_mclk", sys_parents,
clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
clk = clk_register_mux(NULL, "uart1_mclk", uart1_parents,
clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents,
clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents,
clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents,
clk = clk_register_mux(NULL, "smii_pclk", smii0_parents,
clk = clk_register_mux(NULL, "uart1_clk", uartx_parents,
clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
clk = clk_register_mux(NULL, "uart4_clk", uartx_parents,
clk = clk_register_mux(NULL, "uart5_clk", uartx_parents,
clk = clk_register_mux(NULL, "uart6_clk", uartx_parents,
clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents,
clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents,
clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents,
clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents,
clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents,
clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents,
clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
clk = clk_register_mux(NULL, np->name, parents, num_parents,
clk = clk_register_mux(NULL, clk_name, parents, i,
clk = clk_register_mux(NULL, data->mux_name, mux_names,
clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
clk = clk_register_mux(NULL, "audio_mux", audio_parents,
clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
clock = clk_register_mux(d->dev, child_name, parents, 2, 0,
clk_register_mux(NULL, mux_name, parents, 4,
clk_register_mux(NULL, mux_name, parents, 4,
clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
clk_register_mux(NULL, "can_mux", periph_parents, 4,
clk_register_mux(NULL, "can0_mio_mux",
clk_register_mux(NULL, "can1_mio_mux",
clks[can0] = clk_register_mux(NULL, clk_output_name[can0],
clks[can1] = clk_register_mux(NULL, clk_output_name[can1],
clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
clk_register_mux(NULL, "cdev1_mux", cdev1_parents, 4, 0,
clk_register_mux(NULL, "cdev2_mux", cdev2_parents, 4, 0,
clk_register_mux(NULL, "csus_mux", csus_parents, 4, 0,
clk_mux = clk_register_mux(NULL, clk_mux_name, parent_names,
priv->clk_table[CLK_I2S_RCLK_SRC] = clk_register_mux(dev,