clk_hw_register_gate
hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "emmc_extclk_mux",
hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
hw = clk_hw_register_gate(dev, "mac3rclk", "mac34rclk", 0,
hw = clk_hw_register_gate(dev, "mac4rclk", "mac34rclk", 0,
clk_hw_register_gate(dev, "aux_uart", parent, 0, gate, 0, 0, NULL);
clk_hw_register_gate(dev, "aux_spi1", parent, 0, gate, 1, 0, NULL);
clk_hw_register_gate(dev, "aux_spi2", parent, 0, gate, 2, 0, NULL);
return clk_hw_register_gate(cprman->dev, gate_data->name,
clk = clk_hw_register_gate(&pdev->dev, entry->name, NULL,
hws[CLKID_GETH0 + n] = clk_hw_register_gate(NULL, gd->name,
hws[CLKID_GFX2DAXI + n] = clk_hw_register_gate(NULL, gd->name,
clk_hw_register_gate(NULL, gd->name,
hws[gd->idx] = clk_hw_register_gate(NULL, gd->name,
hw = clk_hw_register_gate(NULL, clks[i].name,
hw = clk_hw_register_gate(dev, name, parent_name, flags, reg,
ret = clk_hw_register_gate(NULL, "test_gate", NULL, 0, NULL,
ret = clk_hw_register_gate(&pdev->dev, "test_gate", NULL, 0, NULL,
ret = clk_hw_register_gate(NULL, "test_gate", "test_parent", 0, NULL,
hw = clk_hw_register_gate(NULL, "test_gate", NULL, 0, ctx->fake_mem, 7,
hw = clk_hw_register_gate(NULL, "test_gate", NULL, 0, ctx->fake_mem, 7,
hw = clk_hw_register_gate(NULL, "test_gate", NULL, 0, ctx->fake_mem, 2,
hw = clk_hw_register_gate(NULL, "test_gate", NULL, 0, ctx->fake_mem, 29,
clk_hw_register_gate(NULL, gd->name,
clk_hw_register_gate(NULL, "dfsdm1_apb", "apb2_div", 0,
clks[idx] = clk_hw_register_gate(
hws[PERIF_BANK + n] = clk_hw_register_gate(NULL, pclk[n].name,
hws[IMX7ULP_CLK_MMDC] = clk_hw_register_gate(NULL, "mmdc", "nic1_clk", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
hws[i] = clk_hw_register_gate(dev, data->name, data->parent_names[0],
return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk",
clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus",
clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s",
clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(dev, "pcm_bus",
clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(dev, "sclk_pcm",
clk_table[EXYNOS_ADMA] = clk_hw_register_gate(dev, "adma",
clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss",
clk_table[CLK_HCLK_I2S] = clk_hw_register_gate(NULL, "hclk_i2s_audss",
clk_table[CLK_HCLK_UART] = clk_hw_register_gate(NULL, "hclk_uart_audss",
clk_table[CLK_HCLK_HWA] = clk_hw_register_gate(NULL, "hclk_hwa_audss",
clk_table[CLK_HCLK_DMA] = clk_hw_register_gate(NULL, "hclk_dma_audss",
clk_table[CLK_HCLK_BUF] = clk_hw_register_gate(NULL, "hclk_buf_audss",
clk_table[CLK_HCLK_RP] = clk_hw_register_gate(NULL, "hclk_rp_audss",
clk_hw = clk_hw_register_gate(ctx->dev, list->name,
return clk_hw_register_gate(dev,
hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1",
hws[CLK_GATE_FIXED] = clk_hw_register_gate(NULL, "oscout1",
return clk_hw_register_gate(dev, clk_name, parent_name,