clk_hw_get_rate
pr = clk_hw_get_rate(pc);
parent_rate = clk_hw_get_rate(parent);
master->pms.parent_rate = clk_hw_get_rate(parent_hw);
master->pms.parent_rate = clk_hw_get_rate(parent_hw);
parent_rate = clk_hw_get_rate(parent);
parent_rate = clk_hw_get_rate(parent);
unsigned long parent_rate = clk_hw_get_rate(parent);
pll->pms.parent_rate = clk_hw_get_rate(parent_hw);
prog->pms.parent_rate = clk_hw_get_rate(parent_hw);
parent_rate = clk_hw_get_rate(parent);
parent_rate = clk_hw_get_rate(parent_hw);
usb->pms.parent_rate = clk_hw_get_rate(parent_hw);
parent_rate = clk_hw_get_rate(hw_parent);
parent_rate = clk_hw_get_rate(hw_parent);
parent_rate = clk_hw_get_rate(hw_parent);
ret = ccu_div_var_update_clkdiv(div, clk_hw_get_rate(parent_hw),
ret = ccu_pll_reset(pll, clk_hw_get_rate(parent_hw),
clk_hw_get_rate(hw),
*prate = clk_hw_get_rate(parent);
parent_rate = clk_hw_get_rate(current_parent);
parent_rate = clk_hw_get_rate(parent);
if (rate == clk_hw_get_rate(hw))
return clk_hw_get_rate(hw);
req->best_parent_rate = clk_hw_get_rate(parent_hw);
parent_rate = clk_hw_get_rate(parent);
unsigned long prate = clk_hw_get_rate(parent);
unsigned long rate = clk_hw_get_rate(hw);
np, clk_hw_get_rate(&ksc->clks[K210_CLK_CPU].hw) / 1000000);
if (clk_hw_get_rate(parent) / req->rate <= DIV_MAX) {
req->best_parent_rate = clk_hw_get_rate(parent);
parent_rate = clk_hw_get_rate(parent);
*prate = clk_hw_get_rate(parent);
const unsigned long xosc_rate = clk_hw_get_rate(clk_xosc);
parent_rate = clk_hw_get_rate(parent);
EXPORT_SYMBOL_GPL(clk_hw_get_rate);
lpcg_e10858_writel(clk_hw_get_rate(hw), clk->reg, reg);
lpcg_e10858_writel(clk_hw_get_rate(hw), clk->reg, reg);
clk->rate = clk_hw_get_rate(&clk->hw);
old_rate = clk_hw_get_rate(hw);
parent_rate = clk_hw_get_rate(parent_clk);
return clk_hw_get_rate(hw);
rate = clk_hw_get_rate(hw);
parent_rate = clk_hw_get_rate(parent);
parent_rate = clk_hw_get_rate(parent);
parent_rate = clk_hw_get_rate(parent);
parent_rate = clk_hw_get_rate(parent);
parent_rate = clk_hw_get_rate(parent);
cur_rate = clk_hw_get_rate(hwclk);
o = clk_hw_get_rate(osc_hw); /* must be in range 1..20 MHz */
vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw),
curr_vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
freq_hz = alpha_pll_round_rate(calibration_freq, clk_hw_get_rate(parent),
freq_hz = alpha_pll_round_rate(clk_hw_get_rate(hw),
clk_hw_get_rate(parent), &l, &a, ALPHA_REG_BITWIDTH);
clk_hw_get_name(hw), clk_hw_get_rate(hw), freq_hz);
rate = clk_hw_get_rate(hw);
rate = clk_hw_get_rate(p);
src_rate = clk_hw_get_rate(req->best_parent_hw);
if (req->rate == clk_hw_get_rate(xo)) {
p0_rate = clk_hw_get_rate(p0);
if (clk_hw_get_rate(p2) == parent_req.rate)
prate = clk_hw_get_rate(p);
rate = clk_hw_get_rate(p);
parent_rate = clk_hw_get_rate(p);
rate = clk_hw_get_rate(p);
req->best_parent_rate = clk_hw_get_rate(req->best_parent_hw);
unsigned long parent_rate = clk_hw_get_rate(parent);
unsigned long parent_rate = clk_hw_get_rate(p);
unsigned long parent_rate = clk_hw_get_rate(parent);
req->best_parent_rate = clk_hw_get_rate(p_hw);
prate = clk_hw_get_rate(parent);
zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) /
zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) /
unsigned long rate = clk_hw_get_rate(hw);
unsigned long rate = clk_hw_get_rate(hw);
drate = clk_hw_get_rate(hw);
drate = clk_hw_get_rate(hw);
drate = clk_hw_get_rate(hw);
p_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
p_parent_rate = clk_hw_get_rate(p_parent);
unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
divp_rate = clk_hw_get_rate(clk_divp);
unsigned long alt_prate = clk_hw_get_rate(alt_parent);
finpll_f = clk_hw_get_rate(ctx->clk_data.hws[parent]);
if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) {
if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24000000)
if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) {
clk_hw_get_rate(hws[CLK_SCLK_APLL]),
clk_hw_get_rate(hws[CLK_SCLK_MPLL]),
clk_hw_get_rate(hws[CLK_SCLK_EPLL]),
clk_hw_get_rate(hws[CLK_SCLK_VPLL]),
clk_hw_get_rate(hws[CLK_DIV_CORE2]));
if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) {
if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24 * MHZ)
clk_hw_get_rate(hws[CLK_DIV_ARM2]));
if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) {
clk_hw_get_rate(hws[MOUT_APLL]),
clk_hw_get_rate(hws[MOUT_MPLL]),
clk_hw_get_rate(hws[MOUT_EPLL]),
clk_hw_get_rate(hws[ARMCLK]));
clk_hw_get_rate(hws[MOUT_APLL]),
clk_hw_get_rate(hws[MOUT_MPLL]),
clk_hw_get_rate(hws[MOUT_EPLL]),
clk_hw_get_rate(hws[MOUT_VPLL]));
tmp_req.best_parent_rate = clk_hw_get_rate(best_parent);
tmp_req.best_parent_rate = clk_hw_get_rate(parent);
parent_rate = clk_hw_get_rate(parent);
clk_hw_get_rate(clk_hw_get_parent(clk_hw_get_parent(hw)));
clk_hw_get_rate(parent));
best_parent_rate = clk_hw_get_rate(best_parent);
parent_rate = clk_hw_get_rate(parent);
grandparent_rate = clk_hw_get_rate(grandparent);
parent_rate = clk_hw_get_rate(parent);
grandparent_rate = clk_hw_get_rate(grandparent);
parent_rate = clk_hw_get_rate(parent);
parent_rate = clk_hw_get_rate(parent);
parent_rate = clk_hw_get_rate(parent);
rate = clk_hw_get_rate(clk_dev->hw);
unsigned long parent_rate = clk_hw_get_rate(parent);
unsigned long rate = clk_hw_get_rate(hw);
unsigned long parent_rate = clk_hw_get_rate(parent);
unsigned long rate = clk_hw_get_rate(hw);
input_rate = clk_hw_get_rate(osc);
input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
input_rate = clk_hw_get_rate(__clk_get_hw(osc));
input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
req->rate = clk_hw_get_rate(hw);
input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
unsigned long parent_rate = clk_hw_get_rate(parent);
unsigned long rate = clk_hw_get_rate(hw);
pllp_rate = clk_hw_get_rate(pllp_hw);
parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
req->rate = clk_hw_get_rate(hw);
if (clk_hw_get_rate(hw) == rate)
parent_rate = clk_hw_get_rate(parent_hw);
if (config->parent_rate != clk_hw_get_rate(old)) {
config->parent_rate = clk_hw_get_rate(parent);
parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
req->rate = clk_hw_get_rate(hw);
input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
return clk_hw_get_rate(dd->clk_bypass);
dpll_clk = (u64)clk_hw_get_rate(dd->clk_ref) * dpll_mult;
ref_rate = clk_hw_get_rate(dd->clk_ref);
fint = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)) / n;
clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw));
clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw));
ref_rate = clk_hw_get_rate(dd->clk_ref);
if (clk_hw_get_rate(hw) == clk_hw_get_rate(dd->clk_bypass)) {
if (clk_hw_get_rate(dd->clk_bypass) == req->rate &&
fint = clk_hw_get_rate(clk->dpll_data->clk_ref) / n;
if (clk_hw_get_rate(dd->clk_bypass) == req->rate &&
fint = clk_hw_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1);
cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
pll_in_khz = clk_hw_get_rate(hwclk) / 1000;
parent_rate = clk_hw_get_rate(parent);
prate = clk_hw_get_rate(parent);
req->best_parent_rate = clk_hw_get_rate(best_parent);
parent_rate = clk_hw_get_rate(parent);
unsigned long clk_hw_get_rate(const struct clk_hw *hw);