drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1003

if (tiling_mode[i] == bw_def_linear) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1107

if (data->scatter_gather_enable_for_pipe[i] == 1 && tiling_mode[i] != bw_def_linear) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

1110

else if (data->scatter_gather_enable_for_pipe[i] == 1 && tiling_mode[i] == bw_def_linear && bw_equ(bw_mod((bw_mul(data->pitch_in_pixels_after_surface_type[i], bw_int_to_fixed(data->bytes_per_pixel[i]))), data->inefficient_linear_pitch_in_bytes), bw_int_to_fixed(0))) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

274

tiling_mode[0] = bw_def_linear;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

275

tiling_mode[1] = bw_def_linear;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

276

tiling_mode[2] = bw_def_linear;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

277

tiling_mode[3] = bw_def_linear;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

339

tiling_mode[i] = bw_def_linear;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

386

tiling_mode[maximum_number_of_surfaces - 2] = bw_def_linear;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

387

tiling_mode[maximum_number_of_surfaces - 1] = bw_def_linear;

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

594

if ((bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270))) && (tiling_mode[i] == bw_def_linear || data->stereo_mode[i] != bw_def_mono)) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

693

else if (tiling_mode[i] == bw_def_linear) {

drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c

874

if ((dceip->dmif_pipe_en_fbc_chunk_tracker + 3 == i && fbc_enabled == 0 && tiling_mode[i] != bw_def_linear)) {