drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1329

void hwss_add_optc_pipe_control_lock(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1346

void hwss_add_hubp_set_flip_control_gsl(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1361

void hwss_add_hubp_program_triplebuffer(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1378

void hwss_add_hubp_update_plane_addr(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1393

void hwss_add_dpp_set_input_transfer_func(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1410

void hwss_add_dpp_program_gamut_remap(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1423

void hwss_add_dpp_program_bias_and_scale(struct block_sequence_state *seq_state, struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1435

void hwss_add_optc_program_manual_trigger(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1448

void hwss_add_dpp_set_output_transfer_func(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1465

void hwss_add_mpc_update_visual_confirm(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1482

void hwss_add_mpc_power_on_mpc_mem_pwr(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1499

void hwss_add_mpc_set_output_csc(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1518

void hwss_add_mpc_set_ocsc_default(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1537

void hwss_add_dmub_send_dmcub_cmd(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1554

void hwss_add_dmub_subvp_save_surf_addr(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1571

void hwss_add_hubp_wait_for_dcc_meta_prop(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1586

void hwss_add_hubp_wait_pipe_read_start(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1599

void hwss_add_hws_apply_update_flags_for_phantom(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1612

void hwss_add_hws_update_phantom_vp_position(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1629

void hwss_add_optc_set_odm_combine(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1647

void hwss_add_optc_set_odm_bypass(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1670

void hwss_add_tg_program_global_sync(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1693

void hwss_add_tg_wait_for_state(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1708

void hwss_add_tg_set_vtg_params(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1725

void hwss_add_tg_setup_vertical_interrupt2(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1739

void hwss_add_dpp_set_hdr_multiplier(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1753

void hwss_add_hubp_program_det_size(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1767

void hwss_add_hubp_program_mcache_id(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1779

void hwss_add_hubbub_force_pstate_change_control(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1796

void hwss_add_hubp_program_det_segments(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1813

void hwss_add_opp_set_dyn_expansion(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1832

void hwss_add_opp_program_fmt(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1846

void hwss_add_opp_program_left_edge_extra_pixel(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1863

void hwss_add_abm_set_pipe(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1878

void hwss_add_abm_set_level(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1893

void hwss_add_tg_enable_crtc(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1906

void hwss_add_hubp_wait_flip_pending(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1923

void hwss_add_tg_wait_double_buffer_pending(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3149

void hwss_add_dccg_set_dto_dscclk(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3161

void hwss_add_dsc_calculate_and_set_config(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3173

void hwss_add_mpc_remove_mpcc(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3185

void hwss_add_opp_set_mpcc_disconnect_pending(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3197

void hwss_add_hubp_disconnect(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3207

void hwss_add_dsc_enable_with_opp(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3217

void hwss_add_tg_set_dsc_config(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3229

void hwss_add_dsc_disconnect(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3239

void hwss_add_dc_set_optimized_required(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3250

void hwss_add_abm_set_immediate_disable(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3261

void hwss_add_opp_set_disp_pattern_generator(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3290

void hwss_add_mpc_update_blending(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3307

void hwss_add_mpc_insert_plane(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3332

void hwss_add_mpc_assert_idle_mpcc(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3347

void hwss_add_hubp_set_blank(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3359

void hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3373

void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3385

void hwss_add_dwbc_update(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3397

void hwss_add_mcif_wb_config_buf(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3411

void hwss_add_mcif_wb_config_arb(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3423

void hwss_add_mcif_wb_enable(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3433

void hwss_add_mcif_wb_disable(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3443

void hwss_add_mpc_set_dwb_mux(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3457

void hwss_add_mpc_disable_dwb_mux(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3469

void hwss_add_dwbc_enable(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3481

void hwss_add_dwbc_disable(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3491

void hwss_add_tg_set_gsl(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3503

void hwss_add_tg_set_gsl_source_select(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3517

void hwss_add_hubp_update_mall_sel(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3531

void hwss_add_hubp_prepare_subvp_buffering(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3543

void hwss_add_hubp_set_blank_en(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3555

void hwss_add_hubp_disable_control(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3567

void hwss_add_hubbub_soft_reset(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3581

void hwss_add_hubp_clk_cntl(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3593

void hwss_add_dpp_dppclk_control(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3607

void hwss_add_disable_phantom_crtc(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3617

void hwss_add_dsc_pg_status(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3631

void hwss_add_dsc_wait_disconnect_pending_clear(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3643

void hwss_add_dsc_disable(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3655

void hwss_add_dccg_set_ref_dscclk(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3669

void hwss_add_dpp_root_clock_control(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3683

void hwss_add_dpp_pg_control(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3697

void hwss_add_hubp_pg_control(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3711

void hwss_add_hubp_init(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3721

void hwss_add_hubp_reset(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3731

void hwss_add_dpp_reset(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3741

void hwss_add_opp_pipe_clock_control(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3753

void hwss_add_hubp_set_vm_system_aperture_settings(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3769

void hwss_add_hubp_set_flip_int(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3779

void hwss_add_dccg_update_dpp_dto(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3793

void hwss_add_hubp_vtg_sel(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3805

void hwss_add_hubp_setup2(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3821

void hwss_add_hubp_setup(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3839

void hwss_add_hubp_set_unbounded_requesting(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3851

void hwss_add_hubp_setup_interdependent2(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3863

void hwss_add_hubp_setup_interdependent(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3877

void hwss_add_hubp_program_surface_config(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3901

void hwss_add_dpp_setup_dpp(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3911

void hwss_add_dpp_set_cursor_matrix(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3925

void hwss_add_dpp_set_scaler(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3937

void hwss_add_hubp_mem_program_viewport(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3951

void hwss_add_abort_cursor_offload_update(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3963

void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3975

void hwss_add_set_cursor_position(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3987

void hwss_add_set_cursor_sdr_white_level(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3999

void hwss_add_program_output_csc(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4017

void hwss_add_phantom_hubp_post_enable(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4027

void hwss_add_update_force_pstate(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4039

void hwss_add_hubbub_apply_dedcn21_147_wa(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4049

void hwss_add_hubbub_allow_self_refresh_control(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4063

void hwss_add_tg_get_frame_count(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1623

struct pipe_ctx *otg_master, struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1715

struct pipe_ctx *otg_master, struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2263

struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3045

struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3085

struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3127

struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3206

struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3264

struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3297

struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3322

struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3356

struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3429

struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3482

struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3527

struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3588

struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3771

struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3871

struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3900

struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3913

struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3930

struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3992

struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4006

struct block_sequence_state *seq_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

107

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

123

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

127

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

132

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

140

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

147

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

152

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

158

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

164

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

170

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

175

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

181

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

186

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

190

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

196

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

199

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

202

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

205

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

208

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

211

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

87

struct pipe_ctx *otg_master, struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1009

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1030

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1275

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1282

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1288

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1604

void hwss_add_optc_pipe_control_lock(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1607

void hwss_add_hubp_set_flip_control_gsl(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1610

void hwss_add_hubp_program_triplebuffer(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1613

void hwss_add_hubp_update_plane_addr(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1616

void hwss_add_dpp_set_input_transfer_func(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1619

void hwss_add_dpp_program_gamut_remap(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1622

void hwss_add_dpp_program_bias_and_scale(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1625

void hwss_add_optc_program_manual_trigger(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1628

void hwss_add_dpp_set_output_transfer_func(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1631

void hwss_add_mpc_update_visual_confirm(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1634

void hwss_add_mpc_power_on_mpc_mem_pwr(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1637

void hwss_add_mpc_set_output_csc(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1640

void hwss_add_mpc_set_ocsc_default(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1643

void hwss_add_dmub_send_dmcub_cmd(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1646

void hwss_add_dmub_subvp_save_surf_addr(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1649

void hwss_add_hubp_wait_for_dcc_meta_prop(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1652

void hwss_add_hubp_wait_pipe_read_start(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1655

void hwss_add_hws_apply_update_flags_for_phantom(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1658

void hwss_add_hws_update_phantom_vp_position(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1661

void hwss_add_optc_set_odm_combine(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1665

void hwss_add_optc_set_odm_bypass(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1668

void hwss_add_tg_program_global_sync(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1676

void hwss_add_tg_wait_for_state(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1679

void hwss_add_tg_set_vtg_params(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1682

void hwss_add_tg_setup_vertical_interrupt2(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1685

void hwss_add_dpp_set_hdr_multiplier(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1688

void hwss_add_hubp_program_det_size(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1691

void hwss_add_hubp_program_mcache_id(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1694

void hwss_add_hubbub_force_pstate_change_control(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1697

void hwss_add_hubp_program_det_segments(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1700

void hwss_add_opp_set_dyn_expansion(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1704

void hwss_add_opp_program_fmt(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1708

void hwss_add_abm_set_pipe(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1711

void hwss_add_abm_set_level(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1714

void hwss_add_tg_enable_crtc(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1717

void hwss_add_hubp_wait_flip_pending(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1720

void hwss_add_tg_wait_double_buffer_pending(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1723

void hwss_add_dccg_set_dto_dscclk(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1726

void hwss_add_dsc_calculate_and_set_config(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1729

void hwss_add_mpc_remove_mpcc(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1732

void hwss_add_opp_set_mpcc_disconnect_pending(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1735

void hwss_add_hubp_disconnect(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1738

void hwss_add_dsc_enable_with_opp(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1741

void hwss_add_dsc_disconnect(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1744

void hwss_add_dc_set_optimized_required(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1747

void hwss_add_abm_set_immediate_disable(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1750

void hwss_add_opp_set_disp_pattern_generator(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1761

void hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1766

void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1770

void hwss_add_dwbc_update(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1774

void hwss_add_mcif_wb_config_buf(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1779

void hwss_add_mcif_wb_config_arb(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1783

void hwss_add_mcif_wb_enable(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1786

void hwss_add_mcif_wb_disable(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1789

void hwss_add_mpc_set_dwb_mux(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1794

void hwss_add_mpc_disable_dwb_mux(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1798

void hwss_add_dwbc_enable(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1802

void hwss_add_dwbc_disable(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1805

void hwss_add_tg_set_gsl(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1809

void hwss_add_tg_set_gsl_source_select(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1814

void hwss_add_hubp_update_mall_sel(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1819

void hwss_add_hubp_prepare_subvp_buffering(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1823

void hwss_add_hubp_set_blank_en(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1827

void hwss_add_hubp_disable_control(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1831

void hwss_add_hubbub_soft_reset(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1836

void hwss_add_hubp_clk_cntl(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1840

void hwss_add_dpp_dppclk_control(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1845

void hwss_add_disable_phantom_crtc(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1848

void hwss_add_dsc_pg_status(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1853

void hwss_add_dsc_wait_disconnect_pending_clear(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1857

void hwss_add_dsc_disable(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1861

void hwss_add_dccg_set_ref_dscclk(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1866

void hwss_add_dpp_root_clock_control(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1871

void hwss_add_dpp_pg_control(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1876

void hwss_add_hubp_pg_control(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1881

void hwss_add_hubp_set_blank(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1885

void hwss_add_hubp_init(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1888

void hwss_add_hubp_reset(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1891

void hwss_add_dpp_reset(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1894

void hwss_add_opp_pipe_clock_control(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1898

void hwss_add_hubp_set_vm_system_aperture_settings(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1904

void hwss_add_hubp_set_flip_int(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1907

void hwss_add_dccg_update_dpp_dto(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1912

void hwss_add_hubp_vtg_sel(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1916

void hwss_add_hubp_setup2(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1922

void hwss_add_hubp_setup(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1929

void hwss_add_hubp_set_unbounded_requesting(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1933

void hwss_add_hubp_setup_interdependent2(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1937

void hwss_add_hubp_setup_interdependent(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1941

void hwss_add_hubp_program_surface_config(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1951

void hwss_add_dpp_setup_dpp(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1954

void hwss_add_dpp_set_cursor_matrix(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1959

void hwss_add_mpc_update_blending(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1964

void hwss_add_mpc_assert_idle_mpcc(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1968

void hwss_add_mpc_insert_plane(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1977

void hwss_add_dpp_set_scaler(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1981

void hwss_add_hubp_mem_program_viewport(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1986

void hwss_add_abort_cursor_offload_update(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1990

void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1994

void hwss_add_set_cursor_position(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1998

void hwss_add_set_cursor_sdr_white_level(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2002

void hwss_add_program_output_csc(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2009

void hwss_add_phantom_hubp_post_enable(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2012

void hwss_add_update_force_pstate(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2016

void hwss_add_hubbub_apply_dedcn21_147_wa(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2019

void hwss_add_hubbub_allow_self_refresh_control(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2024

void hwss_add_tg_get_frame_count(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2028

void hwss_add_tg_set_dsc_config(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2033

void hwss_add_opp_program_left_edge_extra_pixel(struct block_sequence_state *seq_state,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

110

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

120

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

131

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

161

struct pipe_ctx *pipe_ctx, struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

169

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

173

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

176

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

184

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

200

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

87

struct block_sequence_state *seq_state);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

90

struct block_sequence_state *seq_state);