at91_adc_writel
at91_adc_writel(st, ACR, acr);
at91_adc_writel(st, IER, AT91_SAMA5D2_IER_PEN);
at91_adc_writel(st, TRGR, status);
at91_adc_writel(st, IER, AT91_SAMA5D2_IER_GOVRE);
at91_adc_writel(st, CHER, BIT(chan->channel));
at91_adc_writel(st, IER, AT91_SAMA5D2_IER_DRDY);
at91_adc_writel(st, CHDR, BIT(chan->channel));
at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_DRDY);
at91_adc_writel(st, CR, AT91_SAMA5D2_CR_START);
at91_adc_writel(st, MR, mr);
at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_PEN);
at91_adc_writel(st, IER, AT91_SAMA5D2_IER_NOPEN |
at91_adc_writel(st, TRGR, AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC |
at91_adc_writel(st, TRGR, AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER);
at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_NOPEN |
at91_adc_writel(st, IER, AT91_SAMA5D2_IER_PEN);
at91_adc_writel(st, CHER, BIT(chan->channel));
at91_adc_writel(st, TEMPMR, AT91_SAMA5D2_TEMPMR_TEMPON);
at91_adc_writel(st, CR, AT91_SAMA5D2_CR_START);
at91_adc_writel(st, TEMPMR, 0U);
at91_adc_writel(st, CHDR, BIT(chan->channel));
at91_adc_writel(st, ACR, tmp);
at91_adc_writel(st, ACR, tmp);
at91_adc_writel(st, CR, AT91_SAMA5D2_CR_SWRST);
at91_adc_writel(st, EOC_IDR, 0xffffffff);
at91_adc_writel(st, IDR, 0xffffffff);
at91_adc_writel(st, MR,
at91_adc_writel(st, CR, AT91_SAMA5D2_CR_SWRST);
at91_adc_writel(st, COR, cur_cor | cor);
at91_adc_writel(st, COR, cur_cor & ~cor);
at91_adc_writel(st, IDR, BIT(channel));
at91_adc_writel(st, IER, BIT(channel));
at91_adc_writel(st, EOC_IER, BIT(channel));
at91_adc_writel(st, EMR, emr);
at91_adc_writel(st, IDR,
at91_adc_writel(st, TSMR, 0);
at91_adc_writel(st, TSMR, tsmr);
at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
at91_adc_writel(st, AT91_ADC_MR, reg);
at91_adc_writel(st, AT91_ADC_MR, reg);
at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN
at91_adc_writel(st, st->registers->trigger_register,
at91_adc_writel(st, AT91_ADC_MR, reg);
at91_adc_writel(st, st->registers->trigger_register,
at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN
at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN |
at91_adc_writel(st, st->registers->trigger_register,
at91_adc_writel(st, st->registers->trigger_register, 0);
at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN |
at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
at91_adc_writel(st, reg->trigger_register,
at91_adc_writel(st, AT91_ADC_CHER,
at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
at91_adc_writel(st, reg->trigger_register,
at91_adc_writel(st, AT91_ADC_CHDR,
at91_adc_writel(st, AT91_ADC_CHER,
at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel));
at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
at91_adc_writel(st, AT91_ADC_CHDR,
at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel));
at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
at91_adc_writel(st, AT91_ADC_MR, reg);
at91_adc_writel(st, AT91_ADC_TSR, reg);
at91_adc_writel(st, AT91_ADC_TSMR, reg);
at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity