drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

20224

#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

18396

#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

17287

#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

19526

#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

13981

#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

13187

#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

12952

#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

12815

#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

14115

#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

13980

#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

3911

#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

16345

#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16