drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

20361

#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

18531

#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

17427

#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

19668

#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

14121

#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

13325

#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

13095

#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

12948

#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

14248

#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

14113

#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

4046

#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

16482

#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

3386

#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

4004

#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

4526

#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc