drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h

142

#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h

4145

#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h

4133

#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h

3351

#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h

4267

#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h

3965

#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8

drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_sh_mask.h

40

#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L

drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_sh_mask.h

904

#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L

drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_sh_mask.h

377

#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L

drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_sh_mask.h

858

#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L