drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

549

#define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

768

#define UVD_VCPU_CNTL__DBG_MUX_MASK 0x0000e000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

553

#define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

585

#define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

587

#define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

4107

#define UVD_VCPU_CNTL__DBG_MUX_MASK 0x0000E000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

3770

#define UVD_VCPU_CNTL__DBG_MUX_MASK 0x0000E000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

5274

#define UVD_VCPU_CNTL__DBG_MUX_MASK 0x0000E000L